OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_wbmux.v] - Blame information for rev 171

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Write-back Mux                                     ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  CPU's write-back stage of the pipeline                      ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 142 marcus.erl
// $Log: or1200_wbmux.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// No update 
49
//
50
// Revision 1.3  2004/06/08 18:17:36  lampret
51
// Non-functional changes. Coding style fixes.
52
//
53 10 unneback
// Revision 1.2  2002/03/29 15:16:56  lampret
54
// Some of the warnings fixed.
55
//
56
// Revision 1.1  2002/01/03 08:16:15  lampret
57
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
58
//
59
// Revision 1.8  2001/10/21 17:57:16  lampret
60
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
61
//
62
// Revision 1.7  2001/10/14 13:12:10  lampret
63
// MP3 version.
64
//
65
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
66
// no message
67
//
68
// Revision 1.2  2001/08/09 13:39:33  lampret
69
// Major clean-up.
70
//
71
// Revision 1.1  2001/07/20 00:46:23  lampret
72
// Development version of RTL. Libraries are missing.
73
//
74
//
75
 
76
// synopsys translate_off
77
`include "timescale.v"
78
// synopsys translate_on
79
`include "or1200_defines.v"
80
 
81
module or1200_wbmux(
82
        // Clock and reset
83
        clk, rst,
84
 
85
        // Internal i/f
86
        wb_freeze, rfwb_op,
87
        muxin_a, muxin_b, muxin_c, muxin_d,
88
        muxout, muxreg, muxreg_valid
89
);
90
 
91
parameter width = `OR1200_OPERAND_WIDTH;
92
 
93
//
94
// I/O
95
//
96
 
97
//
98
// Clock and reset
99
//
100
input                           clk;
101
input                           rst;
102
 
103
//
104
// Internal i/f
105
//
106
input                           wb_freeze;
107
input   [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
108
input   [width-1:0]              muxin_a;
109
input   [width-1:0]              muxin_b;
110
input   [width-1:0]              muxin_c;
111
input   [width-1:0]              muxin_d;
112
output  [width-1:0]              muxout;
113
output  [width-1:0]              muxreg;
114
output                          muxreg_valid;
115
 
116
//
117
// Internal wires and regs
118
//
119
reg     [width-1:0]              muxout;
120
reg     [width-1:0]              muxreg;
121
reg                             muxreg_valid;
122
 
123
//
124
// Registered output from the write-back multiplexer
125
//
126
always @(posedge clk or posedge rst) begin
127
        if (rst) begin
128
                muxreg <= #1 32'd0;
129
                muxreg_valid <= #1 1'b0;
130
        end
131
        else if (!wb_freeze) begin
132
                muxreg <= #1 muxout;
133
                muxreg_valid <= #1 rfwb_op[0];
134
        end
135
end
136
 
137
//
138
// Write-back multiplexer
139
//
140
always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
141
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
142
        case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
143
`else
144
        case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
145
`endif
146
                2'b00: muxout = muxin_a;
147
                2'b01: begin
148
                        muxout = muxin_b;
149
`ifdef OR1200_VERBOSE
150
// synopsys translate_off
151
                        $display("  WBMUX: muxin_b %h", muxin_b);
152
// synopsys translate_on
153
`endif
154
                end
155
                2'b10: begin
156
                        muxout = muxin_c;
157
`ifdef OR1200_VERBOSE
158
// synopsys translate_off
159
                        $display("  WBMUX: muxin_c %h", muxin_c);
160
// synopsys translate_on
161
`endif
162
                end
163
                2'b11: begin
164
                        muxout = muxin_d + 32'h8;
165
`ifdef OR1200_VERBOSE
166
// synopsys translate_off
167
                        $display("  WBMUX: muxin_d %h", muxin_d + 4'h8);
168
// synopsys translate_on
169
`endif
170
                end
171
        endcase
172
end
173
 
174
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.