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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Blame information for rev 55

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Xilinx Virtex RAM 32x8D                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Virtex dual-port memory                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`ifdef OR1200_XILINX_RAM32X1D
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
module or1200_xcv_ram32x8d
(
    DPO,
    SPO,
    A,
    D,
    DPRA,
    WCLK,
    WE
);
output  [7:0]   DPO;
output  [7:0]   SPO;
input   [4:0]   A;
input   [4:0]   DPRA;
input   [7:0]   D;
input           WCLK;
input           WE;
 
wire    [7:0]   DPO_0;
wire    [7:0]   SPO_0;
 
wire    [7:0]   DPO_1;
wire    [7:0]   SPO_1;
 
wire            WE_0 ;
wire            WE_1 ;
 
assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;
assign SPO = A[4] ? SPO_1 : SPO_0 ;
 
assign WE_0 = !A[4] && WE ;
assign WE_1 =  A[4] && WE ;
 
RAM16X1D ram32x1d_0_0(
        .DPO(DPO_0[0]),
        .SPO(SPO_0[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_0_1(
        .DPO(DPO_0[1]),
        .SPO(SPO_0[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_0_2(
        .DPO(DPO_0[2]),
        .SPO(SPO_0[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_0_3(
        .DPO(DPO_0[3]),
        .SPO(SPO_0[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_0_4(
        .DPO(DPO_0[4]),
        .SPO(SPO_0[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_0_5(
        .DPO(DPO_0[5]),
        .SPO(SPO_0[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_0_6(
        .DPO(DPO_0[6]),
        .SPO(SPO_0[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_0_7(
        .DPO(DPO_0[7]),
        .SPO(SPO_0[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
RAM16X1D ram32x1d_1_0(
        .DPO(DPO_1[0]),
        .SPO(SPO_1[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_1_1(
        .DPO(DPO_1[1]),
        .SPO(SPO_1[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_1_2(
        .DPO(DPO_1[2]),
        .SPO(SPO_1[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_1_3(
        .DPO(DPO_1[3]),
        .SPO(SPO_1[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_1_4(
        .DPO(DPO_1[4]),
        .SPO(SPO_1[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_1_5(
        .DPO(DPO_1[5]),
        .SPO(SPO_1[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_1_6(
        .DPO(DPO_1[6]),
        .SPO(SPO_1[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_1_7(
        .DPO(DPO_1[7]),
        .SPO(SPO_1[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
endmodule
 
`else
 
module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
// I/O
//
output [7:0]     DPO;
output [7:0]     SPO;
input [4:0]      A;
input [4:0]      DPRA;
input [7:0]      D;
input           WCLK;
input           WE;
 
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
        .DPO(DPO[0]),
        .SPO(SPO[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
        .DPO(DPO[1]),
        .SPO(SPO[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
        .DPO(DPO[2]),
        .SPO(SPO[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
        .DPO(DPO[3]),
        .SPO(SPO[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
        .DPO(DPO[4]),
        .SPO(SPO[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
        .DPO(DPO[5]),
        .SPO(SPO[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
        .DPO(DPO[6]),
        .SPO(SPO[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
        .DPO(DPO[7]),
        .SPO(SPO[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
endmodule
`endif
`endif

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Blame information for rev 55

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Xilinx Virtex RAM 32x8D ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Virtex dual-port memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50			`// Revision 1.7 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
52			`//`
53			`// Revision 1.6 2001/10/14 13:12:10 lampret`
54			`// MP3 version.`
55			`//`
56			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
57			`// no message`
58			`//`
59			`// Revision 1.1 2001/08/09 13:39:33 lampret`
60			`// Major clean-up.`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "or1200_defines.v"
68
69			`ifdef OR1200_XILINX_RAM32X1D
70			`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
71			`module or1200_xcv_ram32x8d`
72			`(`
73			`DPO,`
74			`SPO,`
75			`A,`
76			`D,`
77			`DPRA,`
78			`WCLK,`
79			`WE`
80			`);`
81			`output [7:0] DPO;`
82			`output [7:0] SPO;`
83			`input [4:0] A;`
84			`input [4:0] DPRA;`
85			`input [7:0] D;`
86			`input WCLK;`
87			`input WE;`
88
89			`wire [7:0] DPO_0;`
90			`wire [7:0] SPO_0;`
91
92			`wire [7:0] DPO_1;`
93			`wire [7:0] SPO_1;`
94
95			`wire WE_0 ;`
96			`wire WE_1 ;`
97
98			`assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;`
99			`assign SPO = A[4] ? SPO_1 : SPO_0 ;`
100
101			`assign WE_0 = !A[4] && WE ;`
102			`assign WE_1 = A[4] && WE ;`
103
104			`RAM16X1D ram32x1d_0_0(`
105			`.DPO(DPO_0[0]),`
106			`.SPO(SPO_0[0]),`
107			`.A0(A[0]),`
108			`.A1(A[1]),`
109			`.A2(A[2]),`
110			`.A3(A[3]),`
111			`.D(D[0]),`
112			`.DPRA0(DPRA[0]),`
113			`.DPRA1(DPRA[1]),`
114			`.DPRA2(DPRA[2]),`
115			`.DPRA3(DPRA[3]),`
116			`.WCLK(WCLK),`
117			`.WE(WE_0)`
118			`);`
119
120			`//`
121			`// Instantiation of block 1`
122			`//`
123			`RAM16X1D ram32x1d_0_1(`
124			`.DPO(DPO_0[1]),`
125			`.SPO(SPO_0[1]),`
126			`.A0(A[0]),`
127			`.A1(A[1]),`
128			`.A2(A[2]),`
129			`.A3(A[3]),`
130			`.D(D[1]),`
131			`.DPRA0(DPRA[0]),`
132			`.DPRA1(DPRA[1]),`
133			`.DPRA2(DPRA[2]),`
134			`.DPRA3(DPRA[3]),`
135			`.WCLK(WCLK),`
136			`.WE(WE_0)`
137			`);`
138
139			`//`
140			`// Instantiation of block 2`
141			`//`
142			`RAM16X1D ram32x1d_0_2(`
143			`.DPO(DPO_0[2]),`
144			`.SPO(SPO_0[2]),`
145			`.A0(A[0]),`
146			`.A1(A[1]),`
147			`.A2(A[2]),`
148			`.A3(A[3]),`
149			`.D(D[2]),`
150			`.DPRA0(DPRA[0]),`
151			`.DPRA1(DPRA[1]),`
152			`.DPRA2(DPRA[2]),`
153			`.DPRA3(DPRA[3]),`
154			`.WCLK(WCLK),`
155			`.WE(WE_0)`
156			`);`
157
158			`//`
159			`// Instantiation of block 3`
160			`//`
161			`RAM16X1D ram32x1d_0_3(`
162			`.DPO(DPO_0[3]),`
163			`.SPO(SPO_0[3]),`
164			`.A0(A[0]),`
165			`.A1(A[1]),`
166			`.A2(A[2]),`
167			`.A3(A[3]),`
168			`.D(D[3]),`
169			`.DPRA0(DPRA[0]),`
170			`.DPRA1(DPRA[1]),`
171			`.DPRA2(DPRA[2]),`
172			`.DPRA3(DPRA[3]),`
173			`.WCLK(WCLK),`
174			`.WE(WE_0)`
175			`);`
176
177			`//`
178			`// Instantiation of block 4`
179			`//`
180			`RAM16X1D ram32x1d_0_4(`
181			`.DPO(DPO_0[4]),`
182			`.SPO(SPO_0[4]),`
183			`.A0(A[0]),`
184			`.A1(A[1]),`
185			`.A2(A[2]),`
186			`.A3(A[3]),`
187			`.D(D[4]),`
188			`.DPRA0(DPRA[0]),`
189			`.DPRA1(DPRA[1]),`
190			`.DPRA2(DPRA[2]),`
191			`.DPRA3(DPRA[3]),`
192			`.WCLK(WCLK),`
193			`.WE(WE_0)`
194			`);`
195
196			`//`
197			`// Instantiation of block 5`
198			`//`
199			`RAM16X1D ram32x1d_0_5(`
200			`.DPO(DPO_0[5]),`
201			`.SPO(SPO_0[5]),`
202			`.A0(A[0]),`
203			`.A1(A[1]),`
204			`.A2(A[2]),`
205			`.A3(A[3]),`
206			`.D(D[5]),`
207			`.DPRA0(DPRA[0]),`
208			`.DPRA1(DPRA[1]),`
209			`.DPRA2(DPRA[2]),`
210			`.DPRA3(DPRA[3]),`
211			`.WCLK(WCLK),`
212			`.WE(WE_0)`
213			`);`
214
215			`//`
216			`// Instantiation of block 6`
217			`//`
218			`RAM16X1D ram32x1d_0_6(`
219			`.DPO(DPO_0[6]),`
220			`.SPO(SPO_0[6]),`
221			`.A0(A[0]),`
222			`.A1(A[1]),`
223			`.A2(A[2]),`
224			`.A3(A[3]),`
225			`.D(D[6]),`
226			`.DPRA0(DPRA[0]),`
227			`.DPRA1(DPRA[1]),`
228			`.DPRA2(DPRA[2]),`
229			`.DPRA3(DPRA[3]),`
230			`.WCLK(WCLK),`
231			`.WE(WE_0)`
232			`);`
233
234			`//`
235			`// Instantiation of block 7`
236			`//`
237			`RAM16X1D ram32x1d_0_7(`
238			`.DPO(DPO_0[7]),`
239			`.SPO(SPO_0[7]),`
240			`.A0(A[0]),`
241			`.A1(A[1]),`
242			`.A2(A[2]),`
243			`.A3(A[3]),`
244			`.D(D[7]),`
245			`.DPRA0(DPRA[0]),`
246			`.DPRA1(DPRA[1]),`
247			`.DPRA2(DPRA[2]),`
248			`.DPRA3(DPRA[3]),`
249			`.WCLK(WCLK),`
250			`.WE(WE_0)`
251			`);`
252
253			`RAM16X1D ram32x1d_1_0(`
254			`.DPO(DPO_1[0]),`
255			`.SPO(SPO_1[0]),`
256			`.A0(A[0]),`
257			`.A1(A[1]),`
258			`.A2(A[2]),`
259			`.A3(A[3]),`
260			`.D(D[0]),`
261			`.DPRA0(DPRA[0]),`
262			`.DPRA1(DPRA[1]),`
263			`.DPRA2(DPRA[2]),`
264			`.DPRA3(DPRA[3]),`
265			`.WCLK(WCLK),`
266			`.WE(WE_1)`
267			`);`
268
269			`//`
270			`// Instantiation of block 1`
271			`//`
272			`RAM16X1D ram32x1d_1_1(`
273			`.DPO(DPO_1[1]),`
274			`.SPO(SPO_1[1]),`
275			`.A0(A[0]),`
276			`.A1(A[1]),`
277			`.A2(A[2]),`
278			`.A3(A[3]),`
279			`.D(D[1]),`
280			`.DPRA0(DPRA[0]),`
281			`.DPRA1(DPRA[1]),`
282			`.DPRA2(DPRA[2]),`
283			`.DPRA3(DPRA[3]),`
284			`.WCLK(WCLK),`
285			`.WE(WE_1)`
286			`);`
287
288			`//`
289			`// Instantiation of block 2`
290			`//`
291			`RAM16X1D ram32x1d_1_2(`
292			`.DPO(DPO_1[2]),`
293			`.SPO(SPO_1[2]),`
294			`.A0(A[0]),`
295			`.A1(A[1]),`
296			`.A2(A[2]),`
297			`.A3(A[3]),`
298			`.D(D[2]),`
299			`.DPRA0(DPRA[0]),`
300			`.DPRA1(DPRA[1]),`
301			`.DPRA2(DPRA[2]),`
302			`.DPRA3(DPRA[3]),`
303			`.WCLK(WCLK),`
304			`.WE(WE_1)`
305			`);`
306
307			`//`
308			`// Instantiation of block 3`
309			`//`
310			`RAM16X1D ram32x1d_1_3(`
311			`.DPO(DPO_1[3]),`
312			`.SPO(SPO_1[3]),`
313			`.A0(A[0]),`
314			`.A1(A[1]),`
315			`.A2(A[2]),`
316			`.A3(A[3]),`
317			`.D(D[3]),`
318			`.DPRA0(DPRA[0]),`
319			`.DPRA1(DPRA[1]),`
320			`.DPRA2(DPRA[2]),`
321			`.DPRA3(DPRA[3]),`
322			`.WCLK(WCLK),`
323			`.WE(WE_1)`
324			`);`
325
326			`//`
327			`// Instantiation of block 4`
328			`//`
329			`RAM16X1D ram32x1d_1_4(`
330			`.DPO(DPO_1[4]),`
331			`.SPO(SPO_1[4]),`
332			`.A0(A[0]),`
333			`.A1(A[1]),`
334			`.A2(A[2]),`
335			`.A3(A[3]),`
336			`.D(D[4]),`
337			`.DPRA0(DPRA[0]),`
338			`.DPRA1(DPRA[1]),`
339			`.DPRA2(DPRA[2]),`
340			`.DPRA3(DPRA[3]),`
341			`.WCLK(WCLK),`
342			`.WE(WE_1)`
343			`);`
344
345			`//`
346			`// Instantiation of block 5`
347			`//`
348			`RAM16X1D ram32x1d_1_5(`
349			`.DPO(DPO_1[5]),`
350			`.SPO(SPO_1[5]),`
351			`.A0(A[0]),`
352			`.A1(A[1]),`
353			`.A2(A[2]),`
354			`.A3(A[3]),`
355			`.D(D[5]),`
356			`.DPRA0(DPRA[0]),`
357			`.DPRA1(DPRA[1]),`
358			`.DPRA2(DPRA[2]),`
359			`.DPRA3(DPRA[3]),`
360			`.WCLK(WCLK),`
361			`.WE(WE_1)`
362			`);`
363
364			`//`
365			`// Instantiation of block 6`
366			`//`
367			`RAM16X1D ram32x1d_1_6(`
368			`.DPO(DPO_1[6]),`
369			`.SPO(SPO_1[6]),`
370			`.A0(A[0]),`
371			`.A1(A[1]),`
372			`.A2(A[2]),`
373			`.A3(A[3]),`
374			`.D(D[6]),`
375			`.DPRA0(DPRA[0]),`
376			`.DPRA1(DPRA[1]),`
377			`.DPRA2(DPRA[2]),`
378			`.DPRA3(DPRA[3]),`
379			`.WCLK(WCLK),`
380			`.WE(WE_1)`
381			`);`
382
383			`//`
384			`// Instantiation of block 7`
385			`//`
386			`RAM16X1D ram32x1d_1_7(`
387			`.DPO(DPO_1[7]),`
388			`.SPO(SPO_1[7]),`
389			`.A0(A[0]),`
390			`.A1(A[1]),`
391			`.A2(A[2]),`
392			`.A3(A[3]),`
393			`.D(D[7]),`
394			`.DPRA0(DPRA[0]),`
395			`.DPRA1(DPRA[1]),`
396			`.DPRA2(DPRA[2]),`
397			`.DPRA3(DPRA[3]),`
398			`.WCLK(WCLK),`
399			`.WE(WE_1)`
400			`);`
401			`endmodule`
402
403			`else
404
405			`module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`
406
407			`//`
408			`// I/O`
409			`//`
410			`output [7:0] DPO;`
411			`output [7:0] SPO;`
412			`input [4:0] A;`
413			`input [4:0] DPRA;`
414			`input [7:0] D;`
415			`input WCLK;`
416			`input WE;`
417
418			`//`
419			`// Instantiation of block 0`
420			`//`
421			`RAM32X1D ram32x1d_0(`
422			`.DPO(DPO[0]),`
423			`.SPO(SPO[0]),`
424			`.A0(A[0]),`
425			`.A1(A[1]),`
426			`.A2(A[2]),`
427			`.A3(A[3]),`
428			`.A4(A[4]),`
429			`.D(D[0]),`
430			`.DPRA0(DPRA[0]),`
431			`.DPRA1(DPRA[1]),`
432			`.DPRA2(DPRA[2]),`
433			`.DPRA3(DPRA[3]),`
434			`.DPRA4(DPRA[4]),`
435			`.WCLK(WCLK),`
436			`.WE(WE)`
437			`);`
438
439			`//`
440			`// Instantiation of block 1`
441			`//`
442			`RAM32X1D ram32x1d_1(`
443			`.DPO(DPO[1]),`
444			`.SPO(SPO[1]),`
445			`.A0(A[0]),`
446			`.A1(A[1]),`
447			`.A2(A[2]),`
448			`.A3(A[3]),`
449			`.A4(A[4]),`
450			`.D(D[1]),`
451			`.DPRA0(DPRA[0]),`
452			`.DPRA1(DPRA[1]),`
453			`.DPRA2(DPRA[2]),`
454			`.DPRA3(DPRA[3]),`
455			`.DPRA4(DPRA[4]),`
456			`.WCLK(WCLK),`
457			`.WE(WE)`
458			`);`
459
460			`//`
461			`// Instantiation of block 2`
462			`//`
463			`RAM32X1D ram32x1d_2(`
464			`.DPO(DPO[2]),`
465			`.SPO(SPO[2]),`
466			`.A0(A[0]),`
467			`.A1(A[1]),`
468			`.A2(A[2]),`
469			`.A3(A[3]),`
470			`.A4(A[4]),`
471			`.D(D[2]),`
472			`.DPRA0(DPRA[0]),`
473			`.DPRA1(DPRA[1]),`
474			`.DPRA2(DPRA[2]),`
475			`.DPRA3(DPRA[3]),`
476			`.DPRA4(DPRA[4]),`
477			`.WCLK(WCLK),`
478			`.WE(WE)`
479			`);`
480
481			`//`
482			`// Instantiation of block 3`
483			`//`
484			`RAM32X1D ram32x1d_3(`
485			`.DPO(DPO[3]),`
486			`.SPO(SPO[3]),`
487			`.A0(A[0]),`
488			`.A1(A[1]),`
489			`.A2(A[2]),`
490			`.A3(A[3]),`
491			`.A4(A[4]),`
492			`.D(D[3]),`
493			`.DPRA0(DPRA[0]),`
494			`.DPRA1(DPRA[1]),`
495			`.DPRA2(DPRA[2]),`
496			`.DPRA3(DPRA[3]),`
497			`.DPRA4(DPRA[4]),`
498			`.WCLK(WCLK),`
499			`.WE(WE)`
500			`);`
501
502			`//`
503			`// Instantiation of block 4`
504			`//`
505			`RAM32X1D ram32x1d_4(`
506			`.DPO(DPO[4]),`
507			`.SPO(SPO[4]),`
508			`.A0(A[0]),`
509			`.A1(A[1]),`
510			`.A2(A[2]),`
511			`.A3(A[3]),`
512			`.A4(A[4]),`
513			`.D(D[4]),`
514			`.DPRA0(DPRA[0]),`
515			`.DPRA1(DPRA[1]),`
516			`.DPRA2(DPRA[2]),`
517			`.DPRA3(DPRA[3]),`
518			`.DPRA4(DPRA[4]),`
519			`.WCLK(WCLK),`
520			`.WE(WE)`
521			`);`
522
523			`//`
524			`// Instantiation of block 5`
525			`//`
526			`RAM32X1D ram32x1d_5(`
527			`.DPO(DPO[5]),`
528			`.SPO(SPO[5]),`
529			`.A0(A[0]),`
530			`.A1(A[1]),`
531			`.A2(A[2]),`
532			`.A3(A[3]),`
533			`.A4(A[4]),`
534			`.D(D[5]),`
535			`.DPRA0(DPRA[0]),`
536			`.DPRA1(DPRA[1]),`
537			`.DPRA2(DPRA[2]),`
538			`.DPRA3(DPRA[3]),`
539			`.DPRA4(DPRA[4]),`
540			`.WCLK(WCLK),`
541			`.WE(WE)`
542			`);`
543
544			`//`
545			`// Instantiation of block 6`
546			`//`
547			`RAM32X1D ram32x1d_6(`
548			`.DPO(DPO[6]),`
549			`.SPO(SPO[6]),`
550			`.A0(A[0]),`
551			`.A1(A[1]),`
552			`.A2(A[2]),`
553			`.A3(A[3]),`
554			`.A4(A[4]),`
555			`.D(D[6]),`
556			`.DPRA0(DPRA[0]),`
557			`.DPRA1(DPRA[1]),`
558			`.DPRA2(DPRA[2]),`
559			`.DPRA3(DPRA[3]),`
560			`.DPRA4(DPRA[4]),`
561			`.WCLK(WCLK),`
562			`.WE(WE)`
563			`);`
564
565			`//`
566			`// Instantiation of block 7`
567			`//`
568			`RAM32X1D ram32x1d_7(`
569			`.DPO(DPO[7]),`
570			`.SPO(SPO[7]),`
571			`.A0(A[0]),`
572			`.A1(A[1]),`
573			`.A2(A[2]),`
574			`.A3(A[3]),`
575			`.A4(A[4]),`
576			`.D(D[7]),`
577			`.DPRA0(DPRA[0]),`
578			`.DPRA1(DPRA[1]),`
579			`.DPRA2(DPRA[2]),`
580			`.DPRA3(DPRA[3]),`
581			`.DPRA4(DPRA[4]),`
582			`.WCLK(WCLK),`
583			`.WE(WE)`
584			`);`
585
586			`endmodule`
587			`endif
588			`endif