URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [flash/] [flash.gen] - Blame information for rev 2

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Version:8.5.0.34
ACTGENU_CALL:1
BATCH:T
FAM:ProASIC3
OUTFORMAT:Verilog
LPMTYPE:LPM_FROM
LPM_HINT:NONE
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
DESDIR:C:/work/IP/trunk/or1k_startup/syn/flash/smartgen\flash
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IS8X8M2
SMARTGEN_PACKAGE:pq208
AGENIII_IS_SUBPROJECT_LIBERO:T
MEMFILE:flash.mem
UFCFILE:flash.ufc

Line No.	Rev	Author	Line
1	2	marcus.erl	`Version:8.5.0.34`
2			`ACTGENU_CALL:1`
3			`BATCH:T`
4			`FAM:ProASIC3`
5			`OUTFORMAT:Verilog`
6			`LPMTYPE:LPM_FROM`
7			`LPM_HINT:NONE`
8			`INSERT_PAD:NO`
9			`INSERT_IOREG:NO`
10			`GEN_BHV_VHDL_VAL:F`
11			`GEN_BHV_VERILOG_VAL:F`
12			`MGNTIMER:F`
13			`MGNCMPL:T`
14			`DESDIR:C:/work/IP/trunk/or1k_startup/syn/flash/smartgen\flash`
15			`GEN_BEHV_MODULE:T`
16			`SMARTGEN_DIE:IS8X8M2`
17			`SMARTGEN_PACKAGE:pq208`
18			`AGENIII_IS_SUBPROJECT_LIBERO:T`
19			`MEMFILE:flash.mem`
20			`UFCFILE:flash.ufc`

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[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [flash/] [flash.gen] - Blame information for rev 2