OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [flash/] [flash.log] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marcus.erl
 ** Message System Log
2
 ** Database:
3
 ** Date:   Mon Mar 16 11:22:43 2009
4
 
5
 
6
****************
7
Macro Parameters
8
****************
9
 
10
Name                            : flash
11
Family                          : ProASIC3
12
Output Format                   : VERILOG
13
Type                            : UFROM
14
MEMFILE                         : flash.mem
15
ACT_PROGFILE                    : flash.ufc
16
 
17
**************
18
Compile Report
19
**************
20
 
21
Warning:  For versions of the A3P1000 device that do not have a 'C' after the
22
          device packing datecode there is a six pages limitation for the
23
          UFROM macro if the AES Key is used for security.
24
 
25
Netlist Resource Report
26
=======================
27
 
28
    CORE                     Used:      8  Total:  24576   (0.03%)
29
    IO (W/ clocks)           Used:      0  Total:    154   (0.00%)
30
    Differential IO          Used:      0  Total:     35   (0.00%)
31
    GLOBAL (Chip+Quadrant)   Used:      0  Total:     18   (0.00%)
32
    PLL                      Used:      0  Total:      1   (0.00%)
33
    RAM/FIFO                 Used:      0  Total:     32   (0.00%)
34
    Low Static ICC           Used:      0  Total:      1   (0.00%)
35
    FlashROM                 Used:      1  Total:      1   (100.00%)
36
    User JTAG                Used:      0  Total:      1   (0.00%)
37
 
38
Wrote Verilog netlist to
39
C:/work/IP/trunk/or1k_startup/syn/flash/smartgen\flash\flash.v.
40
 
41
 ** Log Ended:   Mon Mar 16 11:22:45 2009
42
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.