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[/] [openrisc/] [trunk/] [or1k_startup/] [rtl/] [verilog/] [OR1K_startup.v] - Blame information for rev 2

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1 2 marcus.erl
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1K_startup                                                ////
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////                                                              ////
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////  This file is part of the OR1K startup IP core project       ////
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////  http://www.opencores.org/                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback (unneback@opencores.org)             ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module OR1K_startup
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  (
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    input [6:2]       wb_adr_i,
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    input             wb_stb_i,
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    input             wb_cyc_i,
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    output reg [31:0] wb_dat_o,
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    output reg        wb_ack_o,
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    input             wb_clk,
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    input             wb_rst
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   );
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   always @ (posedge wb_clk or posedge wb_rst)
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     if (wb_rst)
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       wb_dat_o <= 32'h15000000;
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     else
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       case (wb_adr_i)
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          1 : wb_dat_o <= 32'hA8200000;
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          2 : wb_dat_o <= 32'h1880B000;
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          3 : wb_dat_o <= 32'hA8A00520;
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          4 : wb_dat_o <= 32'hA8600001;
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          5 : wb_dat_o <= 32'h04000014;
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          6 : wb_dat_o <= 32'hD4041818;
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          7 : wb_dat_o <= 32'h04000012;
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          8 : wb_dat_o <= 32'hD4040000;
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          9 : wb_dat_o <= 32'hE0431804;
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         10 : wb_dat_o <= 32'h0400000F;
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         11 : wb_dat_o <= 32'h9C210008;
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         12 : wb_dat_o <= 32'h0400000D;
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         13 : wb_dat_o <= 32'hE1031804;
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         14 : wb_dat_o <= 32'hE4080000;
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         15 : wb_dat_o <= 32'h0FFFFFFB;
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         16 : wb_dat_o <= 32'hD4081800;
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         17 : wb_dat_o <= 32'h04000008;
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         18 : wb_dat_o <= 32'h9C210004;
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         19 : wb_dat_o <= 32'hD4011800;
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         20 : wb_dat_o <= 32'hE4011000;
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         21 : wb_dat_o <= 32'h0FFFFFFC;
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         22 : wb_dat_o <= 32'hA8C00100;
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         23 : wb_dat_o <= 32'h44003000;
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         24 : wb_dat_o <= 32'hD4040018;
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         25 : wb_dat_o <= 32'hD4042810;
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         26 : wb_dat_o <= 32'h84640010;
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         27 : wb_dat_o <= 32'hBC030520;
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         28 : wb_dat_o <= 32'h13FFFFFE;
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         29 : wb_dat_o <= 32'h15000000;
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         30 : wb_dat_o <= 32'h44004800;
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         31 : wb_dat_o <= 32'h84640000;
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       endcase
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   always @ (posedge wb_clk or posedge wb_rst)
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     if (wb_rst)
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       wb_ack_o <= 1'b0;
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     else
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       wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
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endmodule

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