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[/] [openrisc/] [trunk/] [or1k_startup/] [rtl/] [verilog/] [OR1K_startup_ACTEL.v] - Blame information for rev 410

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Line No. Rev Author Line
1 2 marcus.erl
module OR1K_startup
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  (
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    input [6:2]       wb_adr_i,
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    input             wb_stb_i,
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    input             wb_cyc_i,
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    output reg [31:0] wb_dat_o,
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    output reg        wb_ack_o,
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    input             wb_clk,
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    input             wb_rst
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   );
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   reg [3:0]           counter;
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   wire [7:0]          do;
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   parameter [31:0] NOP = 32'h15000000;
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   always @ (posedge wb_clk or posedge wb_rst)
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     if (wb_rst)
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       counter <= 4'd0;
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     else
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       if (!wb_cyc_i)
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         counter <= 4'd0;
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       else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
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         counter <= counter + 4'd1;
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   always @ (posedge wb_clk or posedge wb_rst)
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     if (wb_rst)
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       wb_ack_o <= 1'b0;
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     else
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       wb_ack_o <= (counter == 4'd15);
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   always @ (posedge wb_clk or posedge wb_rst)
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     if (wb_rst)
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       wb_dat_o <= NOP;
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     else
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       case (counter)
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         4'd15: wb_dat_o[31:24] <= do;
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         4'd11: wb_dat_o[23:16] <= do;
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         4'd7 : wb_dat_o[15: 8] <= do;
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         4'd3 : wb_dat_o[ 7: 0] <= do;
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       endcase
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   flash flash0
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     (
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      .CLK  (counter[1] ^ counter[0]),
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      .ADDR ({wb_adr_i,counter[3:2]}),
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      .DOUT (do)
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      );
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endmodule // OR1K_startup

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