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marcus.erl |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1K_startup ////
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//// ////
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//// This file is part of the OR1K startup IP core project ////
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//// http://www.opencores.org/ ////
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//// ////
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//// Author(s): ////
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//// - Michael Unneback (unneback@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module OR1K_startup
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(
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input [6:2] wb_adr_i,
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input wb_stb_i,
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input wb_cyc_i,
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output reg [31:0] wb_dat_o,
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output reg wb_ack_o,
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input wb_clk,
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input wb_rst
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);
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reg [3:0] counter;
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wire [7:0] do;
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parameter [31:0] NOP = 32'h15000000;
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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counter <= 4'd0;
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else
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if (!wb_cyc_i)
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counter <= 4'd0;
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else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
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counter <= counter + 4'd1;
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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wb_ack_o <= 1'b0;
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else
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wb_ack_o <= (counter == 4'd15);
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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wb_dat_o <= NOP;
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else
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case (counter)
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4'd15: wb_dat_o[31:24] <= do;
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4'd11: wb_dat_o[23:16] <= do;
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4'd7 : wb_dat_o[15: 8] <= do;
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4'd3 : wb_dat_o[ 7: 0] <= do;
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endcase
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flash flash0
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(
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.CLK (counter[1] ^ counter[0]),
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.ADDR ({wb_adr_i,counter[3:2]}),
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.DOUT (do)
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);
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endmodule
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