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[/] [openrisc/] [trunk/] [or1k_startup/] [rtl/] [verilog/] [OR1K_startup_module_inst.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 marcus.erl
OR1K_startup OR1K_startup0
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  (
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    .wb_adr_i(wbs_rom_adr_i[6:2]),
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    .wb_stb_i(wbs_rom_stb_i),
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    .wb_cyc_i(wbs_rom_cyc_i),
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    .wb_dat_o(wbs_rom_dat_o),
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    .wb_ack_o(wbs_rom_ack_o),
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    .wb_clk(wb_clk),
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    .wb_rst(wb_rst)
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   );
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wire spi_flash_mosi, spi_flash_miso, spi_flash_sclk;
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wire [1:0] spi_flash_ss;
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spi_flash_top #
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  (
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   .divider(`SPI_FLASH_DIVIDER),
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   .divider_len(`SPI_FLASH_DIVIDER_LEN)
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   )
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spi_flash_top0
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  (
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   // Wishbone signals
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   .wb_clk_i(wb_clk),
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   .wb_rst_i(wb_rst),
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   .wb_adr_i(wbs_spi_flash_adr_i[4:2]),
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   .wb_dat_i(wbs_spi_flash_dat_i),
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   .wb_dat_o(wbs_spi_flash_dat_o),
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   .wb_sel_i(wbs_spi_flash_sel_i),
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   .wb_we_i(wbs_spi_flash_we_i),
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   .wb_stb_i(wbs_spi_flash_stb_i),
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   .wb_cyc_i(wbs_spi_flash_cyc_i),
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   .wb_ack_o(wbs_spi_flash_ack_o),
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   // SPI signals
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   .mosi_pad_o(spi_flash_mosi),
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   .miso_pad_i(spi_flash_miso),
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   .sclk_pad_o(spi_flash_sclk),
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   .ss_pad_o(spi_flash_ss)
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   );
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// external SPI FLASH
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assign spi_flash_mosi_pad_o = !spi_flash_ss[0] ? spi_flash_mosi : 1'b1;
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assign spi_flash_sclk_pad_o = !spi_flash_ss[0] ? spi_flash_sclk : 1'b1;
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assign spi_flash_ss_pad_o   =  spi_flash_ss[0];
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assign spi_flash_w_n_pad_o    = 1'b1;
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assign spi_flash_hold_n_pad_o = 1'b1;
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// external SD FLASH in SPI mode
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assign spi_sd_mosi_pad_o = !spi_flash_ss[1] ? spi_flash_mosi : 1'b1;
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assign spi_sd_sclk_pad_o = !spi_flash_ss[1] ? spi_flash_sclk : 1'b1;
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assign spi_sd_ss_pad_o   =  spi_flash_ss[1];
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// input mux
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assign spi_flash_miso = !spi_flash_ss[0] ? spi_flash_miso_pad_i :
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                        !spi_flash_ss[1] ? spi_sd_miso_pad_i :
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                        1'b0;

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