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[/] [openrisc/] [trunk/] [or1k_startup/] [rtl/] [verilog/] [OR1K_startup_rom.v] - Blame information for rev 179

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Line No. Rev Author Line
1 2 marcus.erl
module OR1K_startup_rom
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  (
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    input  [6:0] addr,
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    output [31:0] dout,
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    input       clk
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   );
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   wire [31:0]   rom [0:31];
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   assign rom[ 0] = 32'h18000000;
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   assign rom[ 1] = 32'hA8200000;
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   assign rom[ 2] = 32'h1880B000;
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   assign rom[ 3] = 32'hA8A00520;
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   assign rom[ 4] = 32'hA8600001;
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   assign rom[ 5] = 32'h04000014;
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   assign rom[ 6] = 32'hD4041818;
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   assign rom[ 7] = 32'h04000012;
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   assign rom[ 8] = 32'hD4040000;
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   assign rom[ 9] = 32'hE0431804;
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   assign rom[10] = 32'h0400000F;
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   assign rom[11] = 32'h9C210008;
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   assign rom[12] = 32'h0400000D;
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   assign rom[13] = 32'hE1031804;
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   assign rom[14] = 32'hE4080000;
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   assign rom[15] = 32'h0FFFFFFB;
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   assign rom[16] = 32'hD4081800;
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   assign rom[17] = 32'h04000008;
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   assign rom[18] = 32'h9C210004;
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   assign rom[19] = 32'hD4011800;
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   assign rom[20] = 32'hE4011000;
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   assign rom[21] = 32'h0FFFFFFC;
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   assign rom[22] = 32'hA8C00100;
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   assign rom[23] = 32'h44003000;
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   assign rom[24] = 32'hD4040018;
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   assign rom[25] = 32'hD4042810;
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   assign rom[26] = 32'h84640010;
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   assign rom[27] = 32'hBC030520;
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   assign rom[28] = 32'h13FFFFFE;
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   assign rom[29] = 32'h15000000;
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   assign rom[30] = 32'h44004800;
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   assign rom[31] = 32'h84640000;
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   reg [6:0]     addr_reg;
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   always @ (posedge clk)
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     addr_reg <= addr;
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   /*
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   always @ (*)
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     case (addr_reg[1:0])
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       2'b00 : dout <= rom[addr_reg[6:2]][31:24];
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       2'b01 : dout <= rom[addr_reg[6:2]][23:16];
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       2'b10 : dout <= rom[addr_reg[6:2]][15: 8];
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       2'b11 : dout <= rom[addr_reg[6:2]][ 7: 0];
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     endcase
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    */
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   assign dout = rom[addr_reg];
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endmodule // OR1K_startup_rom

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