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[/] [openrisc/] [trunk/] [or1k_startup/] [rtl/] [verilog/] [spi_defines.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  spi_define.v                                                ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
//
// Number of bits used for devider register. If used in system with
// low frequency of system clock this can be reduced.
// Use SPI_DIVIDER_LEN for fine tuning theexact number.
//
`define SPI_DIVIDER_LEN_8
//`define SPI_DIVIDER_LEN_16
//`define SPI_DIVIDER_LEN_24
//`define SPI_DIVIDER_LEN_32
 
`ifdef SPI_DIVIDER_LEN_8
  `define SPI_DIVIDER_LEN       4    // Can be set from 1 to 8
`endif
`ifdef SPI_DIVIDER_LEN_16
  `define SPI_DIVIDER_LEN       16   // Can be set from 9 to 16
`endif
`ifdef SPI_DIVIDER_LEN_24
  `define SPI_DIVIDER_LEN       24   // Can be set from 17 to 24
`endif
`ifdef SPI_DIVIDER_LEN_32
  `define SPI_DIVIDER_LEN       32   // Can be set from 25 to 32 
`endif
 
//
// Maximum nuber of bits that can be send/received at once. 
// Use SPI_MAX_CHAR for fine tuning the exact number, when using
// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
//
//`define SPI_MAX_CHAR_128
//`define SPI_MAX_CHAR_64
`define SPI_MAX_CHAR_32
//`define SPI_MAX_CHAR_24
//`define SPI_MAX_CHAR_16
//`define SPI_MAX_CHAR_8
 
`ifdef SPI_MAX_CHAR_128
  `define SPI_MAX_CHAR          128  // Can only be set to 128 
  `define SPI_CHAR_LEN_BITS     7
`endif
`ifdef SPI_MAX_CHAR_64
  `define SPI_MAX_CHAR          64   // Can only be set to 64 
  `define SPI_CHAR_LEN_BITS     6
`endif
`ifdef SPI_MAX_CHAR_32
  `define SPI_MAX_CHAR          32   // Can be set from 25 to 32 
  `define SPI_CHAR_LEN_BITS     6
  `define SPI_CHAR_RST          32'h03000000
`endif
`ifdef SPI_MAX_CHAR_24
  `define SPI_MAX_CHAR          24   // Can be set from 17 to 24 
  `define SPI_CHAR_LEN_BITS     5
`endif
`ifdef SPI_MAX_CHAR_16
  `define SPI_MAX_CHAR          16   // Can be set from 9 to 16 
  `define SPI_CHAR_LEN_BITS     4
`endif
`ifdef SPI_MAX_CHAR_8
  `define SPI_MAX_CHAR          8    // Can be set from 1 to 8 
  `define SPI_CHAR_LEN_BITS     3
`endif
 
//
// Number of device select signals. Use SPI_SS_NB for fine tuning the 
// exact number.
//
`define SPI_SS_NB             2    // Can be set from 1 to 2
 
//
// Bits of WISHBONE address used for partial decoding of SPI registers.
//
`define SPI_OFS_BITS              4:2
 
//
// Register offset
//
`define SPI_RX_0                0
`define SPI_RX_1                1
`define SPI_RX_2                2
`define SPI_RX_3                3
`define SPI_TX_0                0
`define SPI_TX_1                1
`define SPI_TX_2                2
`define SPI_TX_3                3
`define SPI_CTRL                4
`define SPI_DEVIDE              5
`define SPI_SS                  6
 
//
// Number of bits in ctrl register
//
`define SPI_CTRL_BIT_NB         14
`define SPI_CTRL_BIT_RST        14'h420
//
// Control register bits
//
//`define SPI_CTRL_LSB            
`define SPI_CTRL_TX_NEGEDGE
//`define SPI_CTRL_RX_NEGEDGE     
 

Line No.	Rev	Author	Line
1	2	marcus.erl	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// spi_define.v ////`
4			`//// ////`
5			`//// This file is part of the SPI IP core project ////`
6			`//// http://www.opencores.org/projects/spi/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Simon Srot (simons@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40
41			`//`
42			`// Number of bits used for devider register. If used in system with`
43			`// low frequency of system clock this can be reduced.`
44			`// Use SPI_DIVIDER_LEN for fine tuning theexact number.`
45			`//`
46			`define SPI_DIVIDER_LEN_8
47			//`define SPI_DIVIDER_LEN_16
48			//`define SPI_DIVIDER_LEN_24
49			//`define SPI_DIVIDER_LEN_32
50
51			`ifdef SPI_DIVIDER_LEN_8
52			`define SPI_DIVIDER_LEN 4 // Can be set from 1 to 8
53			`endif
54			`ifdef SPI_DIVIDER_LEN_16
55			`define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16
56			`endif
57			`ifdef SPI_DIVIDER_LEN_24
58			`define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24
59			`endif
60			`ifdef SPI_DIVIDER_LEN_32
61			`define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32
62			`endif
63
64			`//`
65			`// Maximum nuber of bits that can be send/received at once.`
66			`// Use SPI_MAX_CHAR for fine tuning the exact number, when using`
67			`// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.`
68			`//`
69			//`define SPI_MAX_CHAR_128
70			//`define SPI_MAX_CHAR_64
71			`define SPI_MAX_CHAR_32
72			//`define SPI_MAX_CHAR_24
73			//`define SPI_MAX_CHAR_16
74			//`define SPI_MAX_CHAR_8
75
76			`ifdef SPI_MAX_CHAR_128
77			`define SPI_MAX_CHAR 128 // Can only be set to 128
78			`define SPI_CHAR_LEN_BITS 7
79			`endif
80			`ifdef SPI_MAX_CHAR_64
81			`define SPI_MAX_CHAR 64 // Can only be set to 64
82			`define SPI_CHAR_LEN_BITS 6
83			`endif
84			`ifdef SPI_MAX_CHAR_32
85			`define SPI_MAX_CHAR 32 // Can be set from 25 to 32
86			`define SPI_CHAR_LEN_BITS 6
87			`define SPI_CHAR_RST 32'h03000000
88			`endif
89			`ifdef SPI_MAX_CHAR_24
90			`define SPI_MAX_CHAR 24 // Can be set from 17 to 24
91			`define SPI_CHAR_LEN_BITS 5
92			`endif
93			`ifdef SPI_MAX_CHAR_16
94			`define SPI_MAX_CHAR 16 // Can be set from 9 to 16
95			`define SPI_CHAR_LEN_BITS 4
96			`endif
97			`ifdef SPI_MAX_CHAR_8
98			`define SPI_MAX_CHAR 8 // Can be set from 1 to 8
99			`define SPI_CHAR_LEN_BITS 3
100			`endif
101
102			`//`
103			`// Number of device select signals. Use SPI_SS_NB for fine tuning the`
104			`// exact number.`
105			`//`
106			`define SPI_SS_NB 2 // Can be set from 1 to 2
107
108			`//`
109			`// Bits of WISHBONE address used for partial decoding of SPI registers.`
110			`//`
111			`define SPI_OFS_BITS 4:2
112
113			`//`
114			`// Register offset`
115			`//`
116			`define SPI_RX_0 0
117			`define SPI_RX_1 1
118			`define SPI_RX_2 2
119			`define SPI_RX_3 3
120			`define SPI_TX_0 0
121			`define SPI_TX_1 1
122			`define SPI_TX_2 2
123			`define SPI_TX_3 3
124			`define SPI_CTRL 4
125			`define SPI_DEVIDE 5
126			`define SPI_SS 6
127
128			`//`
129			`// Number of bits in ctrl register`
130			`//`
131			`define SPI_CTRL_BIT_NB 14
132			`define SPI_CTRL_BIT_RST 14'h420
133			`//`
134			`// Control register bits`
135			`//`
136			//`define SPI_CTRL_LSB
137			`define SPI_CTRL_TX_NEGEDGE
138			//`define SPI_CTRL_RX_NEGEDGE
139

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[/] [openrisc/] [trunk/] [or1k_startup/] [rtl/] [verilog/] [spi_defines.v] - Blame information for rev 2