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[/] [openrisc/] [trunk/] [or1k_startup/] [rtl/] [verilog/] [spi_flash.v] - Blame information for rev 283

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1 2 marcus.erl
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  spi_shift.v                                                 ////
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////                                                              ////
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////  This file is part of the SPI IP core project                ////
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////  http://www.opencores.org/projects/spi/                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Srot (simons@opencores.org)                     ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2002 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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 `timescale 1ns / 10ps
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module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge);
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   parameter divider_len = 2;
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   parameter divider = 1;
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   parameter Tp = 1;
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   input                            clk_in;
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   input                            rst;
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   input                            enable;
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   input                            go;
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   input                            last_clk;
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   output                           clk_out;
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   output                           pos_edge;
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   output                           neg_edge;
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   reg                              clk_out;
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   reg                              pos_edge;
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   reg                              neg_edge;
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   reg [divider_len-1:0]             cnt;
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   wire                             cnt_zero;
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   wire                             cnt_one;
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   assign cnt_zero = cnt == {divider_len{1'b0}};
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   assign cnt_one  = cnt == {{divider_len-1{1'b0}}, 1'b1};
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   always @(posedge clk_in or posedge rst)
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     begin
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        if(rst)
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          cnt <= #Tp {divider_len{1'b1}};
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        else
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          begin
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             if(!enable || cnt_zero)
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               cnt <= #Tp divider;
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             else
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               cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1};
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          end
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     end
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   always @(posedge clk_in or posedge rst)
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     begin
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        if(rst)
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          clk_out <= #Tp 1'b0;
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        else
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          clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
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     end
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   always @(posedge clk_in or posedge rst)
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     begin
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        if(rst)
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          begin
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             pos_edge  <= #Tp 1'b0;
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             neg_edge  <= #Tp 1'b0;
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          end
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        else
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          begin
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             pos_edge  <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
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             neg_edge  <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
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          end
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     end
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endmodule
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 `timescale 1ns / 10ps
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module spi_flash_shift
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  (
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   clk, rst, latch, byte_sel, len, go,
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   pos_edge, neg_edge,
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   lsb, rx_negedge, tx_negedge,
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   tip, last,
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   p_in, p_out, s_clk, s_in, s_out);
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  parameter Tp = 1;
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   input                          clk;
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   input                          rst;
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   input                          latch;
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   input [3:0]                     byte_sel;
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   input [6-1:0] len;
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   input                          lsb;
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   input                          tx_negedge;
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   input                          rx_negedge;
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   input                          go;
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   input                          pos_edge;
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   input                          neg_edge;
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   output                         tip;
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   output                         last;
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   input [31:0]            p_in;
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   output [32-1:0]         p_out;
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   input                          s_clk;
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   input                          s_in;
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   output                         s_out;
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   reg                            s_out;
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   reg                            tip;
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   reg [6:0]       cnt;
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   reg [32-1:0]    data;
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   wire [6:0]      tx_bit_pos;
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   wire [6:0]      rx_bit_pos;
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   wire                           rx_clk;
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   wire                           tx_clk;
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   assign p_out = data;
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   assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{6{1'b0}},1'b1};
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   assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{6{1'b0}},1'b1} : cnt) : (rx_negedge ? cnt : cnt - {{6{1'b0}},1'b1});
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  assign last = !(|cnt);
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  assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
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  assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
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  always @(posedge clk or posedge rst)
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  begin
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    if(rst)
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      cnt <= #Tp {6+1{1'b0}};
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    else
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      begin
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        if(tip)
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          cnt <= #Tp pos_edge ? (cnt - {{6{1'b0}}, 1'b1}) : cnt;
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        else
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          cnt <= #Tp !(|len) ? {1'b1, {6{1'b0}}} : {1'b0, len};
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      end
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  end
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  always @(posedge clk or posedge rst)
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  begin
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    if(rst)
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      tip <= #Tp 1'b0;
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  else if(go && ~tip)
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    tip <= #Tp 1'b1;
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  else if(tip && last && pos_edge)
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    tip <= #Tp 1'b0;
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  end
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  always @(posedge clk or posedge rst)
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  begin
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    if (rst)
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      s_out   <= #Tp 1'b0;
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    else
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      s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[6-1:0]] : s_out;
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  end
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   always @(posedge clk or posedge rst)
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     if (rst)
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       data   <= #Tp 32'h03000000;
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     else
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       if (latch & !tip)
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         begin
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            if (byte_sel[0])
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              data[7:0] <= #Tp p_in[7:0];
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            if (byte_sel[1])
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              data[15:8] <= #Tp p_in[15:8];
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            if (byte_sel[2])
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              data[23:16] <= #Tp p_in[23:16];
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            if (byte_sel[3])
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              data[31:24] <= #Tp p_in[31:24];
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         end
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       else
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         data[rx_bit_pos[6-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[6-1:0]];
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endmodule
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 `timescale 1ns / 10ps
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module spi_flash_top
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  (
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   wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
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   wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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   ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
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   );
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   parameter divider_len = 2;
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   parameter divider = 0;
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   parameter Tp = 1;
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   input                            wb_clk_i;
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   input                            wb_rst_i;
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   input [4:2]                      wb_adr_i;
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   input [31:0]              wb_dat_i;
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   output [31:0]                     wb_dat_o;
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   input [3:0]                       wb_sel_i;
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   input                            wb_we_i;
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   input                            wb_stb_i;
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   input                            wb_cyc_i;
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   output                           wb_ack_o;
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   output [2-1:0]            ss_pad_o;
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   output                           sclk_pad_o;
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   output                           mosi_pad_o;
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   input                            miso_pad_i;
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   reg [31:0]                        wb_dat_o;
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   reg                              wb_ack_o;
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   wire [14-1:0]             ctrl;
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   reg [2-1:0]       ss;
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   wire [32-1:0]             rx;
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   wire [5:0]                        char_len;
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   reg                              char_len_ctrl;
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   reg                              go;
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   wire                             spi_ctrl_sel;
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   wire                             spi_tx_sel;
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   wire                             spi_ss_sel;
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   wire                             tip;
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   wire                             pos_edge;
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   wire                             neg_edge;
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   wire                             last_bit;
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  wire                             rx_negedge;
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  wire                             tx_negedge;
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  wire                             lsb;
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  wire                             ass;
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   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == 4);
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   assign spi_tx_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == 0);
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   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == 6);
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   always @(posedge wb_clk_i or posedge wb_rst_i)
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  begin
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     if (wb_rst_i)
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       wb_dat_o <= #Tp 32'b0;
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     else
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       case (wb_adr_i[4:2])
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         0:    wb_dat_o <= rx;
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         4:    wb_dat_o <= {18'd0, ctrl};
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         5:  wb_dat_o <= {{32-divider_len{1'b0}}, divider};
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         6:      wb_dat_o <= {{32-2{1'b0}}, ss};
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        default:      wb_dat_o  <= rx;
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       endcase
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  end
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   always @(posedge wb_clk_i or posedge wb_rst_i)
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     begin
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        if (wb_rst_i)
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          wb_ack_o <= #Tp 1'b0;
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    else
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      wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
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     end
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   always @(posedge wb_clk_i or posedge wb_rst_i)
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     begin
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        if (wb_rst_i)
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          {go,char_len_ctrl} <= #Tp 2'b01;
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        else if(spi_ctrl_sel && wb_we_i && !tip)
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          begin
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             if (wb_sel_i[0])
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               char_len_ctrl <= #Tp wb_dat_i[5];
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             if (wb_sel_i[1])
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               go <= #Tp wb_dat_i[8];
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          end
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        else if(tip && last_bit && pos_edge)
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          go <= #Tp 1'b0;
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     end
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   assign char_len = char_len_ctrl ? 6'd32 : 6'd8;
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   assign ass = 1'b0;
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   assign lsb = 1'b0;
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   assign rx_negedge = 1'b0;
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   assign tx_negedge = 1'b1;
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   assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len};
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   always @(posedge wb_clk_i or posedge wb_rst_i)
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     if (wb_rst_i)
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       ss <= #Tp {2{1'b0}};
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     else if(spi_ss_sel && wb_we_i && !tip)
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       if (wb_sel_i[0])
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         ss <= #Tp wb_dat_i[2-1:0];
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   assign ss_pad_o = ~((ss & {2{tip & ass}}) | (ss & {2{!ass}}));
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   spi_flash_clgen
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     #
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     (
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      .divider_len(divider_len),
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      .divider(divider)
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      )
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     clgen
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       (
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        .clk_in(wb_clk_i),
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        .rst(wb_rst_i),
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        .go(go),
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        .enable(tip),
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        .last_clk(last_bit),
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        .clk_out(sclk_pad_o),
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        .pos_edge(pos_edge),
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        .neg_edge(neg_edge)
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        );
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   spi_flash_shift  shift
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     (
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      .clk(wb_clk_i),
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      .rst(wb_rst_i),
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      .len(char_len[6-1:0]),
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      .latch(spi_tx_sel & wb_we_i),
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      .byte_sel(wb_sel_i),
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      .go(go),
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      .pos_edge(pos_edge),
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      .neg_edge(neg_edge),
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      .lsb(lsb),
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      .rx_negedge(rx_negedge),
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      .tx_negedge(tx_negedge),
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      .tip(tip),
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      .last(last_bit),
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      .p_in(wb_dat_i),
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      .p_out(rx),
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      .s_clk(sclk_pad_o),
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      .s_in(miso_pad_i),
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      .s_out(mosi_pad_o)
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      );
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endmodule

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