OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [NEWS] - Blame information for rev 216

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 85 jeremybenn
              Or1ksim: The OpenRISC 1000 Architectural Simulator
2
              ==================================================
3
 
4
 
5 143 jeremybenn
New in top of tree
6
==================
7
 
8
The library interface is extended to allow registers and memory to be written
9
directly. This is to allow direct integration as a simulator in GDB.
10
 
11
The following bugs are fixed.
12
* Bug 1797: Or1ksim does not compile with GCC 3.4.4 under Cygwin
13
* Bug 1795: GDB breakpoints do not work with Icache enabled.
14
 
15 134 jeremybenn
New in release 0.4.0
16
====================
17
 
18
No new features or bugs. This is the full release based on 0.4.0rc2.
19
 
20
 
21 127 jeremybenn
New in release 0.4.0rc2
22
=======================
23 107 jeremybenn
 
24
No new features are provided, pending full release of 0.4.0.
25
 
26 124 jeremybenn
The configuration options --enable-arith-flag and --enable-ov-flag have been
27
removed, since they were the source of bugs, notably Bugs 1782, 1783 and 1784.
28
 
29 127 jeremybenn
The configuration option --enable-unsigned-xori has been added to allow a
30
conditional solution to Bug 1790.
31
 
32 107 jeremybenn
The following bugs are fixed.
33
* Bug 1770: l.div does not set carry or give correct exception.
34 114 jeremybenn
* Bug 1771: l.add* do not correctly set the overflow flag.
35 115 jeremybenn
* Bug 1772: l.fl1 not implemented.
36 116 jeremybenn
* Bug 1773: l.maci not correctly implemented.
37 118 jeremybenn
* Bug 1774: l.mulu not implemented.
38 121 jeremybenn
* Bug 1775: l.jalr and l.jr don't trigger alignment exceptions.
39 114 jeremybenn
* Bug 1776: l.addic is not implemented.
40 122 jeremybenn
* Bug 1777: l.macrc not correctly implemented.
41
* Bug 1778: l.ror and l.rori are not implemented.
42 123 jeremybenn
* Bug 1779: l.mtspr implementation is incorrect.
43 124 jeremybenn
* Bug 1782: Or1ksim setting of overflow flag is wrong.
44
* Bug 1783: Or1ksim definition of overflow is wrong.
45
* Bug 1784: Or1ksim does not trigger overflow exceptions.
46 127 jeremybenn
* Bug 1790: l.xori implementation is incorrect.
47 107 jeremybenn
 
48
The following bugs are either cannot be reproduced or will not be fixed.
49
 
50
The following bugs are outstanding
51 114 jeremybenn
* Bug 1758: Memory controller issues. Workaround in the user guide.
52 107 jeremybenn
 
53
 
54 104 jeremybenn
New in release 0.4.0rc1
55
=======================
56 85 jeremybenn
 
57 86 jeremybenn
The following new features are provided.
58 85 jeremybenn
* testbench now renamed testsuite and fully integrated using DejaGNU.
59
  "make check" now works correctly if the OpenRISC toolchain is installed.
60 86 jeremybenn
* New configuration flag --enable-all-tests to enable building of incomplete
61
  tests with "make check".
62 104 jeremybenn
* The library offers an interface via modelled JTAG
63
* Single precision floating point is available.
64 85 jeremybenn
 
65 86 jeremybenn
The user guide is updated.
66
 
67
The following feature requests have been accepted.
68 104 jeremybenn
* Feature  413: ORFPX32 single precision floating point now supported.
69 85 jeremybenn
* Feature  469: Icache tags now intialized as invalid.
70
* Feature 1673: Or1ksim now builds on Mac OS X.
71
* Feature 1678: download, patch and build dirs removed from SVN.
72
 
73 86 jeremybenn
The following feature requests have been rejected.
74 85 jeremybenn
* Feature  399: Writeable SR_LEE bit will not be provided.
75
* Feature  409: Separate ELF loader library already exists in binutils.
76
* Feature  586: Ignoring HW breakpoints is already possible.
77
 
78 89 jeremybenn
The following bugs are fixed.
79
* Bug  534: Test suite fixed (see above).
80
* Bug 1710: mprofile now handles mode args correctly.
81
* Bug 1723: PS2 keyboard error message clearer if RX file won't open.
82 104 jeremybenn
* Bug 1733: Or1ksim now accepts ELF image when working through RSP.
83
* Bug 1767: l.lws is not recognized as an opcode.
84 85 jeremybenn
 
85 89 jeremybenn
The following bugs are either cannot be reproduced or will not be fixed.
86
 
87 104 jeremybenn
The following bugs are outstanding
88
* Bug 1758: Memory controller issues. Workaround in the user guide.
89 89 jeremybenn
 
90 104 jeremybenn
 
91 19 jeremybenn
New in release 0.3.0
92 85 jeremybenn
====================
93
 
94 19 jeremybenn
* No new features or bugs. This is the full release based on rc3.
95
 
96
New in release 0.3.0rc3
97 85 jeremybenn
=======================
98
 
99 19 jeremybenn
* Bug 376 fixed: 32 interrupts now supported
100
* Bug 377 fixed: Level triggered interrupts now work correctly
101
* Bug 378 fixed: xterm UART now works with RSP
102
* Bug 379 fixed: RSP performance improved
103
* Bug 380 fixed: GDB 6.8 stepi now works through Or1ksim JTAG interface
104
* Bug 398 fixed: Lack of support for LEE bit in SR documented
105
* Bug 415 fixed: NPC behavior on writing optionally matches real HW
106
* Bug 418 fixed: All library up calls are host-endian
107
 
108
* Feature 395 added: Boot from 0xf0000000 now enabled.
109
* Feature 408 added: Image file may be NULL for or1ksim_init.
110
* Feature 410 added: RSP now clears sigval on unstalling the processor.
111
* Feature 417 added: Or1ksim prints out its version on startup.
112
 
113
New in release 0.3.0rc2
114 85 jeremybenn
=======================
115
 
116 19 jeremybenn
* A number of bug fixes
117
* Updates to user guide
118
 
119
New in release 0.3.0rc1
120 85 jeremybenn
=======================
121
 
122 19 jeremybenn
* Numerous bug fixes (see the OpenRISC tracker and the ChangeLog file)
123
* User Guide
124
* Consistent coding style and file naming throughout
125
* Support for external SystemC models
126
 
127 85 jeremybenn
New in release 1.9 (old style numbering)
128
========================================
129 19 jeremybenn
 
130
* support for binary COFF
131
* generation of verilog memory models (used when you want to run simulation
132
of OpenRISC processor cores)
133
 
134 85 jeremybenn
New in release 1.2 (old style numbering)
135
========================================
136 19 jeremybenn
 
137
* support for OR16 ISA
138
 
139 85 jeremybenn
New in release 1.1 (old style numbering)
140
========================================
141 19 jeremybenn
 
142
 * First release

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.