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[/] [openrisc/] [trunk/] [or1ksim/] [NEWS] - Blame information for rev 464

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1 85 jeremybenn
              Or1ksim: The OpenRISC 1000 Architectural Simulator
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              ==================================================
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New in top of tree
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==================
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New features (shouldn't be there during a release cycle, but prompted by debug
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needs elsewhere in the tool chain).
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New option --trace provides a one line dump of instruction executed and any
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register or memory location changed after each instruction.
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A new configuration option "use_nmi" is added to the programmable interrupt
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controller (PIC). This causes interrupt lines 0 and 1 to be non-maskable, but
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only in the sense that the corresponding bits in PICMR are hard-wired to 1.
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New config setting for memory initialization "exitnops" fills memory with
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"l.nop 1", which will cause the simulator to exit. Good for tracking pointer
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corruption.
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23 385 jeremybenn
New in release 0.5.0rc2
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=======================
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No new features. This is purely bug fixes post-0.5.0rc1.
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The following bugs are fixed.
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* Bug 1847: Build issues with RSP server (duplicate of 1815).
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* Bug 1846: Casting errors.
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* Bug 1824: Memory controller issue (marked as duplicate of Bug 1758).
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* Bug 1816: Error message when target not set is obscure (duplicate of 1813).
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* Bug 1815: Build errors with RSP server.
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* Bug 1813: "make check" fails before installation.
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The following bugs are outstanding
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* Bug 1823: Configuration file error line numbers are wrong.
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* Bug 1822: ATA configuration is broken. Documented in user guide.
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* Bug 1758: Memory controller issues. Workaround in the user guide.
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New in release 0.5.0rc1
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=======================
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The floating point implementation is now based on John Hauser's "softfloat"
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package, ensuring rigorous compliance with the IEEE 754-2008 standard.
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The library interface is extended to allow registers and memory to be written
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directly and processor stalled and unstalled. This is to allow direct
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integration as a simulator in GDB.
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52 346 jeremybenn
Some of the existing library interface functions have different prototypes.
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54 224 jeremybenn
The "include" feature of configuration files (which never worked, but no one
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ever noticed) is dropped.
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If the configuration file is not found in the local directory, it is searched
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for in the ${HOME}/.or1ksim directory, then (for backwards compatibility) the
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${HOME}/.or1k directory.
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If no simulation file is specified, then sim.cfg is not searched for as a
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default.
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64 346 jeremybenn
New options are added -q|--quiet, -V|--verbose, -m|--memory and
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--report-memory-errors. The semantics of --nosrv and --src otpions are changed.
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67 346 jeremybenn
There is a configuration option to collect statistics on instruction execution
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in binary form.
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In previous versions, Bus exceptions were unique in that they produced an
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error message on standard output. The default is now for this exception to be
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handled silently, unless requested by --report-memory-errors.
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The following feature requests have been accepted.
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* Feature  393: Integrate Or1ksim in GDB.
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The following bugs are fixed.
78 346 jeremybenn
* Bug 1821: Reference configuration file has defective debug section.
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* Bug 1817: Reference configuration file missing from distribution.
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* Bug 1795: GDB breakpoints do not work with the instruction cache.
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82 346 jeremybenn
The following bugs are either cannot be reproduced or will not be fixed.
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The following bugs are outstanding
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* Bug 1824: Memory controller issue (probably the same as Bug 1758).
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* Bug 1823: Configuration file error line numbers are wrong.
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* Bug 1822: ATA section in configuration file is broken.
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* Bug 1816: Error message when target not set is obscure.
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* Bug 1813: "make check" fails before installation.
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* Bug 1758: Memory controller issues. Workaround in the user guide.
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New in release 0.4.0
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====================
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No new features or bugs. This is the full release based on 0.4.0rc2.
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New in release 0.4.0rc2
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=======================
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No new features are provided, pending full release of 0.4.0.
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The configuration options --enable-arith-flag and --enable-ov-flag have been
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removed, since they were the source of bugs, notably Bugs 1782, 1783 and 1784.
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The configuration option --enable-unsigned-xori has been added to allow a
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conditional solution to Bug 1790.
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The following bugs are fixed.
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* Bug 1770: l.div does not set carry or give correct exception.
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* Bug 1771: l.add* do not correctly set the overflow flag.
113 115 jeremybenn
* Bug 1772: l.fl1 not implemented.
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* Bug 1773: l.maci not correctly implemented.
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* Bug 1774: l.mulu not implemented.
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* Bug 1775: l.jalr and l.jr don't trigger alignment exceptions.
117 114 jeremybenn
* Bug 1776: l.addic is not implemented.
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* Bug 1777: l.macrc not correctly implemented.
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* Bug 1778: l.ror and l.rori are not implemented.
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* Bug 1779: l.mtspr implementation is incorrect.
121 124 jeremybenn
* Bug 1782: Or1ksim setting of overflow flag is wrong.
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* Bug 1783: Or1ksim definition of overflow is wrong.
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* Bug 1784: Or1ksim does not trigger overflow exceptions.
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* Bug 1790: l.xori implementation is incorrect.
125 107 jeremybenn
 
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The following bugs are either cannot be reproduced or will not be fixed.
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The following bugs are outstanding
129 114 jeremybenn
* Bug 1758: Memory controller issues. Workaround in the user guide.
130 107 jeremybenn
 
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New in release 0.4.0rc1
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=======================
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The following new features are provided.
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* testbench now renamed testsuite and fully integrated using DejaGNU.
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  "make check" now works correctly if the OpenRISC toolchain is installed.
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* New configuration flag --enable-all-tests to enable building of incomplete
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  tests with "make check".
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* The library offers an interface via modelled JTAG
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* Single precision floating point is available.
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The user guide is updated.
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The following feature requests have been accepted.
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* Feature  413: ORFPX32 single precision floating point now supported.
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* Feature  469: Icache tags now intialized as invalid.
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* Feature 1673: Or1ksim now builds on Mac OS X.
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* Feature 1678: download, patch and build dirs removed from SVN.
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The following feature requests have been rejected.
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* Feature  399: Writeable SR_LEE bit will not be provided.
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* Feature  409: Separate ELF loader library already exists in binutils.
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* Feature  586: Ignoring HW breakpoints is already possible.
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156 89 jeremybenn
The following bugs are fixed.
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* Bug  534: Test suite fixed (see above).
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* Bug 1710: mprofile now handles mode args correctly.
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* Bug 1723: PS2 keyboard error message clearer if RX file won't open.
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* Bug 1733: Or1ksim now accepts ELF image when working through RSP.
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* Bug 1767: l.lws is not recognized as an opcode.
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The following bugs are either cannot be reproduced or will not be fixed.
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165 104 jeremybenn
The following bugs are outstanding
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* Bug 1758: Memory controller issues. Workaround in the user guide.
167 89 jeremybenn
 
168 104 jeremybenn
 
169 19 jeremybenn
New in release 0.3.0
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====================
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* No new features or bugs. This is the full release based on rc3.
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New in release 0.3.0rc3
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=======================
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* Bug 376 fixed: 32 interrupts now supported
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* Bug 377 fixed: Level triggered interrupts now work correctly
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* Bug 378 fixed: xterm UART now works with RSP
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* Bug 379 fixed: RSP performance improved
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* Bug 380 fixed: GDB 6.8 stepi now works through Or1ksim JTAG interface
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* Bug 398 fixed: Lack of support for LEE bit in SR documented
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* Bug 415 fixed: NPC behavior on writing optionally matches real HW
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* Bug 418 fixed: All library up calls are host-endian
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* Feature 395 added: Boot from 0xf0000000 now enabled.
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* Feature 408 added: Image file may be NULL for or1ksim_init.
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* Feature 410 added: RSP now clears sigval on unstalling the processor.
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* Feature 417 added: Or1ksim prints out its version on startup.
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New in release 0.3.0rc2
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=======================
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* A number of bug fixes
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* Updates to user guide
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New in release 0.3.0rc1
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=======================
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* Numerous bug fixes (see the OpenRISC tracker and the ChangeLog file)
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* User Guide
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* Consistent coding style and file naming throughout
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* Support for external SystemC models
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New in release 1.9 (old style numbering)
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========================================
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* support for binary COFF
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* generation of verilog memory models (used when you want to run simulation
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of OpenRISC processor cores)
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New in release 1.2 (old style numbering)
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========================================
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* support for OR16 ISA
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New in release 1.1 (old style numbering)
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========================================
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 * First release

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