OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [NEWS] - Blame information for rev 105

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 85 jeremybenn
              Or1ksim: The OpenRISC 1000 Architectural Simulator
2
              ==================================================
3
 
4
 
5 104 jeremybenn
New in release 0.4.0rc1
6
=======================
7 85 jeremybenn
 
8 86 jeremybenn
The following new features are provided.
9 85 jeremybenn
* testbench now renamed testsuite and fully integrated using DejaGNU.
10
  "make check" now works correctly if the OpenRISC toolchain is installed.
11 86 jeremybenn
* New configuration flag --enable-all-tests to enable building of incomplete
12
  tests with "make check".
13 104 jeremybenn
* The library offers an interface via modelled JTAG
14
* Single precision floating point is available.
15 85 jeremybenn
 
16 86 jeremybenn
The user guide is updated.
17
 
18
The following feature requests have been accepted.
19 104 jeremybenn
* Feature  413: ORFPX32 single precision floating point now supported.
20 85 jeremybenn
* Feature  469: Icache tags now intialized as invalid.
21
* Feature 1673: Or1ksim now builds on Mac OS X.
22
* Feature 1678: download, patch and build dirs removed from SVN.
23
 
24 86 jeremybenn
The following feature requests have been rejected.
25 85 jeremybenn
* Feature  399: Writeable SR_LEE bit will not be provided.
26
* Feature  409: Separate ELF loader library already exists in binutils.
27
* Feature  586: Ignoring HW breakpoints is already possible.
28
 
29 89 jeremybenn
The following bugs are fixed.
30
* Bug  534: Test suite fixed (see above).
31
* Bug 1710: mprofile now handles mode args correctly.
32
* Bug 1723: PS2 keyboard error message clearer if RX file won't open.
33 104 jeremybenn
* Bug 1733: Or1ksim now accepts ELF image when working through RSP.
34
* Bug 1767: l.lws is not recognized as an opcode.
35 85 jeremybenn
 
36 89 jeremybenn
The following bugs are either cannot be reproduced or will not be fixed.
37
 
38 104 jeremybenn
The following bugs are outstanding
39
* Bug 1758: Memory controller issues. Workaround in the user guide.
40 89 jeremybenn
 
41 104 jeremybenn
 
42 19 jeremybenn
New in release 0.3.0
43 85 jeremybenn
====================
44
 
45 19 jeremybenn
* No new features or bugs. This is the full release based on rc3.
46
 
47
New in release 0.3.0rc3
48 85 jeremybenn
=======================
49
 
50 19 jeremybenn
* Bug 376 fixed: 32 interrupts now supported
51
* Bug 377 fixed: Level triggered interrupts now work correctly
52
* Bug 378 fixed: xterm UART now works with RSP
53
* Bug 379 fixed: RSP performance improved
54
* Bug 380 fixed: GDB 6.8 stepi now works through Or1ksim JTAG interface
55
* Bug 398 fixed: Lack of support for LEE bit in SR documented
56
* Bug 415 fixed: NPC behavior on writing optionally matches real HW
57
* Bug 418 fixed: All library up calls are host-endian
58
 
59
* Feature 395 added: Boot from 0xf0000000 now enabled.
60
* Feature 408 added: Image file may be NULL for or1ksim_init.
61
* Feature 410 added: RSP now clears sigval on unstalling the processor.
62
* Feature 417 added: Or1ksim prints out its version on startup.
63
 
64
New in release 0.3.0rc2
65 85 jeremybenn
=======================
66
 
67 19 jeremybenn
* A number of bug fixes
68
* Updates to user guide
69
 
70
New in release 0.3.0rc1
71 85 jeremybenn
=======================
72
 
73 19 jeremybenn
* Numerous bug fixes (see the OpenRISC tracker and the ChangeLog file)
74
* User Guide
75
* Consistent coding style and file naming throughout
76
* Support for external SystemC models
77
 
78 85 jeremybenn
New in release 1.9 (old style numbering)
79
========================================
80 19 jeremybenn
 
81
* support for binary COFF
82
* generation of verilog memory models (used when you want to run simulation
83
of OpenRISC processor cores)
84
 
85 85 jeremybenn
New in release 1.2 (old style numbering)
86
========================================
87 19 jeremybenn
 
88
* support for OR16 ISA
89
 
90 85 jeremybenn
New in release 1.1 (old style numbering)
91
========================================
92 19 jeremybenn
 
93
 * First release

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.