URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
[/] [openrisc/] [trunk/] [or1ksim/] [NEWS] - Blame information for rev 33
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
19 |
jeremybenn |
New in release 0.3.0
|
| 2 |
|
|
* No new features or bugs. This is the full release based on rc3.
|
| 3 |
|
|
|
| 4 |
|
|
New in release 0.3.0rc3
|
| 5 |
|
|
* Bug 376 fixed: 32 interrupts now supported
|
| 6 |
|
|
* Bug 377 fixed: Level triggered interrupts now work correctly
|
| 7 |
|
|
* Bug 378 fixed: xterm UART now works with RSP
|
| 8 |
|
|
* Bug 379 fixed: RSP performance improved
|
| 9 |
|
|
* Bug 380 fixed: GDB 6.8 stepi now works through Or1ksim JTAG interface
|
| 10 |
|
|
* Bug 398 fixed: Lack of support for LEE bit in SR documented
|
| 11 |
|
|
* Bug 415 fixed: NPC behavior on writing optionally matches real HW
|
| 12 |
|
|
* Bug 418 fixed: All library up calls are host-endian
|
| 13 |
|
|
|
| 14 |
|
|
* Feature 395 added: Boot from 0xf0000000 now enabled.
|
| 15 |
|
|
* Feature 408 added: Image file may be NULL for or1ksim_init.
|
| 16 |
|
|
* Feature 410 added: RSP now clears sigval on unstalling the processor.
|
| 17 |
|
|
* Feature 417 added: Or1ksim prints out its version on startup.
|
| 18 |
|
|
|
| 19 |
|
|
New in release 0.3.0rc2
|
| 20 |
|
|
* A number of bug fixes
|
| 21 |
|
|
* Updates to user guide
|
| 22 |
|
|
|
| 23 |
|
|
New in release 0.3.0rc1
|
| 24 |
|
|
* Numerous bug fixes (see the OpenRISC tracker and the ChangeLog file)
|
| 25 |
|
|
* User Guide
|
| 26 |
|
|
* Consistent coding style and file naming throughout
|
| 27 |
|
|
* Support for external SystemC models
|
| 28 |
|
|
|
| 29 |
|
|
New in release 1.9 (old style numbering):
|
| 30 |
|
|
|
| 31 |
|
|
* support for binary COFF
|
| 32 |
|
|
* generation of verilog memory models (used when you want to run simulation
|
| 33 |
|
|
of OpenRISC processor cores)
|
| 34 |
|
|
|
| 35 |
|
|
New in release 1.2 (old style numbering):
|
| 36 |
|
|
|
| 37 |
|
|
* support for OR16 ISA
|
| 38 |
|
|
|
| 39 |
|
|
New in release 1.1 (old style numbering):
|
| 40 |
|
|
|
| 41 |
|
|
* First release
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.