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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
[/] [openrisc/] [trunk/] [or1ksim/] [NEWS] - Blame information for rev 39
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19 |
jeremybenn |
New in release 0.3.0
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* No new features or bugs. This is the full release based on rc3.
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New in release 0.3.0rc3
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* Bug 376 fixed: 32 interrupts now supported
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* Bug 377 fixed: Level triggered interrupts now work correctly
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* Bug 378 fixed: xterm UART now works with RSP
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* Bug 379 fixed: RSP performance improved
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* Bug 380 fixed: GDB 6.8 stepi now works through Or1ksim JTAG interface
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* Bug 398 fixed: Lack of support for LEE bit in SR documented
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* Bug 415 fixed: NPC behavior on writing optionally matches real HW
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* Bug 418 fixed: All library up calls are host-endian
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* Feature 395 added: Boot from 0xf0000000 now enabled.
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* Feature 408 added: Image file may be NULL for or1ksim_init.
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* Feature 410 added: RSP now clears sigval on unstalling the processor.
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* Feature 417 added: Or1ksim prints out its version on startup.
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New in release 0.3.0rc2
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* A number of bug fixes
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* Updates to user guide
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New in release 0.3.0rc1
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* Numerous bug fixes (see the OpenRISC tracker and the ChangeLog file)
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* User Guide
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* Consistent coding style and file naming throughout
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* Support for external SystemC models
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New in release 1.9 (old style numbering):
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* support for binary COFF
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* generation of verilog memory models (used when you want to run simulation
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of OpenRISC processor cores)
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New in release 1.2 (old style numbering):
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* support for OR16 ISA
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| 39 |
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New in release 1.1 (old style numbering):
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* First release
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