OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [NEWS] - Blame information for rev 88

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 85 jeremybenn
              Or1ksim: The OpenRISC 1000 Architectural Simulator
2
              ==================================================
3
 
4
 
5
New in top of tree
6
==================
7
 
8 86 jeremybenn
The following new features are provided.
9 85 jeremybenn
* testbench now renamed testsuite and fully integrated using DejaGNU.
10
  "make check" now works correctly if the OpenRISC toolchain is installed.
11 86 jeremybenn
* New configuration flag --enable-all-tests to enable building of incomplete
12
  tests with "make check".
13 85 jeremybenn
 
14 86 jeremybenn
The user guide is updated.
15
 
16
The following feature requests have been accepted.
17 85 jeremybenn
* Feature  469: Icache tags now intialized as invalid.
18
* Feature 1673: Or1ksim now builds on Mac OS X.
19
* Feature 1678: download, patch and build dirs removed from SVN.
20
 
21 86 jeremybenn
The following feature requests have been rejected.
22 85 jeremybenn
* Feature  399: Writeable SR_LEE bit will not be provided.
23
* Feature  409: Separate ELF loader library already exists in binutils.
24
* Feature  586: Ignoring HW breakpoints is already possible.
25
 
26
The following bugs are fixed:
27
* Bug 1773: Or1ksim now accepts ELF image when working through RSP.
28 86 jeremybenn
* Bug 1723: PS2 keyboard error message clearer if RX file won't open.
29 88 jeremybenn
* Bug 1710: mprofile now handles mode args correctly.
30 85 jeremybenn
 
31 19 jeremybenn
New in release 0.3.0
32 85 jeremybenn
====================
33
 
34 19 jeremybenn
* No new features or bugs. This is the full release based on rc3.
35
 
36
New in release 0.3.0rc3
37 85 jeremybenn
=======================
38
 
39 19 jeremybenn
* Bug 376 fixed: 32 interrupts now supported
40
* Bug 377 fixed: Level triggered interrupts now work correctly
41
* Bug 378 fixed: xterm UART now works with RSP
42
* Bug 379 fixed: RSP performance improved
43
* Bug 380 fixed: GDB 6.8 stepi now works through Or1ksim JTAG interface
44
* Bug 398 fixed: Lack of support for LEE bit in SR documented
45
* Bug 415 fixed: NPC behavior on writing optionally matches real HW
46
* Bug 418 fixed: All library up calls are host-endian
47
 
48
* Feature 395 added: Boot from 0xf0000000 now enabled.
49
* Feature 408 added: Image file may be NULL for or1ksim_init.
50
* Feature 410 added: RSP now clears sigval on unstalling the processor.
51
* Feature 417 added: Or1ksim prints out its version on startup.
52
 
53
New in release 0.3.0rc2
54 85 jeremybenn
=======================
55
 
56 19 jeremybenn
* A number of bug fixes
57
* Updates to user guide
58
 
59
New in release 0.3.0rc1
60 85 jeremybenn
=======================
61
 
62 19 jeremybenn
* Numerous bug fixes (see the OpenRISC tracker and the ChangeLog file)
63
* User Guide
64
* Consistent coding style and file naming throughout
65
* Support for external SystemC models
66
 
67 85 jeremybenn
New in release 1.9 (old style numbering)
68
========================================
69 19 jeremybenn
 
70
* support for binary COFF
71
* generation of verilog memory models (used when you want to run simulation
72
of OpenRISC processor cores)
73
 
74 85 jeremybenn
New in release 1.2 (old style numbering)
75
========================================
76 19 jeremybenn
 
77
* support for OR16 ISA
78
 
79 85 jeremybenn
New in release 1.1 (old style numbering)
80
========================================
81 19 jeremybenn
 
82
 * First release

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.