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jeremybenn |
/* branch-predict.c -- branch prediction simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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/* Branch prediction functions. At the moment this functions only simulate
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functionality of branch prediction and do not influence on
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fetche/decode/execute stages. They are here only to verify performance of
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various branch prediction configurations. */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "port.h"
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/* System includes */
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#include <stdio.h>
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#include <errno.h>
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#include <stdarg.h>
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/* Package includes */
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#include "sim-config.h"
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#include "arch.h"
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#include "stats.h"
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/* Branch prediction buffer */
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/* Length of BPB */
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#define BPB_LEN 64
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/* Number of BPB ways (1, 2, 3 etc.). */
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#define BPB_WAYS 1
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/* Number of prediction states (2, 4, 8 etc.). */
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#define BPB_PSTATES 2
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/* Number of usage states (2, 3, 4 etc.). */
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#define BPB_USTATES 2
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/* branch prediction buffer entry */
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struct bpb_entry
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{
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struct
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{
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oraddr_t addr; /* address of a branch insn */
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int taken; /* taken == 1, not taken == 0 OR */
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/* strongly taken == 3, taken == 2,
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not taken == 1, strongly not taken == 0 */
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int lru; /* least recently == 0 */
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} way[BPB_WAYS];
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} bpb[BPB_LEN];
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void
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bpb_info ()
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{
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if (!config.bpb.enabled)
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{
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PRINTF ("BPB not simulated. Check -bpb option.\n");
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return;
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}
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PRINTF ("BPB %d bytes: ",
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BPB_LEN * BPB_WAYS * (BPB_PSTATES + BPB_USTATES) / 8);
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PRINTF ("%d ways, %d sets, %d bits/prediction\n", BPB_WAYS, BPB_LEN,
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BPB_PSTATES + BPB_USTATES);
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}
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/* First check if branch is already in the cache and if it is:
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- increment BPB hit stats,
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- set 'lru' at this way to BPB_USTATES - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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- increment correct/incorrect stats according to BPB 'taken' field
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and 'taken' variable,
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- increment or decrement BPB taken field according to 'taken' variable
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and if not:
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- increment BPB miss stats
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- find lru way and entry and replace old address with 'addr' and
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'taken' field with (BPB_PSTATES/2 - 1) + 'taken'
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- set 'lru' with BPB_USTATES - 1 and decrement 'lru' of other
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ways unless they have reached 0
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*/
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void
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bpb_update (oraddr_t addr, int taken)
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{
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int entry, way = -1;
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int i;
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/* BPB simulation enabled/disabled. */
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if (!config.bpb.enabled)
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return;
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/* Calc entry. */
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entry = addr % BPB_LEN;
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/* Scan all ways and try to find our addr. */
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for (i = 0; i < BPB_WAYS; i++)
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if (bpb[entry].way[i].addr == addr)
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way = i;
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/* Did we find our cached branch? */
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if (way >= 0)
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{ /* Yes, we did. */
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or1k_mstats.bpb.hit++;
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for (i = 0; i < BPB_WAYS; i++)
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if (bpb[entry].way[i].lru)
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bpb[entry].way[i].lru--;
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bpb[entry].way[way].lru = BPB_USTATES - 1;
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if (bpb[entry].way[way].taken / (BPB_PSTATES / 2) == taken)
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or1k_mstats.bpb.correct++;
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else
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or1k_mstats.bpb.incorrect++;
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if (taken && (bpb[entry].way[way].taken < BPB_PSTATES - 1))
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bpb[entry].way[way].taken++;
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else if (!taken && (bpb[entry].way[way].taken))
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bpb[entry].way[way].taken--;
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}
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else
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{ /* No, we didn't. */
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int minlru = BPB_USTATES - 1;
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int minway = 0;
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or1k_mstats.bpb.miss++;
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for (i = 0; i < BPB_WAYS; i++)
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if (bpb[entry].way[i].lru < minlru)
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minway = i;
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bpb[entry].way[minway].addr = addr;
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bpb[entry].way[minway].taken = (BPB_PSTATES / 2 - 1) + taken;
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for (i = 0; i < BPB_WAYS; i++)
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if (bpb[entry].way[i].lru)
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bpb[entry].way[i].lru--;
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bpb[entry].way[minway].lru = BPB_USTATES - 1;
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}
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}
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/* Branch target instruction cache */
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/* Length of BTIC */
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#define BTIC_LEN 128
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/* Number of BTIC ways (1, 2, 3 etc.). */
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#define BTIC_WAYS 2
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/* Number of usage states (2, 3, 4 etc.). */
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#define BTIC_USTATES 2
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/* Target block size in bytes. */
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#define BTIC_BLOCKSIZE 4
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struct btic_entry
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{
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struct
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{
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oraddr_t addr; /* cached target address of a branch */
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int lru; /* least recently used */
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char *insn; /* cached insn at target address (not used currently) */
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} way[BTIC_WAYS];
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} btic[BTIC_LEN];
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void
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btic_info ()
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{
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if (!config.bpb.btic)
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{
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PRINTF ("BTIC not simulated. Check --btic option.\n");
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return;
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}
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PRINTF ("BTIC %d bytes: ",
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BTIC_LEN * BTIC_WAYS * (BTIC_USTATES + BTIC_BLOCKSIZE * 8) / 8);
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PRINTF ("%d ways, %d sets, %d bits/target\n", BTIC_WAYS, BTIC_LEN,
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BTIC_USTATES + BTIC_BLOCKSIZE * 8);
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}
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/* First check if target addr is already in the cache and if it is:
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- increment BTIC hit stats,
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- set 'lru' at this way to BTIC_USTATES - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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and if not:
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- increment BTIC miss stats
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- find lru way and entry and replace old address with 'addr' and
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'insn' with NULL
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- set 'lru' with BTIC_USTATES - 1 and decrement 'lru' of other
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ways unless they have reached 0
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*/
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void
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btic_update (oraddr_t targetaddr)
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{
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int entry, way = -1;
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int i;
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/* BTIC simulation enabled/disabled. */
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if (!config.bpb.btic)
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return;
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/* Calc entry. */
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entry = targetaddr % BTIC_LEN;
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/* Scan all ways and try to find our addr. */
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for (i = 0; i < BTIC_WAYS; i++)
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if (btic[entry].way[i].addr == targetaddr)
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way = i;
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/* Did we find our cached branch? */
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if (way >= 0)
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{ /* Yes, we did. */
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or1k_mstats.btic.hit++;
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for (i = 0; i < BTIC_WAYS; i++)
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if (btic[entry].way[i].lru)
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btic[entry].way[i].lru--;
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btic[entry].way[way].lru = BTIC_USTATES - 1;
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}
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else
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{ /* No, we didn't. */
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int minlru = BTIC_USTATES - 1;
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int minway = 0;
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or1k_mstats.btic.miss++;
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for (i = 0; i < BTIC_WAYS; i++)
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if (btic[entry].way[i].lru < minlru)
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minway = i;
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btic[entry].way[minway].addr = targetaddr;
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btic[entry].way[minway].insn = NULL;
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for (i = 0; i < BTIC_WAYS; i++)
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if (btic[entry].way[i].lru)
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btic[entry].way[i].lru--;
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btic[entry].way[minway].lru = BTIC_USTATES - 1;
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}
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}
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/*----------------------------------------------------[ BPB configuration ]---*/
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static void
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bpb_enabled (union param_val val, void *dat)
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{
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config.bpb.enabled = val.int_val;
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}
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static void
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bpb_btic (union param_val val, void *dat)
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{
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config.bpb.btic = val.int_val;
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}
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static void
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bpb_sbp_bnf_fwd (union param_val val, void *dat)
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{
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config.bpb.sbp_bnf_fwd = val.int_val;
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}
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static void
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bpb_sbp_bf_fwd (union param_val val, void *dat)
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{
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config.bpb.sbp_bf_fwd = val.int_val;
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}
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static void
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bpb_missdelay (union param_val val, void *dat)
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{
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config.bpb.missdelay = val.int_val;
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}
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static void
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bpb_hitdelay (union param_val val, void *dat)
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{
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config.bpb.hitdelay = val.int_val;
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}
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void
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reg_bpb_sec ()
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{
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struct config_section *sec = reg_config_sec ("bpb", NULL, NULL);
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jeremybenn |
reg_config_param (sec, "enabled", PARAMT_INT, bpb_enabled);
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reg_config_param (sec, "btic", PARAMT_INT, bpb_btic);
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reg_config_param (sec, "sbp_bnf_fwd", PARAMT_INT, bpb_sbp_bnf_fwd);
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reg_config_param (sec, "sbp_bf_fwd", PARAMT_INT, bpb_sbp_bf_fwd);
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reg_config_param (sec, "missdelay", PARAMT_INT, bpb_missdelay);
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reg_config_param (sec, "hitdelay", PARAMT_INT, bpb_hitdelay);
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19 |
jeremybenn |
}
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