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[/] [openrisc/] [trunk/] [or1ksim/] [cache/] [dcache-model.c] - Blame information for rev 23

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1 19 jeremybenn
/* dcache-model.c -- data cache simulation
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
/* Cache functions.  At the moment these functions only simulate functionality
27
   of data caches and do not influence on fetche/decode/execute stages and
28
   timings.  They are here only to verify performance of various cache
29
   configurations. */
30
 
31
 
32
/* Autoconf and/or portability configuration */
33
#include "config.h"
34
 
35
/* Package includes */
36
#include "dcache-model.h"
37
#include "execute.h"
38
#include "spr-defs.h"
39
#include "abstract.h"
40
#include "stats.h"
41
#include "misc.h"
42
 
43
 
44
/* Data cache */
45
 
46
struct dc_set
47
{
48
  struct
49
  {
50
    uint32_t line[MAX_DC_BLOCK_SIZE/4];
51
    oraddr_t tagaddr;           /* tag address */
52
    int lru;                    /* least recently used */
53
  } way[MAX_DC_WAYS];
54
} dc[MAX_DC_SETS];
55
 
56
void
57
dc_info (void)
58
{
59
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
60
    {
61
      PRINTF ("DCache not implemented. Set UPR[DCP].\n");
62
      return;
63
    }
64
 
65
  PRINTF ("Data cache %dKB: ",
66
          config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
67
  PRINTF ("%d ways, %d sets, block size %d bytes\n", config.dc.nways,
68
          config.dc.nsets, config.dc.blocksize);
69
}
70
 
71
/* First check if data is already in the cache and if it is:
72
    - increment DC read hit stats,
73
    - set 'lru' at this way to config.dc.ustates - 1 and
74
      decrement 'lru' of other ways unless they have reached 0,
75
   and if not:
76
    - increment DC read miss stats
77
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
78
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
79
      ways unless they have reached 0
80
    - refill cache line
81
*/
82
 
83
uint32_t
84
dc_simulate_read (oraddr_t dataaddr, oraddr_t virt_addr, int width)
85
{
86
  int set, way = -1;
87
  int i;
88
  oraddr_t tagaddr;
89
  uint32_t tmp = 0;
90
 
91
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
92
      !(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci)
93
    {
94
      if (width == 4)
95
        tmp = evalsim_mem32 (dataaddr, virt_addr);
96
      else if (width == 2)
97
        tmp = evalsim_mem16 (dataaddr, virt_addr);
98
      else if (width == 1)
99
        tmp = evalsim_mem8 (dataaddr, virt_addr);
100
 
101
      if (cur_area && cur_area->log)
102
        fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
103
                 dataaddr, tmp);
104
 
105
      return tmp;
106
    }
107
 
108
  /* Which set to check out? */
109
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
110
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
111
 
112
  /* Scan all ways and try to find a matching way. */
113
  for (i = 0; i < config.dc.nways; i++)
114
    if (dc[set].way[i].tagaddr == tagaddr)
115
      way = i;
116
 
117
  /* Did we find our cached data? */
118
  if (way >= 0)
119
    {                           /* Yes, we did. */
120
      dc_stats.readhit++;
121
 
122
      for (i = 0; i < config.dc.nways; i++)
123
        if (dc[set].way[i].lru > dc[set].way[way].lru)
124
          dc[set].way[i].lru--;
125
      dc[set].way[way].lru = config.dc.ustates - 1;
126
      runtime.sim.mem_cycles += config.dc.load_hitdelay;
127
 
128
      tmp =
129
        dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
130
      if (width == 4)
131
        return tmp;
132
      else if (width == 2)
133
        {
134
          tmp = ((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
135
          return tmp;
136
        }
137
      else if (width == 1)
138
        {
139
          tmp = ((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
140
          return tmp;
141
        }
142
    }
143
  else
144
    {                           /* No, we didn't. */
145
      int minlru = config.dc.ustates - 1;
146
      int minway = 0;
147
 
148
      dc_stats.readmiss++;
149
 
150
      for (i = 0; i < config.dc.nways; i++)
151
        {
152
          if (dc[set].way[i].lru < minlru)
153
            {
154
              minway = i;
155
              minlru = dc[set].way[i].lru;
156
            }
157
        }
158
 
159
      for (i = 0; i < (config.dc.blocksize); i += 4)
160
        {
161
          /* FIXME: What is the virtual address meant to be? (ie. What happens if
162
           * we read out of memory while refilling a cache line?) */
163
          tmp =
164
            evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
165
                           (((dataaddr & ~ADDR_C (3)) +
166
                             i) & (config.dc.blocksize - 1)), 0);
167
 
168
          dc[set].way[minway].
169
            line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] = tmp;
170
          if (!cur_area)
171
            {
172
              dc[set].way[minway].tagaddr = -1;
173
              dc[set].way[minway].lru = 0;
174
              return 0;
175
            }
176
          else if (cur_area->log)
177
            fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
178
                     dataaddr, tmp);
179
        }
180
 
181
      dc[set].way[minway].tagaddr = tagaddr;
182
      for (i = 0; i < config.dc.nways; i++)
183
        if (dc[set].way[i].lru)
184
          dc[set].way[i].lru--;
185
      dc[set].way[minway].lru = config.dc.ustates - 1;
186
      runtime.sim.mem_cycles += config.dc.load_missdelay;
187
 
188
      tmp =
189
        dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
190
      if (width == 4)
191
        return tmp;
192
      else if (width == 2)
193
        {
194
          tmp = (tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff;
195
          return tmp;
196
        }
197
      else if (width == 1)
198
        {
199
          tmp = (tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff;
200
          return tmp;
201
        }
202
    }
203
  return 0;
204
}
205
 
206
/* First check if data is already in the cache and if it is:
207
    - increment DC write hit stats,
208
    - set 'lru' at this way to config.dc.ustates - 1 and
209
      decrement 'lru' of other ways unless they have reached 0,
210
   and if not:
211
    - increment DC write miss stats
212
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
213
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
214
      ways unless they have reached 0
215
*/
216
 
217
void
218
dc_simulate_write (oraddr_t dataaddr, oraddr_t virt_addr, uint32_t data,
219
                   int width)
220
{
221
  int set, way = -1;
222
  int i;
223
  oraddr_t tagaddr;
224
  uint32_t tmp;
225
 
226
  if (width == 4)
227
    setsim_mem32 (dataaddr, virt_addr, data);
228
  else if (width == 2)
229
    setsim_mem16 (dataaddr, virt_addr, data);
230
  else if (width == 1)
231
    setsim_mem8 (dataaddr, virt_addr, data);
232
 
233
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
234
      !(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci || !cur_area)
235
    return;
236
 
237
  /* Which set to check out? */
238
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
239
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
240
 
241
  /* Scan all ways and try to find a matching way. */
242
  for (i = 0; i < config.dc.nways; i++)
243
    if (dc[set].way[i].tagaddr == tagaddr)
244
      way = i;
245
 
246
  /* Did we find our cached data? */
247
  if (way >= 0)
248
    {                           /* Yes, we did. */
249
      dc_stats.writehit++;
250
 
251
      for (i = 0; i < config.dc.nways; i++)
252
        if (dc[set].way[i].lru > dc[set].way[way].lru)
253
          dc[set].way[i].lru--;
254
      dc[set].way[way].lru = config.dc.ustates - 1;
255
      runtime.sim.mem_cycles += config.dc.store_hitdelay;
256
 
257
      tmp =
258
        dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
259
      if (width == 4)
260
        tmp = data;
261
      else if (width == 2)
262
        {
263
          tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
264
          tmp |= (data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
265
        }
266
      else if (width == 1)
267
        {
268
          tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
269
          tmp |= (data & 0xff) << (8 * (3 - (dataaddr & 3)));
270
        }
271
      dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] =
272
        tmp;
273
    }
274
  else
275
    {                           /* No, we didn't. */
276
      int minlru = config.dc.ustates - 1;
277
      int minway = 0;
278
 
279
      dc_stats.writemiss++;
280
 
281
      for (i = 0; i < config.dc.nways; i++)
282
        if (dc[set].way[i].lru < minlru)
283
          minway = i;
284
 
285
      for (i = 0; i < (config.dc.blocksize); i += 4)
286
        {
287
          dc[set].way[minway].
288
            line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
289
            /* FIXME: Same comment as in dc_simulate_read */
290
            evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
291
                           (((dataaddr & ~3ul) + i) & (config.dc.blocksize -
292
                                                       1)), 0);
293
          if (!cur_area)
294
            {
295
              dc[set].way[minway].tagaddr = -1;
296
              dc[set].way[minway].lru = 0;
297
              return;
298
            }
299
        }
300
 
301
      dc[set].way[minway].tagaddr = tagaddr;
302
      for (i = 0; i < config.dc.nways; i++)
303
        if (dc[set].way[i].lru)
304
          dc[set].way[i].lru--;
305
      dc[set].way[minway].lru = config.dc.ustates - 1;
306
      runtime.sim.mem_cycles += config.dc.store_missdelay;
307
    }
308
}
309
 
310
/* First check if data is already in the cache and if it is:
311
    - invalidate block if way isn't locked
312
   otherwise don't do anything.
313
*/
314
 
315
void
316
dc_inv (oraddr_t dataaddr)
317
{
318
  int set, way = -1;
319
  int i;
320
  oraddr_t tagaddr;
321
 
322
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
323
    return;
324
 
325
  /* Which set to check out? */
326
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
327
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
328
 
329
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE))
330
    {
331
      for (i = 0; i < config.dc.nways; i++)
332
        {
333
          dc[set].way[i].tagaddr = -1;
334
          dc[set].way[i].lru = 0;
335
        }
336
      return;
337
    }
338
  /* Scan all ways and try to find a matching way. */
339
  for (i = 0; i < config.dc.nways; i++)
340
    if (dc[set].way[i].tagaddr == tagaddr)
341
      way = i;
342
 
343
  /* Did we find our cached data? */
344
  if (way >= 0)
345
    {                           /* Yes, we did. */
346
      dc[set].way[way].tagaddr = -1;
347
      dc[set].way[way].lru = 0;
348
    }
349
}
350
 
351
/*-----------------------------------------------------[ DC configuration ]---*/
352
 
353
/*---------------------------------------------------------------------------*/
354
/*!Enable or disable the data cache
355
 
356
   Set the corresponding field in the UPR
357
 
358
   @param[in] val  The value to use
359
   @param[in] dat  The config data structure (not used here)                 */
360
/*---------------------------------------------------------------------------*/
361
static void
362
dc_enabled (union param_val  val,
363
            void            *dat)
364
{
365
  if (val.int_val)
366
    {
367
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_DCP;
368
    }
369
  else
370
    {
371
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DCP;
372
    }
373
 
374
  config.dc.enabled = val.int_val;
375
 
376
    }   /* dc_enabled() */
377
 
378
 
379
/*---------------------------------------------------------------------------*/
380
/*!Set the number of data cache sets
381
 
382
   Value must be a power of 2 <= MAX_DC_SETS. If not issue a warning and
383
   ignore. Set the relevant field in the data cache config register
384
 
385
   @param[in] val  The value to use
386
   @param[in] dat  The config data structure (not used here)                 */
387
/*---------------------------------------------------------------------------*/
388
static void
389
dc_nsets (union param_val  val,
390
          void            *dat)
391
{
392
  if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_SETS))
393
    {
394
      int  set_bits = log2_int (val.int_val);
395
 
396
      config.dc.nsets = val.int_val;
397
 
398
      cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCS;
399
      cpu_state.sprs[SPR_DCCFGR] |= set_bits << SPR_DCCFGR_NCS_OFF;
400
    }
401
  else
402
    {
403
      fprintf (stderr, "Warning: data cache nsets not a power of 2 <= %d: "
404
               "ignored\n", MAX_DC_SETS);
405
    }
406
}       /* dc_nsets() */
407
 
408
 
409
/*---------------------------------------------------------------------------*/
410
/*!Set the number of data cache ways
411
 
412
   Value must be a power of 2 <= MAX_DC_WAYS. If not issue a warning and
413
   ignore. Set the relevant field in the data cache config register
414
 
415
   @param[in] val  The value to use
416
   @param[in] dat  The config data structure (not used here)                 */
417
/*---------------------------------------------------------------------------*/
418
static void
419
dc_nways (union param_val  val,
420
          void            *dat)
421
{
422
  if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_WAYS))
423
    {
424
      int  way_bits = log2_int (val.int_val);
425
 
426
      config.dc.nways = val.int_val;
427
 
428
      cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCW;
429
      cpu_state.sprs[SPR_DCCFGR] |= way_bits << SPR_DCCFGR_NCW_OFF;
430
    }
431
  else
432
    {
433
      fprintf (stderr, "Warning: data cache nways not a power of 2 <= %d: "
434
               "ignored\n", MAX_DC_WAYS);
435
    }
436
}        /* dc_nways() */
437
 
438
 
439
/*---------------------------------------------------------------------------*/
440
/*!Set the data cache block size
441
 
442
   Value must be either MIN_DC_BLOCK_SIZE or MAX_DC_BLOCK_SIZE. If not issue a
443
   warning and ignore. Set the relevant field in the data cache config register
444
 
445
   @param[in] val  The value to use
446
   @param[in] dat  The config data structure (not used here)                 */
447
/*---------------------------------------------------------------------------*/
448
static void
449
dc_blocksize (union param_val  val,
450
              void            *dat)
451
{
452
  switch (val.int_val)
453
    {
454
    case MIN_DC_BLOCK_SIZE:
455
      config.dc.blocksize         = val.int_val;
456
      cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_CBS;
457
      break;
458
 
459
    case MAX_DC_BLOCK_SIZE:
460
      config.dc.blocksize         = val.int_val;
461
      cpu_state.sprs[SPR_DCCFGR] |= SPR_DCCFGR_CBS;
462
      break;
463
 
464
    default:
465
      fprintf (stderr, "Warning: data cache block size not %d or %d: "
466
               "ignored\n", MIN_DC_BLOCK_SIZE, MAX_DC_BLOCK_SIZE);
467
      break;
468
    }
469
}       /* dc_blocksize() */
470
 
471
 
472
/*---------------------------------------------------------------------------*/
473
/*!Set the number of data cache usage states
474
 
475
   Value must be 2, 3 or 4. If not issue a warning and ignore.
476
 
477
   @param[in] val  The value to use
478
   @param[in] dat  The config data structure (not used here)                 */
479
/*---------------------------------------------------------------------------*/
480
static void
481
dc_ustates (union param_val  val,
482
            void            *dat)
483
{
484
  if ((val.int_val >= 2) && (val.int_val <= 4))
485
    {
486
      config.dc.ustates = val.int_val;
487
    }
488
  else
489
    {
490
      fprintf (stderr, "Warning number of data cache usage states must be "
491
               "2, 3 or 4: ignored\n");
492
    }
493
}       /* dc_ustates() */
494
 
495
 
496
static void
497
dc_load_hitdelay (union param_val val, void *dat)
498
{
499
  config.dc.load_hitdelay = val.int_val;
500
}
501
 
502
static void
503
dc_load_missdelay (union param_val val, void *dat)
504
{
505
  config.dc.load_missdelay = val.int_val;
506
}
507
 
508
static void
509
dc_store_hitdelay (union param_val val, void *dat)
510
{
511
  config.dc.store_hitdelay = val.int_val;
512
}
513
 
514
static void
515
dc_store_missdelay (union param_val val, void *dat)
516
{
517
  config.dc.store_missdelay = val.int_val;
518
}
519
 
520
void
521
reg_dc_sec (void)
522
{
523
  struct config_section *sec = reg_config_sec ("dc", NULL, NULL);
524
 
525
  reg_config_param (sec, "enabled", paramt_int, dc_enabled);
526
  reg_config_param (sec, "nsets", paramt_int, dc_nsets);
527
  reg_config_param (sec, "nways", paramt_int, dc_nways);
528
  reg_config_param (sec, "blocksize", paramt_int, dc_blocksize);
529
  reg_config_param (sec, "ustates", paramt_int, dc_ustates);
530
  reg_config_param (sec, "load_hitdelay", paramt_int, dc_load_hitdelay);
531
  reg_config_param (sec, "load_missdelay", paramt_int, dc_load_missdelay);
532
  reg_config_param (sec, "store_hitdelay", paramt_int, dc_store_hitdelay);
533
  reg_config_param (sec, "store_missdelay", paramt_int, dc_store_missdelay);
534
}

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