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[/] [openrisc/] [trunk/] [or1ksim/] [cache/] [dcache-model.c] - Blame information for rev 577

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Line No. Rev Author Line
1 19 jeremybenn
/* dcache-model.c -- data cache simulation
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
/* Cache functions.  At the moment these functions only simulate functionality
27
   of data caches and do not influence on fetche/decode/execute stages and
28
   timings.  They are here only to verify performance of various cache
29
   configurations. */
30
 
31
 
32
/* Autoconf and/or portability configuration */
33
#include "config.h"
34
 
35
/* Package includes */
36
#include "dcache-model.h"
37
#include "execute.h"
38
#include "spr-defs.h"
39
#include "abstract.h"
40
#include "stats.h"
41
#include "misc.h"
42 556 julius
#include "pcu.h"
43 19 jeremybenn
 
44
/* Data cache */
45
 
46
struct dc_set
47
{
48
  struct
49
  {
50
    uint32_t line[MAX_DC_BLOCK_SIZE/4];
51
    oraddr_t tagaddr;           /* tag address */
52
    int lru;                    /* least recently used */
53
  } way[MAX_DC_WAYS];
54
} dc[MAX_DC_SETS];
55
 
56
void
57
dc_info (void)
58
{
59
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
60
    {
61
      PRINTF ("DCache not implemented. Set UPR[DCP].\n");
62
      return;
63
    }
64
 
65
  PRINTF ("Data cache %dKB: ",
66
          config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
67
  PRINTF ("%d ways, %d sets, block size %d bytes\n", config.dc.nways,
68
          config.dc.nsets, config.dc.blocksize);
69
}
70
 
71
/* First check if data is already in the cache and if it is:
72
    - increment DC read hit stats,
73
    - set 'lru' at this way to config.dc.ustates - 1 and
74
      decrement 'lru' of other ways unless they have reached 0,
75
   and if not:
76
    - increment DC read miss stats
77
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
78
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
79
      ways unless they have reached 0
80
    - refill cache line
81
*/
82
 
83
uint32_t
84
dc_simulate_read (oraddr_t dataaddr, oraddr_t virt_addr, int width)
85
{
86
  int set, way = -1;
87
  int i;
88
  oraddr_t tagaddr;
89
  uint32_t tmp = 0;
90
 
91
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
92
      !(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci)
93
    {
94
      if (width == 4)
95
        tmp = evalsim_mem32 (dataaddr, virt_addr);
96
      else if (width == 2)
97
        tmp = evalsim_mem16 (dataaddr, virt_addr);
98
      else if (width == 1)
99
        tmp = evalsim_mem8 (dataaddr, virt_addr);
100
 
101
      if (cur_area && cur_area->log)
102
        fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
103
                 dataaddr, tmp);
104
 
105
      return tmp;
106
    }
107
 
108
  /* Which set to check out? */
109
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
110
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
111
 
112
  /* Scan all ways and try to find a matching way. */
113
  for (i = 0; i < config.dc.nways; i++)
114
    if (dc[set].way[i].tagaddr == tagaddr)
115
      way = i;
116
 
117
  /* Did we find our cached data? */
118
  if (way >= 0)
119
    {                           /* Yes, we did. */
120
      dc_stats.readhit++;
121
 
122
      for (i = 0; i < config.dc.nways; i++)
123
        if (dc[set].way[i].lru > dc[set].way[way].lru)
124
          dc[set].way[i].lru--;
125
      dc[set].way[way].lru = config.dc.ustates - 1;
126
      runtime.sim.mem_cycles += config.dc.load_hitdelay;
127
 
128
      tmp =
129
        dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
130
      if (width == 4)
131
        return tmp;
132
      else if (width == 2)
133
        {
134
          tmp = ((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
135
          return tmp;
136
        }
137
      else if (width == 1)
138
        {
139
          tmp = ((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff);
140
          return tmp;
141
        }
142
    }
143
  else
144
    {                           /* No, we didn't. */
145
      int minlru = config.dc.ustates - 1;
146
      int minway = 0;
147
 
148
      dc_stats.readmiss++;
149
 
150
      for (i = 0; i < config.dc.nways; i++)
151
        {
152
          if (dc[set].way[i].lru < minlru)
153
            {
154
              minway = i;
155
              minlru = dc[set].way[i].lru;
156
            }
157
        }
158
 
159
      for (i = 0; i < (config.dc.blocksize); i += 4)
160
        {
161
          /* FIXME: What is the virtual address meant to be? (ie. What happens if
162
           * we read out of memory while refilling a cache line?) */
163
          tmp =
164
            evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
165
                           (((dataaddr & ~ADDR_C (3)) +
166
                             i) & (config.dc.blocksize - 1)), 0);
167
 
168
          dc[set].way[minway].
169
            line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] = tmp;
170
          if (!cur_area)
171
            {
172
              dc[set].way[minway].tagaddr = -1;
173
              dc[set].way[minway].lru = 0;
174
              return 0;
175
            }
176
          else if (cur_area->log)
177
            fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
178
                     dataaddr, tmp);
179
        }
180
 
181
      dc[set].way[minway].tagaddr = tagaddr;
182
      for (i = 0; i < config.dc.nways; i++)
183
        if (dc[set].way[i].lru)
184
          dc[set].way[i].lru--;
185
      dc[set].way[minway].lru = config.dc.ustates - 1;
186
      runtime.sim.mem_cycles += config.dc.load_missdelay;
187
 
188 556 julius
      if (config.pcu.enabled)
189
        pcu_count_event(SPR_PCMR_DCM);
190
 
191
 
192 19 jeremybenn
      tmp =
193
        dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
194
      if (width == 4)
195
        return tmp;
196
      else if (width == 2)
197
        {
198
          tmp = (tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff;
199
          return tmp;
200
        }
201
      else if (width == 1)
202
        {
203
          tmp = (tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff;
204
          return tmp;
205
        }
206
    }
207
  return 0;
208
}
209
 
210
/* First check if data is already in the cache and if it is:
211
    - increment DC write hit stats,
212
    - set 'lru' at this way to config.dc.ustates - 1 and
213
      decrement 'lru' of other ways unless they have reached 0,
214
   and if not:
215
    - increment DC write miss stats
216
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
217
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
218
      ways unless they have reached 0
219
*/
220
 
221
void
222
dc_simulate_write (oraddr_t dataaddr, oraddr_t virt_addr, uint32_t data,
223
                   int width)
224
{
225
  int set, way = -1;
226
  int i;
227
  oraddr_t tagaddr;
228
  uint32_t tmp;
229
 
230
  if (width == 4)
231
    setsim_mem32 (dataaddr, virt_addr, data);
232
  else if (width == 2)
233
    setsim_mem16 (dataaddr, virt_addr, data);
234
  else if (width == 1)
235
    setsim_mem8 (dataaddr, virt_addr, data);
236
 
237
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
238
      !(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci || !cur_area)
239
    return;
240
 
241
  /* Which set to check out? */
242
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
243
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
244
 
245
  /* Scan all ways and try to find a matching way. */
246
  for (i = 0; i < config.dc.nways; i++)
247
    if (dc[set].way[i].tagaddr == tagaddr)
248
      way = i;
249
 
250
  /* Did we find our cached data? */
251
  if (way >= 0)
252
    {                           /* Yes, we did. */
253
      dc_stats.writehit++;
254
 
255
      for (i = 0; i < config.dc.nways; i++)
256
        if (dc[set].way[i].lru > dc[set].way[way].lru)
257
          dc[set].way[i].lru--;
258
      dc[set].way[way].lru = config.dc.ustates - 1;
259
      runtime.sim.mem_cycles += config.dc.store_hitdelay;
260
 
261
      tmp =
262
        dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
263
      if (width == 4)
264
        tmp = data;
265
      else if (width == 2)
266
        {
267
          tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
268
          tmp |= (data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
269
        }
270
      else if (width == 1)
271
        {
272
          tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
273
          tmp |= (data & 0xff) << (8 * (3 - (dataaddr & 3)));
274
        }
275
      dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] =
276
        tmp;
277
    }
278
  else
279
    {                           /* No, we didn't. */
280
      int minlru = config.dc.ustates - 1;
281
      int minway = 0;
282
 
283
      dc_stats.writemiss++;
284
 
285
      for (i = 0; i < config.dc.nways; i++)
286
        if (dc[set].way[i].lru < minlru)
287
          minway = i;
288
 
289
      for (i = 0; i < (config.dc.blocksize); i += 4)
290
        {
291
          dc[set].way[minway].
292
            line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
293
            /* FIXME: Same comment as in dc_simulate_read */
294
            evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
295
                           (((dataaddr & ~3ul) + i) & (config.dc.blocksize -
296
                                                       1)), 0);
297
          if (!cur_area)
298
            {
299
              dc[set].way[minway].tagaddr = -1;
300
              dc[set].way[minway].lru = 0;
301
              return;
302
            }
303
        }
304
 
305
      dc[set].way[minway].tagaddr = tagaddr;
306
      for (i = 0; i < config.dc.nways; i++)
307
        if (dc[set].way[i].lru)
308
          dc[set].way[i].lru--;
309
      dc[set].way[minway].lru = config.dc.ustates - 1;
310
      runtime.sim.mem_cycles += config.dc.store_missdelay;
311 556 julius
 
312
      if (config.pcu.enabled)
313
        pcu_count_event(SPR_PCMR_DCM);
314
 
315 19 jeremybenn
    }
316
}
317
 
318
/* First check if data is already in the cache and if it is:
319
    - invalidate block if way isn't locked
320
   otherwise don't do anything.
321
*/
322
 
323
void
324
dc_inv (oraddr_t dataaddr)
325
{
326
  int set, way = -1;
327
  int i;
328
  oraddr_t tagaddr;
329
 
330
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
331
    return;
332
 
333
  /* Which set to check out? */
334
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
335
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
336
 
337
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE))
338
    {
339
      for (i = 0; i < config.dc.nways; i++)
340
        {
341
          dc[set].way[i].tagaddr = -1;
342
          dc[set].way[i].lru = 0;
343
        }
344
      return;
345
    }
346
  /* Scan all ways and try to find a matching way. */
347
  for (i = 0; i < config.dc.nways; i++)
348
    if (dc[set].way[i].tagaddr == tagaddr)
349
      way = i;
350
 
351
  /* Did we find our cached data? */
352
  if (way >= 0)
353
    {                           /* Yes, we did. */
354
      dc[set].way[way].tagaddr = -1;
355
      dc[set].way[way].lru = 0;
356
    }
357
}
358
 
359
/*-----------------------------------------------------[ DC configuration ]---*/
360
 
361
/*---------------------------------------------------------------------------*/
362
/*!Enable or disable the data cache
363
 
364
   Set the corresponding field in the UPR
365
 
366
   @param[in] val  The value to use
367
   @param[in] dat  The config data structure (not used here)                 */
368
/*---------------------------------------------------------------------------*/
369
static void
370
dc_enabled (union param_val  val,
371
            void            *dat)
372
{
373
  if (val.int_val)
374
    {
375
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_DCP;
376
    }
377
  else
378
    {
379
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DCP;
380
    }
381
 
382
  config.dc.enabled = val.int_val;
383
 
384
    }   /* dc_enabled() */
385
 
386
 
387
/*---------------------------------------------------------------------------*/
388
/*!Set the number of data cache sets
389
 
390
   Value must be a power of 2 <= MAX_DC_SETS. If not issue a warning and
391
   ignore. Set the relevant field in the data cache config register
392
 
393
   @param[in] val  The value to use
394
   @param[in] dat  The config data structure (not used here)                 */
395
/*---------------------------------------------------------------------------*/
396
static void
397
dc_nsets (union param_val  val,
398
          void            *dat)
399
{
400
  if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_SETS))
401
    {
402
      int  set_bits = log2_int (val.int_val);
403
 
404
      config.dc.nsets = val.int_val;
405
 
406
      cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCS;
407
      cpu_state.sprs[SPR_DCCFGR] |= set_bits << SPR_DCCFGR_NCS_OFF;
408
    }
409
  else
410
    {
411
      fprintf (stderr, "Warning: data cache nsets not a power of 2 <= %d: "
412
               "ignored\n", MAX_DC_SETS);
413
    }
414
}       /* dc_nsets() */
415
 
416
 
417
/*---------------------------------------------------------------------------*/
418
/*!Set the number of data cache ways
419
 
420
   Value must be a power of 2 <= MAX_DC_WAYS. If not issue a warning and
421
   ignore. Set the relevant field in the data cache config register
422
 
423
   @param[in] val  The value to use
424
   @param[in] dat  The config data structure (not used here)                 */
425
/*---------------------------------------------------------------------------*/
426
static void
427
dc_nways (union param_val  val,
428
          void            *dat)
429
{
430
  if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_WAYS))
431
    {
432
      int  way_bits = log2_int (val.int_val);
433
 
434
      config.dc.nways = val.int_val;
435
 
436
      cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCW;
437
      cpu_state.sprs[SPR_DCCFGR] |= way_bits << SPR_DCCFGR_NCW_OFF;
438
    }
439
  else
440
    {
441
      fprintf (stderr, "Warning: data cache nways not a power of 2 <= %d: "
442
               "ignored\n", MAX_DC_WAYS);
443
    }
444
}        /* dc_nways() */
445
 
446
 
447
/*---------------------------------------------------------------------------*/
448
/*!Set the data cache block size
449
 
450
   Value must be either MIN_DC_BLOCK_SIZE or MAX_DC_BLOCK_SIZE. If not issue a
451
   warning and ignore. Set the relevant field in the data cache config register
452
 
453
   @param[in] val  The value to use
454
   @param[in] dat  The config data structure (not used here)                 */
455
/*---------------------------------------------------------------------------*/
456
static void
457
dc_blocksize (union param_val  val,
458
              void            *dat)
459
{
460
  switch (val.int_val)
461
    {
462
    case MIN_DC_BLOCK_SIZE:
463
      config.dc.blocksize         = val.int_val;
464
      cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_CBS;
465
      break;
466
 
467
    case MAX_DC_BLOCK_SIZE:
468
      config.dc.blocksize         = val.int_val;
469
      cpu_state.sprs[SPR_DCCFGR] |= SPR_DCCFGR_CBS;
470
      break;
471
 
472
    default:
473
      fprintf (stderr, "Warning: data cache block size not %d or %d: "
474
               "ignored\n", MIN_DC_BLOCK_SIZE, MAX_DC_BLOCK_SIZE);
475
      break;
476
    }
477
}       /* dc_blocksize() */
478
 
479
 
480
/*---------------------------------------------------------------------------*/
481
/*!Set the number of data cache usage states
482
 
483
   Value must be 2, 3 or 4. If not issue a warning and ignore.
484
 
485
   @param[in] val  The value to use
486
   @param[in] dat  The config data structure (not used here)                 */
487
/*---------------------------------------------------------------------------*/
488
static void
489
dc_ustates (union param_val  val,
490
            void            *dat)
491
{
492
  if ((val.int_val >= 2) && (val.int_val <= 4))
493
    {
494
      config.dc.ustates = val.int_val;
495
    }
496
  else
497
    {
498
      fprintf (stderr, "Warning number of data cache usage states must be "
499
               "2, 3 or 4: ignored\n");
500
    }
501
}       /* dc_ustates() */
502
 
503
 
504
static void
505
dc_load_hitdelay (union param_val val, void *dat)
506
{
507
  config.dc.load_hitdelay = val.int_val;
508
}
509
 
510
static void
511
dc_load_missdelay (union param_val val, void *dat)
512
{
513
  config.dc.load_missdelay = val.int_val;
514
}
515
 
516
static void
517
dc_store_hitdelay (union param_val val, void *dat)
518
{
519
  config.dc.store_hitdelay = val.int_val;
520
}
521
 
522
static void
523
dc_store_missdelay (union param_val val, void *dat)
524
{
525
  config.dc.store_missdelay = val.int_val;
526
}
527
 
528
void
529
reg_dc_sec (void)
530
{
531
  struct config_section *sec = reg_config_sec ("dc", NULL, NULL);
532
 
533 224 jeremybenn
  reg_config_param (sec, "enabled",         PARAMT_INT, dc_enabled);
534
  reg_config_param (sec, "nsets",           PARAMT_INT, dc_nsets);
535
  reg_config_param (sec, "nways",           PARAMT_INT, dc_nways);
536
  reg_config_param (sec, "blocksize",       PARAMT_INT, dc_blocksize);
537
  reg_config_param (sec, "ustates",         PARAMT_INT, dc_ustates);
538
  reg_config_param (sec, "load_hitdelay",   PARAMT_INT, dc_load_hitdelay);
539
  reg_config_param (sec, "load_missdelay",  PARAMT_INT, dc_load_missdelay);
540
  reg_config_param (sec, "store_hitdelay",  PARAMT_INT, dc_store_hitdelay);
541
  reg_config_param (sec, "store_missdelay", PARAMT_INT, dc_store_missdelay);
542 19 jeremybenn
}

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