OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cache/] [icache-model.h] - Blame information for rev 857

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jeremybenn
/* icache-model.h -- instruction cache header file
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
 
27
#ifndef ICACHE_MODEL__H
28
#define ICACHE_MODEL__H
29
 
30
/* Autoconf and/or portability configuration */
31
#include "port.h"
32
 
33
/* Package includes */
34
#include "sim-config.h"
35
 
36
 
37
struct ic
38
{
39
  uint8_t      *mem;
40
  unsigned int *lrus;
41
  oraddr_t     *tags;
42
 
43
  int           enabled;            /* Whether instruction cache is enabled */
44
  unsigned int  nways;              /* Number of IC ways */
45
  unsigned int  nsets;              /* Number of IC sets */
46
  unsigned int  blocksize;          /* IC entry size */
47
  unsigned int  ustates;            /* number of IC usage states */
48
  int           missdelay;          /* How much cycles does the miss cost */
49
  int           hitdelay;           /* How much cycles does the hit cost */
50
  unsigned int  blocksize_log2;     /* log2(blocksize) */
51
  oraddr_t      set_mask;           /* Mask to get set number */
52
  oraddr_t      tagaddr_mask;       /* Mask to get tag address */
53
  oraddr_t      last_way;           /* nways * nsets */
54
  oraddr_t      block_offset_mask;  /* mask to get offset into block */
55
  oraddr_t      block_mask;         /* mask to get block number */
56
  unsigned int  ustates_reload;     /* ustates - 1 */
57
};
58
 
59
/* External variables */
60
extern struct ic *ic_state;
61
 
62
/* Prototypes for external use */
63
extern uint32_t  ic_simulate_fetch (oraddr_t fetchaddr,
64
                                    oraddr_t virt_addr);
65
extern void      ic_inv (oraddr_t dataaddr);
66
extern void      reg_ic_sec ();
67
 
68
#endif  /* ICACHE_MODEL__H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.