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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 584

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1 19 jeremybenn
/* abstract.c -- Abstract entities
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
5
   Copyright (C) 2008 Embecosm Limited
6
 
7
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
23
 
24
/* This program is commented throughout in a fashion suitable for processing
25
   with Doxygen. */
26
 
27
/* Abstract memory and routines that go with this. I need to add all sorts of
28
   other abstract entities. Currently we have only memory. */
29
 
30
 
31
/* Autoconf and/or portability configuration */
32
#include "config.h"
33
#include "port.h"
34
 
35
/* System includes */
36
#include <stdlib.h>
37
 
38
/* Package includes */
39
#include "abstract.h"
40
#include "except.h"
41
#include "support/profile.h"
42
#include "debug-unit.h"
43
#include "icache-model.h"
44
#include "dcache-model.h"
45
#include "labels.h"
46
#include "opcode/or32.h"
47
#include "dmmu.h"
48
#include "immu.h"
49 420 jeremybenn
#include "execute.h"
50 556 julius
#include "pcu.h"
51 19 jeremybenn
 
52
/*! Global temporary variable to increase speed.  */
53
struct dev_memarea *cur_area;
54
 
55
/* Glboal variables set by MMU if cache inhibit bit is set for current
56
   access.  */
57
int  data_ci;                   /*!< Global var: data cache inhibit bit set */
58
int  insn_ci;                   /*!< Global var: instr cache inhibit bit set */
59
 
60
/* Pointer to memory area descriptions that are assigned to individual
61
   peripheral devices. */
62
static struct dev_memarea *dev_list;
63
 
64
/* Pointer to memory controller device descriptor.  */
65
static struct dev_memarea *mc_area = NULL;
66
 
67
/* Virtual address of current access. */
68
static oraddr_t cur_vadd;
69
 
70
/* Forward declarations */
71
static uint32_t eval_mem_32_inv (oraddr_t, void *);
72
static uint16_t eval_mem_16_inv (oraddr_t, void *);
73
static uint8_t  eval_mem_8_inv (oraddr_t, void *);
74
static uint32_t eval_mem_32_inv_direct (oraddr_t, void *);
75
static uint16_t eval_mem_16_inv_direct (oraddr_t, void *);
76
static uint8_t  eval_mem_8_inv_direct (oraddr_t, void *);
77
static void     set_mem_32_inv (oraddr_t, uint32_t, void *);
78
static void     set_mem_16_inv (oraddr_t, uint16_t, void *);
79
static void     set_mem_8_inv (oraddr_t, uint8_t, void *);
80
static void     set_mem_32_inv_direct (oraddr_t, uint32_t, void *);
81
static void     set_mem_16_inv_direct (oraddr_t, uint16_t, void *);
82
static void     set_mem_8_inv_direct (oraddr_t, uint8_t, void *);
83
 
84
/* Calculates bit mask to fit the data */
85
static unsigned int
86
bit_mask (uint32_t data)
87
{
88
  int i = 0;
89
  data--;
90
  while (data >> i)
91
    data |= 1 << i++;
92
  return data;
93
}
94
 
95
/* Register read and write function for a memory area.
96
   addr is inside the area, if addr & addr_mask == addr_compare
97
   (used also by peripheral devices like 16450 UART etc.) */
98
static struct dev_memarea *
99
register_memoryarea_mask (oraddr_t addr_mask,
100
                          oraddr_t addr_compare,
101
                          uint32_t size, unsigned mc_dev)
102
{
103
  struct dev_memarea **pptmp;
104
  unsigned int size_mask = bit_mask (size);
105
  int found_error = 0;
106
  addr_compare &= addr_mask;
107
 
108
  /* Go to the end of the list. */
109
  for (pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
110
    if (((addr_compare >= (*pptmp)->addr_compare) &&
111
         (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) ||
112
        ((addr_compare + size > (*pptmp)->addr_compare) &&
113
         (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)))
114
      {
115
        if (!found_error)
116
          {
117
            fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
118
            fprintf (stderr,
119
                     "\taddr & %" PRIxADDR " == %" PRIxADDR " to %" PRIxADDR
120
                     ", size %08" PRIx32 "\n", addr_mask, addr_compare,
121
                     addr_compare | bit_mask (size), size);
122
          }
123
        found_error = 1;
124
        fprintf (stderr,
125
                 "and\taddr & %" PRIxADDR " == %" PRIxADDR " to %" PRIxADDR
126
                 ", size %08" PRIx32 "\n", (*pptmp)->addr_mask,
127
                 (*pptmp)->addr_compare,
128
                 (*pptmp)->addr_compare | (*pptmp)->size_mask,
129
                 (*pptmp)->size);
130
      }
131
 
132
  if (found_error)
133
    exit (-1);
134
 
135
  cur_area = *pptmp =
136
    (struct dev_memarea *) malloc (sizeof (struct dev_memarea));
137
 
138
  if (mc_dev)
139
    mc_area = *pptmp;
140
 
141
  (*pptmp)->addr_mask = addr_mask;
142
  (*pptmp)->addr_compare = addr_compare;
143
  (*pptmp)->size = size;
144
  (*pptmp)->size_mask = size_mask;
145
  (*pptmp)->log = NULL;
146
  (*pptmp)->valid = 1;
147
  (*pptmp)->next = NULL;
148
 
149
  return *pptmp;
150
}
151
 
152
/* Register read and write function for a memory area.
153
   Memory areas should be aligned. Memory area is rounded up to
154
   fit the nearest 2^n aligment.
155
   (used also by peripheral devices like 16450 UART etc.)
156
   If mc_dev is 1, this device will be checked first for a match
157
   and will be accessed in case of overlaping memory areas.
158
   Only one device can have this set to 1 (used for memory controller) */
159
struct dev_memarea *
160
reg_mem_area (oraddr_t addr, uint32_t size, unsigned mc_dev,
161
              struct mem_ops *ops)
162
{
163
  unsigned int size_mask = bit_mask (size);
164
  unsigned int addr_mask = ~size_mask;
165
  struct dev_memarea *mem;
166
 
167
  mem = register_memoryarea_mask (addr_mask, addr & addr_mask, size_mask + 1,
168
                                  mc_dev);
169
 
170
  memcpy (&mem->ops, ops, sizeof (struct mem_ops));
171
  memcpy (&mem->direct_ops, ops, sizeof (struct mem_ops));
172
 
173
  if (!ops->readfunc32)
174
    {
175
      mem->ops.readfunc32 = eval_mem_32_inv;
176
      mem->direct_ops.readfunc32 = eval_mem_32_inv_direct;
177
      mem->direct_ops.read_dat32 = mem;
178
    }
179
  if (!ops->readfunc16)
180
    {
181
      mem->ops.readfunc16 = eval_mem_16_inv;
182
      mem->direct_ops.readfunc16 = eval_mem_16_inv_direct;
183
      mem->direct_ops.read_dat16 = mem;
184
    }
185
  if (!ops->readfunc8)
186
    {
187
      mem->ops.readfunc8 = eval_mem_8_inv;
188
      mem->direct_ops.readfunc8 = eval_mem_8_inv_direct;
189
      mem->direct_ops.read_dat8 = mem;
190
    }
191
 
192
  if (!ops->writefunc32)
193
    {
194
      mem->ops.writefunc32 = set_mem_32_inv;
195
      mem->direct_ops.writefunc32 = set_mem_32_inv_direct;
196
      mem->direct_ops.write_dat32 = mem;
197
    }
198
  if (!ops->writefunc16)
199
    {
200
      mem->ops.writefunc16 = set_mem_16_inv;
201
      mem->direct_ops.writefunc16 = set_mem_16_inv_direct;
202
      mem->direct_ops.write_dat16 = mem;
203
    }
204
  if (!ops->writefunc8)
205
    {
206
      mem->ops.writefunc8 = set_mem_8_inv;
207
      mem->direct_ops.writefunc8 = set_mem_8_inv_direct;
208
      mem->direct_ops.write_dat8 = mem;
209
    }
210
 
211
  if (!ops->writeprog8)
212
    {
213
      mem->ops.writeprog8 = mem->ops.writefunc8;
214
      mem->ops.writeprog8_dat = mem->ops.write_dat8;
215
    }
216
 
217
  if (!ops->writeprog32)
218
    {
219
      mem->ops.writeprog32 = mem->ops.writefunc32;
220
      mem->ops.writeprog32_dat = mem->ops.write_dat32;
221
    }
222
 
223
  if (ops->log)
224
    {
225
      if (!(mem->log = fopen (ops->log, "w")))
226
        PRINTF ("ERR: Unable to open %s to log memory acesses to\n",
227
                ops->log);
228
    }
229
 
230
  return mem;
231
}
232
 
233
/* Check if access is to registered area of memory. */
234
struct dev_memarea *
235
verify_memoryarea (oraddr_t addr)
236
{
237
  struct dev_memarea *ptmp;
238
 
239
  /* Check memory controller space first */
240
  if (mc_area
241
      && (addr & mc_area->addr_mask) ==
242
      (mc_area->addr_compare & mc_area->addr_mask))
243 98 jeremybenn
    {
244
      return cur_area = mc_area;
245
    }
246 19 jeremybenn
 
247
  /* Check cached value */
248
  if (cur_area
249
      && (addr & cur_area->addr_mask) ==
250
      (cur_area->addr_compare & cur_area->addr_mask))
251 98 jeremybenn
    {
252
      return cur_area;
253
    }
254 19 jeremybenn
 
255
  /* When mc is enabled, we must check valid also, otherwise we assume it is
256
     nonzero */
257
  /* Check list of registered devices. */
258
  for (ptmp = dev_list; ptmp; ptmp = ptmp->next)
259 98 jeremybenn
    {
260
      if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask)
261
          && ptmp->valid)
262
        {
263
          return cur_area = ptmp;
264
        }
265
    }
266
 
267 19 jeremybenn
  return cur_area = NULL;
268
}
269
 
270
/* Sets the valid bit (Used only by memory controllers) */
271
void
272
set_mem_valid (struct dev_memarea *mem, int valid)
273
{
274
  mem->valid = valid;
275
}
276
 
277
/* Adjusts the read and write delays for the memory area pointed to by mem. */
278
void
279
adjust_rw_delay (struct dev_memarea *mem, int delayr, int delayw)
280
{
281
  mem->ops.delayr = delayr;
282
  mem->ops.delayw = delayw;
283
}
284
 
285
static uint8_t
286
eval_mem_8_inv (oraddr_t memaddr, void *dat)
287
{
288
  except_handle (EXCEPT_BUSERR, cur_vadd);
289
  return 0;
290
}
291
 
292
static uint16_t
293
eval_mem_16_inv (oraddr_t memaddr, void *dat)
294
{
295
  except_handle (EXCEPT_BUSERR, cur_vadd);
296
  return 0;
297
}
298
 
299
static uint32_t
300
eval_mem_32_inv (oraddr_t memaddr, void *dat)
301
{
302
  except_handle (EXCEPT_BUSERR, cur_vadd);
303
  return 0;
304
}
305
 
306
static void
307
set_mem_8_inv (oraddr_t memaddr, uint8_t val, void *dat)
308
{
309
  except_handle (EXCEPT_BUSERR, cur_vadd);
310
}
311
 
312
static void
313
set_mem_16_inv (oraddr_t memaddr, uint16_t val, void *dat)
314
{
315
  except_handle (EXCEPT_BUSERR, cur_vadd);
316
}
317
 
318
static void
319
set_mem_32_inv (oraddr_t memaddr, uint32_t val, void *dat)
320
{
321
  except_handle (EXCEPT_BUSERR, cur_vadd);
322
}
323
 
324
uint8_t
325
eval_mem_8_inv_direct (oraddr_t memaddr, void *dat)
326
{
327
  struct dev_memarea *mem = dat;
328
 
329
  PRINTF ("ERROR: Invalid 8-bit direct read from memory %" PRIxADDR "\n",
330
          mem->addr_compare | memaddr);
331
  return 0;
332
}
333
 
334
uint16_t
335
eval_mem_16_inv_direct (oraddr_t memaddr, void *dat)
336
{
337
  struct dev_memarea *mem = dat;
338
 
339
  PRINTF ("ERROR: Invalid 16-bit direct read from memory %" PRIxADDR "\n",
340
          mem->addr_compare | memaddr);
341
  return 0;
342
}
343
 
344
uint32_t
345
eval_mem_32_inv_direct (oraddr_t memaddr, void *dat)
346
{
347
  struct dev_memarea *mem = dat;
348
 
349
  PRINTF ("ERROR: Invalid 32-bit direct read from memory %" PRIxADDR "\n",
350
          mem->addr_compare | memaddr);
351
  return 0;
352
}
353
 
354
void
355
set_mem_8_inv_direct (oraddr_t memaddr, uint8_t val, void *dat)
356
{
357
  struct dev_memarea *mem = dat;
358
 
359
  PRINTF ("ERROR: Invalid 32-bit direct write to memory %" PRIxADDR "\n",
360
          mem->addr_compare | memaddr);
361
}
362
 
363
void
364
set_mem_16_inv_direct (oraddr_t memaddr, uint16_t val, void *dat)
365
{
366
  struct dev_memarea *mem = dat;
367
 
368
  PRINTF ("ERROR: Invalid 16-bit direct write to memory %" PRIxADDR "\n",
369
          mem->addr_compare | memaddr);
370
}
371
 
372
void
373
set_mem_32_inv_direct (oraddr_t memaddr, uint32_t val, void *dat)
374
{
375
  struct dev_memarea *mem = dat;
376
 
377
  PRINTF ("ERROR: Invalid 32-bit direct write to memory %" PRIxADDR "\n",
378
          mem->addr_compare | memaddr);
379
}
380
 
381
/* For cpu accesses
382
 *
383
 * NOTE: This function _is_ only called from eval_mem32 below and
384
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
385
 */
386
uint32_t
387
evalsim_mem32 (oraddr_t memaddr, oraddr_t vaddr)
388
{
389
  struct dev_memarea *mem;
390
 
391
  if ((mem = verify_memoryarea (memaddr)))
392
    {
393
      runtime.sim.mem_cycles += mem->ops.delayr;
394
      return mem->ops.readfunc32 (memaddr & mem->size_mask,
395
                                  mem->ops.read_dat32);
396
    }
397
  else
398
    {
399 220 jeremybenn
      if (config.sim.report_mem_errs)
400
        {
401
          PRINTF ("EXCEPTION: read out of memory (32-bit access to %" PRIxADDR
402
                  ")\n", memaddr);
403
        }
404
 
405 19 jeremybenn
      except_handle (EXCEPT_BUSERR, vaddr);
406
    }
407
 
408
  return 0;
409
}
410
 
411
/* For cpu accesses
412
 *
413
 * NOTE: This function _is_ only called from eval_mem16 below and
414
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
415
 */
416
uint16_t
417
evalsim_mem16 (oraddr_t memaddr, oraddr_t vaddr)
418
{
419
  struct dev_memarea *mem;
420
 
421
  if ((mem = verify_memoryarea (memaddr)))
422
    {
423
      runtime.sim.mem_cycles += mem->ops.delayr;
424
      return mem->ops.readfunc16 (memaddr & mem->size_mask,
425
                                  mem->ops.read_dat16);
426
    }
427
  else
428
    {
429 220 jeremybenn
      if (config.sim.report_mem_errs)
430
        {
431
          PRINTF ("EXCEPTION: read out of memory (16-bit access to %" PRIxADDR
432
                  ")\n", memaddr);
433
        }
434
 
435 19 jeremybenn
      except_handle (EXCEPT_BUSERR, vaddr);
436
    }
437
 
438
  return 0;
439
}
440
 
441
/* For cpu accesses
442
 *
443
 * NOTE: This function _is_ only called from eval_mem8 below and
444
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
445
 */
446
uint8_t
447
evalsim_mem8 (oraddr_t memaddr, oraddr_t vaddr)
448
{
449
  struct dev_memarea *mem;
450
 
451
  if ((mem = verify_memoryarea (memaddr)))
452
    {
453
      runtime.sim.mem_cycles += mem->ops.delayr;
454
      return mem->ops.readfunc8 (memaddr & mem->size_mask,
455
                                 mem->ops.read_dat8);
456
    }
457
  else
458
    {
459 220 jeremybenn
      if (config.sim.report_mem_errs)
460
        {
461
          PRINTF ("EXCEPTION: read out of memory (8-bit access to %" PRIxADDR
462
                  ")\n", memaddr);
463
        }
464
 
465 19 jeremybenn
      except_handle (EXCEPT_BUSERR, vaddr);
466
    }
467
 
468
  return 0;
469
}
470
 
471
/* Returns 32-bit values from mem array. Big endian version.
472
 *
473
 * STATISTICS OK (only used for cpu_access, that is architectural access)
474
 */
475
uint32_t
476
eval_mem32 (oraddr_t memaddr, int *breakpoint)
477
{
478
  uint32_t temp;
479
  oraddr_t phys_memaddr;
480
 
481
  if (config.sim.mprofile)
482
    mprofile (memaddr, MPROF_32 | MPROF_READ);
483
 
484
  if (memaddr & 3)
485
    {
486
      except_handle (EXCEPT_ALIGN, memaddr);
487
      return 0;
488
    }
489
 
490
  phys_memaddr = dmmu_translate (memaddr, 0);
491
  if (except_pending)
492
    return 0;
493
 
494 556 julius
  if (config.pcu.enabled)
495
    pcu_count_event(SPR_PCMR_LA);
496
 
497
  if (config.debug.enabled)
498
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);
499
 
500 19 jeremybenn
  if (config.dc.enabled)
501
    temp = dc_simulate_read (phys_memaddr, memaddr, 4);
502
  else
503
    temp = evalsim_mem32 (phys_memaddr, memaddr);
504
 
505
  if (config.debug.enabled)
506 556 julius
    *breakpoint += check_debug_unit (DebugLoadData, temp);
507 19 jeremybenn
 
508
  return temp;
509
}
510
 
511
/* for simulator accesses, the ones that cpu wouldn't do
512
 *
513
 * STATISTICS OK
514
 */
515
uint32_t
516
eval_direct32 (oraddr_t memaddr, int through_mmu, int through_dc)
517
{
518
  oraddr_t phys_memaddr;
519
  struct dev_memarea *mem;
520
 
521
  if (memaddr & 3)
522
    {
523
      PRINTF ("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__,
524
              __FUNCTION__);
525
      return 0;
526
    }
527
 
528
  phys_memaddr = memaddr;
529
 
530
  if (through_mmu)
531
    phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
532
 
533
  if (through_dc)
534
    return dc_simulate_read (phys_memaddr, memaddr, 4);
535
  else
536
    {
537
      if ((mem = verify_memoryarea (phys_memaddr)))
538
        return mem->direct_ops.readfunc32 (phys_memaddr & mem->size_mask,
539
                                           mem->direct_ops.read_dat32);
540
      else
541 220 jeremybenn
        fprintf (stderr, "ERR: 32-bit read out of memory area: %" PRIxADDR
542
                 " (physical: %" PRIxADDR ")\n", memaddr, phys_memaddr);
543 19 jeremybenn
    }
544
 
545
  return 0;
546
}
547
 
548
 
549
/* Returns 32-bit values from mem array. Big endian version.
550
 *
551
 * STATISTICS OK (only used for cpu_access, that is architectural access)
552
 */
553
uint32_t
554
eval_insn (oraddr_t memaddr, int *breakpoint)
555
{
556
  uint32_t temp;
557
  oraddr_t phys_memaddr;
558
 
559
  if (config.sim.mprofile)
560
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
561
 
562
  phys_memaddr = memaddr;
563
  phys_memaddr = immu_translate (memaddr);
564
 
565
  if (except_pending)
566
    return 0;
567
 
568
  if (config.debug.enabled)
569
    *breakpoint += check_debug_unit (DebugInstructionFetch, memaddr);
570
 
571 556 julius
  if (config.pcu.enabled)
572
    pcu_count_event(SPR_PCMR_IF);
573
 
574 19 jeremybenn
  if ((NULL != ic_state) && ic_state->enabled)
575
    temp = ic_simulate_fetch (phys_memaddr, memaddr);
576
  else
577
    temp = evalsim_mem32 (phys_memaddr, memaddr);
578
 
579
  if (config.debug.enabled)
580
    *breakpoint += check_debug_unit (DebugLoadData, temp);
581
  return temp;
582
}
583
 
584
/* Returns 16-bit values from mem array. Big endian version.
585
 *
586
 * STATISTICS OK (only used for cpu_access, that is architectural access)
587
 */
588
uint16_t
589
eval_mem16 (oraddr_t memaddr, int *breakpoint)
590
{
591
  uint16_t temp;
592
  oraddr_t phys_memaddr;
593
 
594
  if (config.sim.mprofile)
595
    mprofile (memaddr, MPROF_16 | MPROF_READ);
596
 
597
  if (memaddr & 1)
598
    {
599
      except_handle (EXCEPT_ALIGN, memaddr);
600
      return 0;
601
    }
602
 
603
  phys_memaddr = dmmu_translate (memaddr, 0);
604
  if (except_pending)
605
    return 0;
606
 
607 556 julius
  if (config.pcu.enabled)
608
    pcu_count_event(SPR_PCMR_LA);
609
 
610
  if (config.debug.enabled)
611
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);
612
 
613 19 jeremybenn
  if (config.dc.enabled)
614
    temp = dc_simulate_read (phys_memaddr, memaddr, 2);
615
  else
616
    temp = evalsim_mem16 (phys_memaddr, memaddr);
617
 
618
  if (config.debug.enabled)
619 556 julius
    *breakpoint += check_debug_unit (DebugLoadData, temp);
620 19 jeremybenn
 
621
  return temp;
622
}
623
 
624
/* for simulator accesses, the ones that cpu wouldn't do
625
 *
626
 * STATISTICS OK.
627
 */
628
uint16_t
629
eval_direct16 (oraddr_t memaddr, int through_mmu, int through_dc)
630
{
631
  oraddr_t phys_memaddr;
632
  struct dev_memarea *mem;
633
 
634
  if (memaddr & 1)
635
    {
636
      PRINTF ("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__,
637
              __FUNCTION__);
638
      return 0;
639
    }
640
 
641
  phys_memaddr = memaddr;
642
 
643
  if (through_mmu)
644
    phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
645
 
646
  if (through_dc)
647
    return dc_simulate_read (phys_memaddr, memaddr, 2);
648
  else
649
    {
650
      if ((mem = verify_memoryarea (phys_memaddr)))
651
        return mem->direct_ops.readfunc16 (phys_memaddr & mem->size_mask,
652
                                           mem->direct_ops.read_dat16);
653
      else
654 220 jeremybenn
        fprintf (stderr, "ERR: 16-bit read out of memory area: %" PRIxADDR
655
                 " (physical: %" PRIxADDR "\n", memaddr, phys_memaddr);
656 19 jeremybenn
    }
657
 
658
  return 0;
659
}
660
 
661
/* Returns 8-bit values from mem array.
662
 *
663
 * STATISTICS OK (only used for cpu_access, that is architectural access)
664
 */
665
uint8_t
666
eval_mem8 (oraddr_t memaddr, int *breakpoint)
667
{
668
  uint8_t temp;
669
  oraddr_t phys_memaddr;
670
 
671
  if (config.sim.mprofile)
672
    mprofile (memaddr, MPROF_8 | MPROF_READ);
673
 
674
  phys_memaddr = dmmu_translate (memaddr, 0);
675
  if (except_pending)
676
    return 0;
677
 
678 556 julius
  if (config.pcu.enabled)
679
    pcu_count_event(SPR_PCMR_LA);
680
 
681
  if (config.debug.enabled)
682
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);
683
 
684 19 jeremybenn
  if (config.dc.enabled)
685
    temp = dc_simulate_read (phys_memaddr, memaddr, 1);
686
  else
687
    temp = evalsim_mem8 (phys_memaddr, memaddr);
688
 
689
  if (config.debug.enabled)
690 556 julius
    *breakpoint += check_debug_unit (DebugLoadData, temp);
691 19 jeremybenn
  return temp;
692
}
693
 
694
/* for simulator accesses, the ones that cpu wouldn't do
695
 *
696
 * STATISTICS OK.
697
 */
698
uint8_t
699
eval_direct8 (oraddr_t memaddr, int through_mmu, int through_dc)
700
{
701
  oraddr_t phys_memaddr;
702
  struct dev_memarea *mem;
703
 
704
  phys_memaddr = memaddr;
705
 
706
  if (through_mmu)
707
    phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
708
 
709
  if (through_dc)
710
    return dc_simulate_read (phys_memaddr, memaddr, 1);
711
  else
712
    {
713
      if ((mem = verify_memoryarea (phys_memaddr)))
714
        return mem->direct_ops.readfunc8 (phys_memaddr & mem->size_mask,
715
                                          mem->direct_ops.read_dat8);
716
      else
717 220 jeremybenn
        fprintf (stderr, "ERR: 8-bit read out of memory area: %" PRIxADDR
718
                 " (physical: %" PRIxADDR "\n", memaddr, phys_memaddr);
719 19 jeremybenn
    }
720
 
721
  return 0;
722
}
723
 
724
/* For cpu accesses
725
 *
726
 * NOTE: This function _is_ only called from set_mem32 below and
727
 * dc_simulate_write.  _Don't_ call it from anywere else.
728
 */
729
void
730
setsim_mem32 (oraddr_t memaddr, oraddr_t vaddr, uint32_t value)
731
{
732
  struct dev_memarea *mem;
733
 
734
  if ((mem = verify_memoryarea (memaddr)))
735
    {
736
      cur_vadd = vaddr;
737
      runtime.sim.mem_cycles += mem->ops.delayw;
738
      mem->ops.writefunc32 (memaddr & mem->size_mask, value,
739
                            mem->ops.write_dat32);
740
    }
741
  else
742
    {
743 220 jeremybenn
      if (config.sim.report_mem_errs)
744
        {
745
          PRINTF ("EXCEPTION: write out of memory (32-bit access to %" PRIxADDR
746
                  ")\n", memaddr);
747
        }
748
 
749 19 jeremybenn
      except_handle (EXCEPT_BUSERR, vaddr);
750
    }
751
}
752
 
753
/* For cpu accesses
754
 *
755
 * NOTE: This function _is_ only called from set_mem16 below and
756
 * dc_simulate_write.  _Don't_ call it from anywere else.
757
 */
758
void
759
setsim_mem16 (oraddr_t memaddr, oraddr_t vaddr, uint16_t value)
760
{
761
  struct dev_memarea *mem;
762
 
763
  if ((mem = verify_memoryarea (memaddr)))
764
    {
765
      cur_vadd = vaddr;
766
      runtime.sim.mem_cycles += mem->ops.delayw;
767
      mem->ops.writefunc16 (memaddr & mem->size_mask, value,
768
                            mem->ops.write_dat16);
769
    }
770
  else
771
    {
772 220 jeremybenn
      if (config.sim.report_mem_errs)
773
        {
774
          PRINTF ("EXCEPTION: write out of memory (16-bit access to %" PRIxADDR
775
                  ")\n", memaddr);
776
        }
777
 
778 19 jeremybenn
      except_handle (EXCEPT_BUSERR, vaddr);
779
    }
780
}
781
 
782
/* For cpu accesses
783
 *
784
 * NOTE: This function _is_ only called from set_mem8 below and
785
 * dc_simulate_write.  _Don't_ call it from anywere else.
786
 */
787
void
788
setsim_mem8 (oraddr_t memaddr, oraddr_t vaddr, uint8_t value)
789
{
790
  struct dev_memarea *mem;
791
 
792
  if ((mem = verify_memoryarea (memaddr)))
793
    {
794
      cur_vadd = vaddr;
795
      runtime.sim.mem_cycles += mem->ops.delayw;
796
      mem->ops.writefunc8 (memaddr & mem->size_mask, value,
797
                           mem->ops.write_dat8);
798
    }
799
  else
800
    {
801 220 jeremybenn
      if (config.sim.report_mem_errs)
802
        {
803
          PRINTF ("EXCEPTION: write out of memory (8-bit access to %" PRIxADDR
804
                  ")\n", memaddr);
805
        }
806
 
807 19 jeremybenn
      except_handle (EXCEPT_BUSERR, vaddr);
808
    }
809
}
810
 
811
/* Set mem, 32-bit. Big endian version.
812
 *
813
 * STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
814
 *                 where this instruction is used for patching memory,
815
 *                 wether this is cpu or architectual access is yet to
816
 *                 be decided)
817
 */
818
void
819
set_mem32 (oraddr_t memaddr, uint32_t value, int *breakpoint)
820
{
821
  oraddr_t phys_memaddr;
822
 
823
  if (config.sim.mprofile)
824
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
825
 
826
  if (memaddr & 3)
827
    {
828
      except_handle (EXCEPT_ALIGN, memaddr);
829
      return;
830
    }
831
 
832
  phys_memaddr = dmmu_translate (memaddr, 1);;
833
  /* If we produced exception don't set anything */
834
  if (except_pending)
835
    return;
836
 
837 556 julius
  if (config.pcu.enabled)
838
    pcu_count_event(SPR_PCMR_SA);
839
 
840 19 jeremybenn
  if (config.debug.enabled)
841
    {
842
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
843
      *breakpoint += check_debug_unit (DebugStoreData, value);
844
    }
845
 
846
  if (config.dc.enabled)
847
    dc_simulate_write (phys_memaddr, memaddr, value, 4);
848
  else
849
    setsim_mem32 (phys_memaddr, memaddr, value);
850
 
851
  if (cur_area && cur_area->log)
852
    fprintf (cur_area->log, "[%" PRIxADDR "] -> write %08" PRIx32 "\n",
853
             memaddr, value);
854
}
855
 
856
/*
857
 * STATISTICS NOT OK.
858
 */
859
void
860
set_direct32 (oraddr_t memaddr, uint32_t value, int through_mmu,
861
              int through_dc)
862
{
863
  oraddr_t phys_memaddr;
864
  struct dev_memarea *mem;
865
 
866
  if (memaddr & 3)
867
    {
868
      PRINTF ("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__,
869
              __FUNCTION__);
870
      return;
871
    }
872
 
873
  phys_memaddr = memaddr;
874
 
875
  if (through_mmu)
876
    {
877
      /* 0 - no write access, we do not want a DPF exception do we ;)
878
       */
879
      phys_memaddr = peek_into_dtlb (memaddr, 1, through_dc);
880
    }
881
 
882
  if (through_dc)
883
    dc_simulate_write (memaddr, memaddr, value, 4);
884
  else
885
    {
886
      if ((mem = verify_memoryarea (phys_memaddr)))
887
        mem->direct_ops.writefunc32 (phys_memaddr & mem->size_mask, value,
888
                                     mem->direct_ops.write_dat32);
889
      else
890 220 jeremybenn
        fprintf (stderr, "ERR: 32-bit write out of memory area: %" PRIxADDR
891 19 jeremybenn
                " (physical: %" PRIxADDR ")\n", memaddr, phys_memaddr);
892
    }
893
 
894
  if (cur_area && cur_area->log)
895
    fprintf (cur_area->log, "[%" PRIxADDR "] -> DIRECT write %08" PRIx32 "\n",
896
             memaddr, value);
897
}
898
 
899
 
900
/* Set mem, 16-bit. Big endian version. */
901
 
902
void
903
set_mem16 (oraddr_t memaddr, uint16_t value, int *breakpoint)
904
{
905
  oraddr_t phys_memaddr;
906
 
907
  if (config.sim.mprofile)
908
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
909
 
910
  if (memaddr & 1)
911
    {
912
      except_handle (EXCEPT_ALIGN, memaddr);
913
      return;
914
    }
915
 
916
  phys_memaddr = dmmu_translate (memaddr, 1);;
917
  /* If we produced exception don't set anything */
918
  if (except_pending)
919
    return;
920
 
921 556 julius
  if (config.pcu.enabled)
922
    pcu_count_event(SPR_PCMR_SA);
923
 
924 19 jeremybenn
  if (config.debug.enabled)
925
    {
926
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
927
      *breakpoint += check_debug_unit (DebugStoreData, value);
928
    }
929
 
930
  if (config.dc.enabled)
931
    dc_simulate_write (phys_memaddr, memaddr, value, 2);
932
  else
933
    setsim_mem16 (phys_memaddr, memaddr, value);
934
 
935
  if (cur_area && cur_area->log)
936
    fprintf (cur_area->log, "[%" PRIxADDR "] -> write %04" PRIx16 "\n",
937
             memaddr, value);
938
}
939
 
940
/*
941
 * STATISTICS NOT OK.
942
 */
943
void
944
set_direct16 (oraddr_t memaddr, uint16_t value, int through_mmu,
945
              int through_dc)
946
{
947
  oraddr_t phys_memaddr;
948
  struct dev_memarea *mem;
949
 
950
  if (memaddr & 1)
951
    {
952
      PRINTF ("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__,
953
              __FUNCTION__);
954
      return;
955
    }
956
 
957
  phys_memaddr = memaddr;
958
 
959
  if (through_mmu)
960
    {
961
      /* 0 - no write access, we do not want a DPF exception do we ;)
962
       */
963
      phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
964
    }
965
 
966
  if (through_dc)
967
    dc_simulate_write (memaddr, memaddr, value, 2);
968
  else
969
    {
970
      if ((mem = verify_memoryarea (phys_memaddr)))
971
        mem->direct_ops.writefunc16 (phys_memaddr & mem->size_mask, value,
972
                                     mem->direct_ops.write_dat16);
973
      else
974 220 jeremybenn
        fprintf (stderr, "ERR: 16-bit write out of memory area: %" PRIxADDR
975
                 " (physical: %" PRIxADDR "\n", memaddr, phys_memaddr);
976 19 jeremybenn
    }
977
 
978
  if (cur_area && cur_area->log)
979
    fprintf (cur_area->log, "[%" PRIxADDR "] -> DIRECT write %04" PRIx16 "\n",
980
             memaddr, value);
981
}
982
 
983
/* Set mem, 8-bit. */
984
void
985
set_mem8 (oraddr_t memaddr, uint8_t value, int *breakpoint)
986
{
987
  oraddr_t phys_memaddr;
988
 
989
  if (config.sim.mprofile)
990
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
991
 
992
  phys_memaddr = memaddr;
993
 
994
  phys_memaddr = dmmu_translate (memaddr, 1);;
995
  /* If we produced exception don't set anything */
996
  if (except_pending)
997
    return;
998
 
999 556 julius
  if (config.pcu.enabled)
1000
    pcu_count_event(SPR_PCMR_SA);
1001
 
1002 19 jeremybenn
  if (config.debug.enabled)
1003
    {
1004
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
1005
      *breakpoint += check_debug_unit (DebugStoreData, value);
1006
    }
1007
 
1008
  if (config.dc.enabled)
1009
    dc_simulate_write (phys_memaddr, memaddr, value, 1);
1010
  else
1011
    setsim_mem8 (phys_memaddr, memaddr, value);
1012
 
1013
  if (cur_area && cur_area->log)
1014
    fprintf (cur_area->log, "[%" PRIxADDR "] -> write %02" PRIx8 "\n",
1015
             memaddr, value);
1016
}
1017
 
1018
/*
1019
 * STATISTICS NOT OK.
1020
 */
1021
void
1022
set_direct8 (oraddr_t memaddr, uint8_t value, int through_mmu, int through_dc)
1023
{
1024
  oraddr_t phys_memaddr;
1025
  struct dev_memarea *mem;
1026
 
1027
  phys_memaddr = memaddr;
1028
 
1029
  if (through_mmu)
1030
    {
1031
      /* 0 - no write access, we do not want a DPF exception do we ;)
1032
       */
1033
      phys_memaddr = peek_into_dtlb (memaddr, 0, through_dc);
1034
    }
1035
 
1036
  if (through_dc)
1037
    dc_simulate_write (phys_memaddr, memaddr, value, 1);
1038
  else
1039
    {
1040
      if ((mem = verify_memoryarea (phys_memaddr)))
1041
        mem->direct_ops.writefunc8 (phys_memaddr & mem->size_mask, value,
1042
                                    mem->direct_ops.write_dat8);
1043
      else
1044 220 jeremybenn
        fprintf (stderr, "ERR: 8-bit write out of memory area: %" PRIxADDR
1045
                 " (physical: %" PRIxADDR "\n", memaddr, phys_memaddr);
1046 19 jeremybenn
    }
1047
 
1048
  if (cur_area && cur_area->log)
1049
    fprintf (cur_area->log, "[%" PRIxADDR "] -> DIRECT write %02" PRIx8 "\n",
1050
             memaddr, value);
1051
}
1052
 
1053
 
1054
/* set_program32 - same as set_direct32, but it also writes to memory that is
1055
 *                 non-writeable to the rest of the sim.  Used to do program
1056
 *                 loading.
1057
 */
1058
void
1059
set_program32 (oraddr_t memaddr, uint32_t value)
1060
{
1061
  struct dev_memarea *mem;
1062
 
1063
  if (memaddr & 3)
1064
    {
1065
      PRINTF ("%s(): ERR unaligned 32-bit program write\n", __FUNCTION__);
1066
      return;
1067
    }
1068
 
1069
  if ((mem = verify_memoryarea (memaddr)))
1070
    {
1071
      mem->ops.writeprog32 (memaddr & mem->size_mask, value,
1072
                            mem->ops.writeprog32_dat);
1073
    }
1074
  else
1075
    PRINTF ("ERR: 32-bit program load out of memory area: %" PRIxADDR "\n",
1076
            memaddr);
1077
}
1078
 
1079
/* set_program8 - same as set_direct8, but it also writes to memory that is
1080
 *                non-writeable to the rest of the sim.  Used to do program
1081
 *                loading.
1082
 */
1083
void
1084
set_program8 (oraddr_t memaddr, uint8_t value)
1085
{
1086
  struct dev_memarea *mem;
1087
 
1088
  if ((mem = verify_memoryarea (memaddr)))
1089
    {
1090
      mem->ops.writeprog8 (memaddr & mem->size_mask, value,
1091
                           mem->ops.writeprog8_dat);
1092
    }
1093
  else
1094
    PRINTF ("ERR: 8-bit program load out of memory area: %" PRIxADDR "\n",
1095
            memaddr);
1096
}
1097
 
1098
 
1099
/*---------------------------------------------------------------------------*/
1100
/*!Dump memory to the current output
1101
 
1102
   Output format is hex bytes, 16 bytes per line. Start each line with its
1103
   address and (optionally) its symbolic name. Always end with a newline.
1104
 
1105
   There are all sorts of ways to trip this up, but they are unlikely. The
1106
   validity of a memory area is taken from the address of the start of a line
1107
   to be printed, so assumes the following 15 bytes are present. This could be
1108
   fooled by ridiculous memory declarations.
1109
 
1110
   @param[in] from    Start address of the area of memory
1111
   @param[in] to      End address of the area of memory                      */
1112
/*---------------------------------------------------------------------------*/
1113
void
1114
dump_memory (oraddr_t from, oraddr_t to)
1115
{
1116
  const int ROW_LEN = 16;
1117
  oraddr_t i;                   /* Row counter */
1118
 
1119
  for (i = from; i < to; i += ROW_LEN)
1120
    {
1121
      struct label_entry *entry = get_label (i);
1122
      oraddr_t j;               /* Index in row */
1123
 
1124
      PRINTF ("%" PRIxADDR, i);
1125
 
1126
      if (NULL != entry)
1127
        {
1128
          int padding = 11 - strlen (entry->name);
1129
 
1130
          PRINTF (" <%s>: ", entry->name);
1131
          PRINTF ("%*s ", padding < 0 ? 0 : padding, " ");
1132
        }
1133
      else
1134
        {
1135
          PRINTF (":                ");
1136
        }
1137
 
1138
 
1139
      for (j = 0; j < ROW_LEN; j++)
1140
        {
1141
          if (verify_memoryarea (i + j))
1142
            {
1143
              PRINTF ("%02" PRIx8 " ", eval_direct8 (i + j, 0, 0));
1144
            }
1145
          else
1146
            {
1147
              /* Not a valid memory area. Print Xs as required */
1148
              PRINTF ("XX ");
1149
            }
1150
        }
1151
 
1152
      PRINTF ("\n");
1153
    }
1154
}                               /* dump_memory() */
1155
 
1156
 
1157
/*---------------------------------------------------------------------------*/
1158
/*!Disassemble memory to the current output
1159
 
1160
   Output format is symbolic disassembly, one instruction per line. Start each
1161
   line with its address and (optionally) its symbolic name.
1162
 
1163
   There are all sorts of ways to trip this up, but they are unlikely. The
1164
   validity of a memory area is taken from the address of the start of a line
1165
   to be printed, so assumes the following 3 bytes are present. This could be
1166
   fooled by ridiculous memory declarations.
1167
 
1168
   @param[in] from    Start address of the area of memory
1169
   @param[in] to      End address of the area of memory
1170
   @param[in] nl      If non-zero (true) print a newline at the end of each
1171
                      line                                                   */
1172
/*---------------------------------------------------------------------------*/
1173
void
1174
disassemble_memory (oraddr_t from, oraddr_t to, int nl)
1175
{
1176
  const int INSTR_LEN = 4;
1177
  oraddr_t i;                   /* Row counter */
1178
 
1179
  for (i = from; i < to; i += INSTR_LEN)
1180
    {
1181
      struct label_entry *entry = get_label (i);
1182
 
1183
      PRINTF ("%" PRIxADDR, i);
1184
 
1185
      if (NULL != entry)
1186
        {
1187
          int padding = 11 - strlen (entry->name);
1188
 
1189
          PRINTF (" <%s>: ", entry->name);
1190
          PRINTF ("%*s ", padding < 0 ? 0 : padding, " ");
1191
        }
1192
      else
1193
        {
1194
          PRINTF (":                ");
1195
        }
1196
 
1197
      if (verify_memoryarea (i))
1198
        {
1199
          uint32_t insn = eval_direct32 (i, 0, 0);
1200 230 jeremybenn
          int index = or1ksim_insn_decode (insn);
1201 19 jeremybenn
 
1202
          PRINTF ("%08" PRIx32 " ", insn);
1203
 
1204
          if (index >= 0)
1205
            {
1206 230 jeremybenn
              or1ksim_disassemble_insn (insn);
1207
              PRINTF (" %s", or1ksim_disassembled);
1208 19 jeremybenn
            }
1209
          else
1210
            {
1211
              PRINTF ("<invalid>");
1212
            }
1213
 
1214
        }
1215
      else
1216
        {
1217
          /* Not a valid memory area. Print Xs as required */
1218
          PRINTF ("XXXXXXXX");
1219
        }
1220
 
1221
      if (nl)
1222
        {
1223
          PRINTF ("\n");
1224
        }
1225
    }
1226 420 jeremybenn
}       /* disassemble_memory() */
1227 19 jeremybenn
 
1228
 
1229 420 jeremybenn
/*---------------------------------------------------------------------------*/
1230
/*!Trace the current instr to output
1231
 
1232
   This is a simpler form of disassemble_memory for GDB instruction tracing.
1233
 
1234
   Output format is symbolic disassembly, one instruction per line. Start each
1235 472 jeremybenn
   line with a flag to indicate supervisor or user mode then its hex address
1236
   (physical and/or virtual in that order). At the end print the value of any
1237
   destination register, the flag and the number of cycles executed.
1238 420 jeremybenn
 
1239
   There are all sorts of ways to trip this up, but they are unlikely. The
1240
   validity of a memory area is taken from the address of the start of a line
1241
   to be printed, so assumes the following 3 bytes are present. This could be
1242
   fooled by ridiculous memory declarations.
1243
 
1244 472 jeremybenn
   @param[in] phyaddr   Physical address of the instruction to trace
1245
   @param[in] virtaddr  Virtual address of the instruction to trace
1246
   @param[in] insn      The instruction just fetched and possibly executed.  */
1247 420 jeremybenn
/*---------------------------------------------------------------------------*/
1248
void
1249 472 jeremybenn
disassemble_instr (oraddr_t  phyaddr,
1250
                   oraddr_t  virtaddr,
1251
                   uint32_t  insn)
1252 420 jeremybenn
{
1253 472 jeremybenn
  /* Log whether we are supervisor mode */
1254
  printf ("%c ",
1255
          (SPR_SR_SM == (cpu_state.sprs[SPR_SR] & SPR_SR_SM)) ? 'S' : 'U');
1256
 
1257
  /* The address */
1258
  if (runtime.sim.trace_phy)
1259
    {
1260
      PRINTF ("%" PRIxADDR ": ", phyaddr);
1261
    }
1262 420 jeremybenn
 
1263 472 jeremybenn
  if (runtime.sim.trace_virt)
1264 420 jeremybenn
    {
1265 472 jeremybenn
      PRINTF ("%" PRIxADDR ": ", virtaddr);
1266
    }
1267 420 jeremybenn
 
1268 472 jeremybenn
  /* The instruction details */
1269
  int  index = or1ksim_insn_decode (insn);
1270 420 jeremybenn
 
1271 472 jeremybenn
  PRINTF ("%08" PRIx32 " ", insn);
1272
 
1273
  if (index >= 0)
1274
    {
1275
      or1ksim_disassemble_trace_index (insn, index);
1276
      PRINTF ("%-24s", or1ksim_disassembled);
1277
 
1278
      /* Put either the register assignment, SPR value, or store */
1279
      if (-1 != trace_dest_spr)
1280 420 jeremybenn
        {
1281 472 jeremybenn
          PRINTF ("SPR[%04x]  = %08x", (trace_dest_spr |
1282
                                        evalsim_reg (trace_dest_reg)),
1283
                  cpu_state.sprs[(trace_dest_spr |
1284
                                  evalsim_reg (trace_dest_reg))]);
1285 420 jeremybenn
 
1286 472 jeremybenn
        }
1287
      else if (-1 != trace_dest_reg)
1288
        {
1289
          PRINTF ("r%-2u        = %" PRIxREG "", trace_dest_reg,
1290
                  evalsim_reg (trace_dest_reg));
1291
        }
1292
      else
1293
        {
1294
          uorreg_t  store_val  = 0;
1295
          oraddr_t  store_addr = 0;
1296
 
1297
          if (0 != trace_store_width)
1298 420 jeremybenn
            {
1299 472 jeremybenn
              store_val  = evalsim_reg (trace_store_val_reg);
1300
              store_addr = evalsim_reg (trace_store_addr_reg) +
1301
                trace_store_imm;
1302 420 jeremybenn
            }
1303 472 jeremybenn
 
1304
          switch (trace_store_width)
1305 420 jeremybenn
            {
1306 472 jeremybenn
            case 1:
1307
              PRINTF ("[%" PRIxADDR "] = %02x      ", store_addr,
1308
                      store_val);
1309
              break;
1310 420 jeremybenn
 
1311 472 jeremybenn
            case 2:
1312
              PRINTF ("[%" PRIxADDR "] = %04x    ", store_addr, store_val);
1313
              break;
1314 420 jeremybenn
 
1315 472 jeremybenn
            case 4:
1316
              PRINTF ("[%" PRIxADDR "] = %08x", store_addr, store_val);
1317
              break;
1318 420 jeremybenn
 
1319 472 jeremybenn
            default:
1320
              PRINTF ("                     ");
1321
              break;
1322 420 jeremybenn
            }
1323 472 jeremybenn
        }
1324 458 julius
 
1325 420 jeremybenn
 
1326 472 jeremybenn
      /* Print the flag */
1327
      PRINTF ("  flag: %u\n", cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
1328 420 jeremybenn
 
1329
    }
1330
  else
1331
    {
1332 472 jeremybenn
      PRINTF ("<invalid>\n");
1333 420 jeremybenn
    }
1334
}       /* disassemble_instr() */
1335
 
1336
 
1337 19 jeremybenn
/* Closes files, etc. */
1338
 
1339
void
1340
done_memory_table ()
1341
{
1342
  struct dev_memarea *ptmp;
1343
 
1344
  /* Check list of registered devices. */
1345
  for (ptmp = dev_list; ptmp; ptmp = ptmp->next)
1346
    {
1347
      if (ptmp->log)
1348
        fclose (ptmp->log);
1349
    }
1350
}
1351
 
1352
/* Displays current memory configuration */
1353
 
1354
void
1355
memory_table_status (void)
1356
{
1357
  struct dev_memarea *ptmp;
1358
 
1359
  /* Check list of registered devices. */
1360
  for (ptmp = dev_list; ptmp; ptmp = ptmp->next)
1361
    {
1362
      PRINTF ("addr & %" PRIxADDR " == %" PRIxADDR " to %" PRIxADDR ", size %"
1363
              PRIx32 "\n", ptmp->addr_mask, ptmp->addr_compare,
1364
              ptmp->addr_compare | bit_mask (ptmp->size), ptmp->size);
1365
      PRINTF ("\t");
1366
      if (ptmp->ops.delayr >= 0)
1367
        PRINTF ("read delay = %i cycles, ", ptmp->ops.delayr);
1368
      else
1369
        PRINTF ("reads not possible, ");
1370
 
1371
      if (ptmp->ops.delayw >= 0)
1372
        PRINTF ("write delay = %i cycles", ptmp->ops.delayw);
1373
      else
1374
        PRINTF ("writes not possible");
1375
 
1376
      if (ptmp->log)
1377
        PRINTF (", (logged)\n");
1378
      else
1379
        PRINTF ("\n");
1380
    }
1381
}
1382
 
1383
/* Outputs time in pretty form to dest string */
1384
 
1385
char *
1386
generate_time_pretty (char *dest, long time_ps)
1387
{
1388
  int exp3 = 0;
1389
  if (time_ps)
1390
    {
1391
      while ((time_ps % 1000) == 0)
1392
        {
1393
          time_ps /= 1000;
1394
          exp3++;
1395
        }
1396
    }
1397
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
1398
  return dest;
1399
}

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