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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [execute.h] - Blame information for rev 774

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1 19 jeremybenn
/* execute.h -- Header file for architecture dependent execute.c
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   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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   Copyright (C) 2008 Embecosm Limited
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   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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/* This program is commented throughout in a fashion suitable for processing
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   with Doxygen. */
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#ifndef EXECUTE__H
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#define EXECUTE__H
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#include "spr-defs.h"
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#include "opcode/or32.h"
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#include "abstract.h"
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#define CURINSN(INSN) (strcmp(cur->insn, (INSN)) == 0)
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/*!The main structure holding the current execution state of the CPU
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   Not to be confused with @c runtime, which holds the state of the
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   simulation.
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   @c insn_ea field is only used to get dump_exe_log() correct.
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   @c iqueue and @c icomplet fields are only used in analysis().
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   The micro-operation queue, @c opqs, is only used to speed up
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   recompile_page().                                                         */
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struct cpu_state {
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  uorreg_t             reg[MAX_GPRS];   /*!< General purpose registers */
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  uorreg_t             sprs[MAX_SPRS];  /*!< Special purpose registers */
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  oraddr_t             insn_ea;         /*!< EA of instrs that have an EA */
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  int                  delay_insn;      /*!< Is current instr in delay slot */
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  int                  npc_not_valid;   /*!< NPC updated while stalled */
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  oraddr_t             pc;              /*!< PC (and translated PC) */
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  oraddr_t             pc_delay;        /*!< Delay instr EA register */
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  struct iqueue_entry  iqueue;          /*!< Decode of just executed instr */
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  struct iqueue_entry  icomplet;        /*!< Decode of instr before this */
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};
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/*! History of execution */
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struct hist_exec
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{
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  oraddr_t addr;
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  struct hist_exec *prev;
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  struct hist_exec *next;
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};
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/* Globally visible data structures */
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extern struct cpu_state  cpu_state;
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extern oraddr_t          pcnext;
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extern int               sbuf_wait_cyc;
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extern int               sbuf_total_cyc;
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extern int               do_stats;
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extern struct hist_exec *hist_exec_tail;
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/* Prototypes for external use */
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extern void      dumpreg ();
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extern void      trace_instr ();
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extern void      dump_exe_log ();
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extern void      dump_exe_bin_insn_log (struct iqueue_entry *current);
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extern int       cpu_clock ();
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extern void      cpu_reset ();
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extern uorreg_t  evalsim_reg (unsigned int  regno);
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extern void      setsim_reg (unsigned int  regno,
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                             uorreg_t      value);
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extern uorreg_t  eval_operand_val (uint32_t               insn,
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                                   struct insn_op_struct *opd);
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extern void      analysis (struct iqueue_entry *current);
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extern void      cpu_reset ();
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extern int       cpu_clock ();
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extern void      exec_main ();
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extern int       depend_operands (struct iqueue_entry *prev,
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                                  struct iqueue_entry *next);
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#endif  /* EXECUTE__H */

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