OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [trace.c] - Blame information for rev 590

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jeremybenn
/* trace.c -- Simulator breakpoints
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
 
27
/* Autoconf and/or portability configuration */
28
#include "config.h"
29
 
30
/* Package includes */
31
#include "trace.h"
32
#include "sim-config.h"
33
#include "abstract.h"
34
#include "labels.h"
35
 
36
 
37
/*---------------------------------------------------------------------------*/
38
/*!Set instruction execution breakpoint
39
 
40
   @param[in] addr  The address for the breakpoint                           */
41
/*---------------------------------------------------------------------------*/
42
void
43
set_insnbrkpoint (oraddr_t addr)
44
{
45
  addr &= ~ADDR_C (3);          /* 32-bit aligned */
46
 
47
  if (!verify_memoryarea (addr))
48
    {
49
      PRINTF
50
        ("WARNING: This breakpoint is out of the simulated memory range.\n");
51
    }
52
 
53
  if (has_breakpoint (addr))
54
    {
55
      remove_breakpoint (addr);
56
      PRINTF ("\nBreakpoint at 0x%" PRIxADDR " cleared.\n", addr);
57
    }
58
  else
59
    {
60
      add_breakpoint (addr);
61
      PRINTF ("\nBreakpoint at 0x%" PRIxADDR " set.\n", addr);
62
    }
63
 
64
  return;
65
 
66
}       /* set_insnbrkpoint () */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.