OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [arch.h] - Blame information for rev 161

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jeremybenn
/* arch.h -- OR1K architecture specific macros
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
 
27
#ifndef ARCH__H
28
#define ARCH__H
29
 
30
/* Autoconf and/or portability configuration */
31
#include "port.h"
32
 
33
/*! Index of the link register */
34
#define LINK_REGNO     9
35
 
36
/* Conversion macros */
37
#define ADDR_C(c)  UINT32_C(c)
38
#define REG_C(c)   UINT32_C(c)
39
 
40
/* Strings for printing OpenRISC types */
41
#define PRIxADDR  "08" PRIx32   /*!< print an openrisc address in hex */
42
#define PRIxREG   "08" PRIx32   /*!< print an openrisc register in hex */
43
#define PRIdREG   PRId32        /*!< print an openrisc register in decimals */
44
 
45
/* Basic types for openrisc */
46
typedef uint32_t  oraddr_t;     /*!< Address as addressed by openrisc */
47
typedef uint32_t  uorreg_t;     /*!< An unsigned register of openrisc */
48
typedef int32_t   orreg_t;      /*!< A signed register of openrisc */
49
 
50
#endif /* ARCH__H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.