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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [except.c] - Blame information for rev 352

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1 19 jeremybenn
/* except.c -- Simulation of OR1K exceptions
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   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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   Copyright (C) 2008 Embecosm Limited
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   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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/* This program is commented throughout in a fashion suitable for processing
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   with Doxygen. */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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/* Package includes */
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#include "except.h"
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#include "sim-config.h"
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#include "arch.h"
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#include "debug.h"
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#include "spr-defs.h"
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#include "execute.h"
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#include "debug-unit.h"
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#if DYNAMIC_EXECUTION
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#include "sched.h"
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#include "op-support.h"
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#endif
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extern void op_join_mem_cycles(void);
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int except_pending = 0;
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/* Asserts OR1K exception. */
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/* WARNING: Don't expect except_handle to return.  Sometimes it _may_ return at
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 * other times it may not. */
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void
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except_handle (oraddr_t except, oraddr_t ea)
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{
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  oraddr_t except_vector;
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  if (debug_ignore_exception (except))
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    return;
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#if !(DYNAMIC_EXECUTION)
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  /* In the dynamic recompiler, this function never returns, so this is not
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   * needed.  Ofcourse we could set it anyway, but then all code that checks
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   * this variable would break, since it is never reset */
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  except_pending = 1;
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#endif
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  except_vector =
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    except + (cpu_state.sprs[SPR_SR] & SPR_SR_EPH ? 0xf0000000 : 0x00000000);
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#if !(DYNAMIC_EXECUTION)
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  pcnext = except_vector;
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#endif
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  cpu_state.sprs[SPR_EEAR_BASE] = ea;
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  cpu_state.sprs[SPR_ESR_BASE] = cpu_state.sprs[SPR_SR];
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  cpu_state.sprs[SPR_SR] &= ~SPR_SR_OVE;        /* Disable overflow flag exception. */
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  cpu_state.sprs[SPR_SR] |= SPR_SR_SM;  /* SUPV mode */
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  cpu_state.sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */
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  /* Address translation is always disabled when starting exception. */
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  cpu_state.sprs[SPR_SR] &= ~SPR_SR_DME;
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#if DYNAMIC_EXECUTION
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  /* If we were called from do_scheduler and there were more jobs scheduled to
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   * run after this, they won't run unless the following call is made since this
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   * function never returns.  (If we weren't called from do_scheduler, then the
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   * job at the head of the queue will still have some time remaining) */
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  if (scheduler.job_queue->time <= 0)
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    do_scheduler ();
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#endif
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  switch (except)
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    {
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      /* EPCR is irrelevent */
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    case EXCEPT_RESET:
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      break;
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      /* EPCR is loaded with address of instruction that caused the exception */
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    case EXCEPT_ITLBMISS:
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    case EXCEPT_IPF:
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      cpu_state.sprs[SPR_EPCR_BASE] = ea - (cpu_state.delay_insn ? 4 : 0);
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#if DYNAMIC_EXECUTION
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      op_join_mem_cycles ();
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#endif
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      break;
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    case EXCEPT_BUSERR:
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    case EXCEPT_DPF:
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    case EXCEPT_ALIGN:
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    case EXCEPT_ILLEGAL:
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    case EXCEPT_DTLBMISS:
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    case EXCEPT_RANGE:
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    case EXCEPT_TRAP:
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      /* All these exceptions happen during a simulated instruction */
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#if DYNAMIC_EXECUTION
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      /* Since these exceptions happen during a simulated instruction and this
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       * function jumps out to the exception vector the scheduler would never have
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       * a chance to run, therefore run it now */
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      run_sched_out_of_line ();
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#endif
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      cpu_state.sprs[SPR_EPCR_BASE] =
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        cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
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      break;
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      /* EPCR is loaded with address of next not-yet-executed instruction */
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    case EXCEPT_SYSCALL:
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      cpu_state.sprs[SPR_EPCR_BASE] =
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        (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0);
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      break;
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      /* These exceptions happen AFTER (or before) an instruction has been
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       * simulated, therefore the pc already points to the *next* instruction */
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    case EXCEPT_TICK:
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    case EXCEPT_INT:
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      cpu_state.sprs[SPR_EPCR_BASE] =
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        cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
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#if !(DYNAMIC_EXECUTION)
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      /* If we don't update the pc now, then it will only happen *after* the next
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       * instruction (There would be serious problems if the next instruction just
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       * happens to be a branch), when it should happen NOW. */
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      cpu_state.pc = pcnext;
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      pcnext += 4;
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#endif
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      break;
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    }
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  /* Address trnaslation is here because run_sched_out_of_line calls
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   * eval_insn_direct which checks out the immu for the address translation but
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   * if it would be disabled above then there would be not much point... */
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  cpu_state.sprs[SPR_SR] &= ~SPR_SR_IME;
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  /* Complex/simple execution strictly don't need this because of the
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   * next_delay_insn thingy but in the dynamic execution modell that doesn't
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   * exist and thus cpu_state.delay_insn would stick in the exception handler
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   * causeing grief if the first instruction of the exception handler is also in
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   * the delay slot of the previous instruction */
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  cpu_state.delay_insn = 0;
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#if DYNAMIC_EXECUTION
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  do_jump (except_vector);
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#endif
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}

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