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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [opcode/] [or32.h] - Blame information for rev 352

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1 19 jeremybenn
/* Table of opcodes for the OpenRISC 1000 ISA.
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   Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
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   Copyright (C) 2008 Embecosm Limited
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   Contributed by Damjan Lampret (lampret@opencores.org).
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   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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   This file is also part of or1k_gen_isa, GDB and GAS.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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/* This program is commented throughout in a fashion suitable for processing
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   with Doxygen. */
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/* We treat all letters the same in encode/decode routines so
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   we need to assign some characteristics to them like signess etc.*/
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#ifndef OR32_H_ISA
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#define OR32_H_ISA
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#define NUM_UNSIGNED (0)
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#define NUM_SIGNED (1)
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#ifndef PARAMS
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#define PARAMS(x) x
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#endif
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#ifndef CONST
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#define CONST const
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#endif
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#define MAX_GPRS 32
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#define PAGE_SIZE 8192
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#undef __HALF_WORD_INSN__
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#define OPERAND_DELIM (',')
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#define OR32_IF_DELAY (1)
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#define OR32_W_FLAG   (2)
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#define OR32_R_FLAG   (4)
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#if defined(HAVE_EXECUTION)
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# if SIMPLE_EXECUTION
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#  include "simpl32-defs.h"
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# elif DYNAMIC_EXECUTION
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#  include "dyn32-defs.h"
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# endif
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#endif
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struct or32_letter {
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  char letter;
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  int  sign;
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  /* int  reloc; relocation per letter ??*/
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};
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enum insn_type {
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 it_unknown,
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 it_exception,
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 it_arith,
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 it_shift,
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 it_compare,
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 it_branch,
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 it_jump,
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 it_load,
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 it_store,
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 it_movimm,
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 it_move,
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 it_extend,
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 it_nop,
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 it_mac,
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 it_float };
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/* Main instruction specification array.  */
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struct or32_opcode {
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  /* Name of the instruction.  */
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  char *name;
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  /* A string of characters which describe the operands.
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     Valid characters are:
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     ,() Itself.  Characters appears in the assembly code.
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     rA  Register operand.
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     rB  Register operand.
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     rD  Register operand (destination).
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     I   An immediate operand, range -32768 to 32767.
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     J   An immediate operand, range . (unused)
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     K   An immediate operand, range 0 to 65535.
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     L   An immediate operand, range 0 to 63.
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     M   An immediate operand, range . (unused)
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     N   An immediate operand, range -33554432 to 33554431.
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     O   An immediate operand, range . (unused) */
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  char *args;
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  /* Opcode and operand encoding. */
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  char *encoding;
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#ifdef HAVE_EXECUTION
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# if COMPLEX_EXECUTION
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  char *function_name;
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# elif SIMPLE_EXECUTION
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  void (*exec)(struct iqueue_entry *);
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# else /* DYNAMIC_EXECUTION */
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  void (*exec)(struct op_queue *opq, int param_t[3], int);
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# endif
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#else  /* HAVE_EXECUTION */
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  void (*exec)(void);
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#endif
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  unsigned int flags;
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  enum insn_type func_unit;
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};
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/* This operand is the last in the list */
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#define OPTYPE_LAST (0x80000000)
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/* This operand marks the end of the operand sequence (for things like I(rD)) */
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#define OPTYPE_OP   (0x40000000)
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/* The operand specifies a register index */
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#define OPTYPE_REG  (0x20000000)
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/* The operand must be sign extended */
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#define OPTYPE_SIG  (0x10000000)
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/* Operand is a relative address, the `I' in `I(rD)' */
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#define OPTYPE_DIS  (0x08000000)
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/* The operand is a destination */
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#define OPTYPE_DST  (0x04000000)
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/* Which bit of the operand is the sign bit */
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#define OPTYPE_SBIT (0x00001F00)
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/* Amount to shift the instruction word right to get the operand */
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#define OPTYPE_SHR  (0x0000001F)
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#define OPTYPE_SBIT_SHR (8)
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/* MM: Data how to decode operands.  */
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extern struct insn_op_struct {
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  unsigned long type;
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  unsigned long data;
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} **or1ksim_op_start;
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/* Leaf flag used in automata building */
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#define LEAF_FLAG         (0x80000000)
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struct temp_insn_struct
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{
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  unsigned long insn;
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  unsigned long insn_mask;
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  int in_pass;
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};
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extern unsigned long *or1ksim_automata;
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extern struct temp_insn_struct *or1ksim_ti;
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extern CONST struct  or32_opcode  or1ksim_or32_opcodes[];
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extern char *or1ksim_disassembled;
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/* Calculates instruction length in bytes.  Always 4 for OR32. */
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extern int or1ksim_insn_len PARAMS((int insn_index));
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/* MM: Returns instruction name from index.  */
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extern CONST char *or1ksim_insn_name PARAMS ((int index));
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/* MM: Constructs new FSM, based on or1ksim_or32_opcodes.  */
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extern void or1ksim_build_automata PARAMS ((int  quiet));
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/* MM: Destructs FSM.  */
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extern void or1ksim_destruct_automata PARAMS ((void));
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/* MM: Decodes instruction using FSM.  Call or1ksim_build_automata first.  */
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extern int or1ksim_insn_decode PARAMS((unsigned int insn));
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/* Disassemble one instruction from insn to disassemble.
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   Return the size of the instruction.  */
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extern int or1ksim_disassemble_insn (unsigned long insn);
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/* Disassemble one instruction from insn index.
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   Return the size of the instruction.  */
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int or1ksim_disassemble_index (unsigned long insn, int index);
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/* FOR INTERNAL USE ONLY */
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/* Automatically does zero- or sign- extension and also finds correct
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   sign bit position if sign extension is correct extension. Which extension
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   is proper is figured out from letter description. */
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unsigned long or1ksim_extend_imm(unsigned long imm, char l);
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/* Extracts value from opcode */
197 230 jeremybenn
unsigned long or1ksim_or32_extract(char param_ch, char *enc_initial, unsigned long insn);
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#endif
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