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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [spr-defs.h] - Blame information for rev 224

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1 82 jeremybenn 
/* ipc.h.  Microkernel IPC header for Or1ksim
2 
 
3 
   Copyright (C) 2000 Damjan Lampret
4 
   Copyright (C) 2008, 2010 Embecosm Limited
5 
 
6 
   Contributor Damjan Lampret <lampret@opencores.org>
7 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8 
 
9 
   This file is part of OpenRISC 1000 Architectural Simulator.
10 
 
11 
   This program is free software; you can redistribute it and/or modify it
12 
   under the terms of the GNU General Public License as published by the Free
13 
   Software Foundation; either version 3 of the License, or (at your option)
14 
   any later version.
15 
 
16 
   This program is distributed in the hope that it will be useful, but WITHOUT
17 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19 
   more details.
20 
 
21 
   You should have received a copy of the GNU General Public License along
22 
   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
23 
 
24 
/* ----------------------------------------------------------------------------
25 
   This code is commented throughout for use with Doxygen.
26 
   --------------------------------------------------------------------------*/
27 
 
28 
/* This file is part of test microkernel for OpenRISC 1000. */
29 19 jeremybenn 
/* spr-defs.h -- Defines OR1K architecture specific special-purpose registers
30 
 
31 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
32 
   Copyright (C) 2008 Embecosm Limited
33 
 
34 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
35 
 
36 
   This file is part of OpenRISC 1000 Architectural Simulator.
37 
 
38 
   This program is free software; you can redistribute it and/or modify it
39 
   under the terms of the GNU General Public License as published by the Free
40 
   Software Foundation; either version 3 of the License, or (at your option)
41 
   any later version.
42 
 
43 
   This program is distributed in the hope that it will be useful, but WITHOUT
44 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
45 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
46 
   more details.
47 
 
48 
   You should have received a copy of the GNU General Public License along
49 
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
50 
 
51 
/* This program is commented throughout in a fashion suitable for processing
52 
   with Doxygen. */
53 
 
54 
 
55 
#ifndef SPR_DEFS__H
56 
#define SPR_DEFS__H
57 
 
58 
/* Definition of special-purpose registers (SPRs). */
59 
 
60 
#define MAX_GRPS (32)
61 
#define MAX_SPRS_PER_GRP_BITS (11)
62 
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
63 
#define MAX_SPRS (0x10000)
64 
 
65 
/* Base addresses for the groups */
66 
#define SPRGROUP_SYS    (0<< MAX_SPRS_PER_GRP_BITS)
67 
#define SPRGROUP_DMMU   (1<< MAX_SPRS_PER_GRP_BITS)
68 
#define SPRGROUP_IMMU   (2<< MAX_SPRS_PER_GRP_BITS)
69 
#define SPRGROUP_DC     (3<< MAX_SPRS_PER_GRP_BITS)
70 
#define SPRGROUP_IC     (4<< MAX_SPRS_PER_GRP_BITS)
71 
#define SPRGROUP_MAC    (5<< MAX_SPRS_PER_GRP_BITS)
72 
#define SPRGROUP_D      (6<< MAX_SPRS_PER_GRP_BITS)
73 
#define SPRGROUP_PC     (7<< MAX_SPRS_PER_GRP_BITS)
74 
#define SPRGROUP_PM     (8<< MAX_SPRS_PER_GRP_BITS)
75 
#define SPRGROUP_PIC    (9<< MAX_SPRS_PER_GRP_BITS)
76 
#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)
77 
 
78 
/* System control and status group */
79 
#define SPR_VR          (SPRGROUP_SYS + 0)
80 
#define SPR_UPR         (SPRGROUP_SYS + 1)
81 
#define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
82 
#define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
83 
#define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
84 
#define SPR_DCCFGR      (SPRGROUP_SYS + 5)
85 
#define SPR_ICCFGR      (SPRGROUP_SYS + 6)
86 
#define SPR_DCFGR       (SPRGROUP_SYS + 7)
87 
#define SPR_PCCFGR      (SPRGROUP_SYS + 8)
88 
#define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
89 
#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
90 
#define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
91 
#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
92 
#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
93 
#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
94 
#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
95 
#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
96 
#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
97 224 jeremybenn 
#define SPR_GPR_BASE    (SPRGROUP_SYS + 1024)
98 19 jeremybenn 
 
99 
/* Data MMU group */
100 
#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
101 
#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
102 
#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
103 
#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
104 
#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
105 
 
106 
/* Instruction MMU group */
107 
#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
108 
#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
109 
#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
110 
#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
111 
#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
112 
 
113 
/* Data cache group */
114 
#define SPR_DCCR        (SPRGROUP_DC + 0)
115 
#define SPR_DCBPR       (SPRGROUP_DC + 1)
116 
#define SPR_DCBFR       (SPRGROUP_DC + 2)
117 
#define SPR_DCBIR       (SPRGROUP_DC + 3)
118 
#define SPR_DCBWR       (SPRGROUP_DC + 4)
119 
#define SPR_DCBLR       (SPRGROUP_DC + 5)
120 
#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
121 
#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
122 
 
123 
/* Instruction cache group */
124 
#define SPR_ICCR        (SPRGROUP_IC + 0)
125 
#define SPR_ICBPR       (SPRGROUP_IC + 1)
126 
#define SPR_ICBIR       (SPRGROUP_IC + 2)
127 
#define SPR_ICBLR       (SPRGROUP_IC + 3)
128 
#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
129 
#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
130 
 
131 
/* MAC group */
132 
#define SPR_MACLO       (SPRGROUP_MAC + 1)
133 
#define SPR_MACHI       (SPRGROUP_MAC + 2)
134 
 
135 
/* Debug group */
136 
#define SPR_DVR(N)      (SPRGROUP_D + (N))
137 
#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
138 
#define SPR_DMR1        (SPRGROUP_D + 16)
139 
#define SPR_DMR2        (SPRGROUP_D + 17)
140 
#define SPR_DWCR0       (SPRGROUP_D + 18)
141 
#define SPR_DWCR1       (SPRGROUP_D + 19)
142 
#define SPR_DSR         (SPRGROUP_D + 20)
143 
#define SPR_DRR         (SPRGROUP_D + 21)
144 
 
145 
/* Performance counters group */
146 
#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
147 
#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
148 
 
149 
/* Power management group */
150 
#define SPR_PMR (SPRGROUP_PM + 0)
151 
 
152 
/* PIC group */
153 
#define SPR_PICMR (SPRGROUP_PIC + 0)
154 
#define SPR_PICPR (SPRGROUP_PIC + 1)
155 
#define SPR_PICSR (SPRGROUP_PIC + 2)
156 
 
157 
/* Tick Timer group */
158 
#define SPR_TTMR (SPRGROUP_TT + 0)
159 
#define SPR_TTCR (SPRGROUP_TT + 1)
160 
 
161 
/*
162 
 * Bit definitions for the Version Register
163 
 *
164 
 */
165 
#define SPR_VR_VER      0xff000000  /* Processor version */
166 
#define SPR_VR_CFG      0x00ff0000  /* Processor configuration */
167 
#define SPR_VR_RES      0x00ff0000  /* Reserved */
168 
#define SPR_VR_REV      0x0000003f  /* Processor revision */
169 
 
170 
#define SPR_VR_VER_OFF  24
171 
#define SPR_VR_CFG_OFF  16
172 
#define SPR_VR_REV_OFF  0
173 
 
174 
/*
175 
 * Bit definitions for the Unit Present Register
176 
 *
177 
 */
178 
#define SPR_UPR_UP         0x00000001  /* UPR present */
179 
#define SPR_UPR_DCP        0x00000002  /* Data cache present */
180 
#define SPR_UPR_ICP        0x00000004  /* Instruction cache present */
181 
#define SPR_UPR_DMP        0x00000008  /* Data MMU present */
182 
#define SPR_UPR_IMP        0x00000010  /* Instruction MMU present */
183 
#define SPR_UPR_MP         0x00000020  /* MAC present */
184 
#define SPR_UPR_DUP        0x00000040  /* Debug unit present */
185 
#define SPR_UPR_PCUP       0x00000080  /* Performance counters unit present */
186 
#define SPR_UPR_PMP        0x00000100  /* Power management present */
187 
#define SPR_UPR_PICP       0x00000200  /* PIC present */
188 
#define SPR_UPR_TTP        0x00000400  /* Tick timer present */
189 
#define SPR_UPR_RES        0x00fe0000  /* Reserved */
190 
#define SPR_UPR_CUP        0xff000000  /* Context units present */
191 
 
192 
/*
193 
 * JPB: Bit definitions for the CPU configuration register
194 
 *
195 
 */
196 
#define SPR_CPUCFGR_NSGF   0x0000000f  /* Number of shadow GPR files */
197 
#define SPR_CPUCFGR_CGF    0x00000010  /* Custom GPR file */
198 
#define SPR_CPUCFGR_OB32S  0x00000020  /* ORBIS32 supported */
199 
#define SPR_CPUCFGR_OB64S  0x00000040  /* ORBIS64 supported */
200 
#define SPR_CPUCFGR_OF32S  0x00000080  /* ORFPX32 supported */
201 
#define SPR_CPUCFGR_OF64S  0x00000100  /* ORFPX64 supported */
202 
#define SPR_CPUCFGR_OV64S  0x00000200  /* ORVDX64 supported */
203 
#define SPR_CPUCFGR_RES    0xfffffc00  /* Reserved */
204 
 
205 
/*
206 
 * JPB: Bit definitions for the Debug configuration register and other
207 
 * constants.
208 
 *
209 
 */
210 
 
211 
#define SPR_DCFGR_NDP      0x00000007  /* Number of matchpoints mask */
212 
#define SPR_DCFGR_NDP1     0x00000000  /* One matchpoint supported */
213 
#define SPR_DCFGR_NDP2     0x00000001  /* Two matchpoints supported */
214 
#define SPR_DCFGR_NDP3     0x00000002  /* Three matchpoints supported */
215 
#define SPR_DCFGR_NDP4     0x00000003  /* Four matchpoints supported */
216 
#define SPR_DCFGR_NDP5     0x00000004  /* Five matchpoints supported */
217 
#define SPR_DCFGR_NDP6     0x00000005  /* Six matchpoints supported */
218 
#define SPR_DCFGR_NDP7     0x00000006  /* Seven matchpoints supported */
219 
#define SPR_DCFGR_NDP8     0x00000007  /* Eight matchpoints supported */
220 
#define SPR_DCFGR_WPCI     0x00000008  /* Watchpoint counters implemented */
221 
 
222 
#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
223 
                               2 == n ? SPR_DCFGR_NDP2 : \
224 
                               3 == n ? SPR_DCFGR_NDP3 : \
225 
                               4 == n ? SPR_DCFGR_NDP4 : \
226 
                               5 == n ? SPR_DCFGR_NDP5 : \
227 
                               6 == n ? SPR_DCFGR_NDP6 : \
228 
                               7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
229 
#define MAX_MATCHPOINTS  8
230 
#define MAX_WATCHPOINTS  (MAX_MATCHPOINTS + 2)
231 
 
232 
/*
233 
 * Bit definitions for the Supervision Register
234 
 *
235 
 */
236 
#define SPR_SR_SM          0x00000001  /* Supervisor Mode */
237 
#define SPR_SR_TEE         0x00000002  /* Tick timer Exception Enable */
238 
#define SPR_SR_IEE         0x00000004  /* Interrupt Exception Enable */
239 
#define SPR_SR_DCE         0x00000008  /* Data Cache Enable */
240 
#define SPR_SR_ICE         0x00000010  /* Instruction Cache Enable */
241 
#define SPR_SR_DME         0x00000020  /* Data MMU Enable */
242 
#define SPR_SR_IME         0x00000040  /* Instruction MMU Enable */
243 
#define SPR_SR_LEE         0x00000080  /* Little Endian Enable */
244 
#define SPR_SR_CE          0x00000100  /* CID Enable */
245 
#define SPR_SR_F           0x00000200  /* Condition Flag */
246 
#define SPR_SR_CY          0x00000400  /* Carry flag */
247 
#define SPR_SR_OV          0x00000800  /* Overflow flag */
248 
#define SPR_SR_OVE         0x00001000  /* Overflow flag Exception */
249 
#define SPR_SR_DSX         0x00002000  /* Delay Slot Exception */
250 
#define SPR_SR_EPH         0x00004000  /* Exception Prefix High */
251 
#define SPR_SR_FO          0x00008000  /* Fixed one */
252 
#define SPR_SR_SUMRA       0x00010000  /* Supervisor SPR read access */
253 
#define SPR_SR_RES         0x0ffe0000  /* Reserved */
254 
#define SPR_SR_CID         0xf0000000  /* Context ID */
255 
 
256 
/*
257 
 * Bit definitions for the Data MMU Control Register
258 
 *
259 
 */
260 
#define SPR_DMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
261 
#define SPR_DMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
262 
#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
263 
#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
264 
 
265 
/*
266 
 * Bit definitions for the Instruction MMU Control Register
267 
 *
268 
 */
269 
#define SPR_IMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
270 
#define SPR_IMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
271 
#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
272 
#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
273 
 
274 
/*
275 
 * Bit definitions for the Data TLB Match Register
276 
 *
277 
 */
278 
#define SPR_DTLBMR_V       0x00000001  /* Valid */
279 
#define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
280 
#define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
281 
#define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
282 
#define SPR_DTLBMR_VPN     0xfffff000  /* Virtual Page Number */
283 
 
284 
/*
285 
 * Bit definitions for the Data TLB Translate Register
286 
 *
287 
 */
288 
#define SPR_DTLBTR_CC      0x00000001  /* Cache Coherency */
289 
#define SPR_DTLBTR_CI      0x00000002  /* Cache Inhibit */
290 
#define SPR_DTLBTR_WBC     0x00000004  /* Write-Back Cache */
291 
#define SPR_DTLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
292 
#define SPR_DTLBTR_A       0x00000010  /* Accessed */
293 
#define SPR_DTLBTR_D       0x00000020  /* Dirty */
294 
#define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
295 
#define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
296 
#define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
297 
#define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
298 
#define SPR_DTLBTR_PPN     0xfffff000  /* Physical Page Number */
299 
 
300 
/*
301 
 * Bit definitions for the Instruction TLB Match Register
302 
 *
303 
 */
304 
#define SPR_ITLBMR_V       0x00000001  /* Valid */
305 
#define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
306 
#define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
307 
#define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
308 
#define SPR_ITLBMR_VPN     0xfffff000  /* Virtual Page Number */
309 
 
310 
/*
311 
 * Bit definitions for the Instruction TLB Translate Register
312 
 *
313 
 */
314 
#define SPR_ITLBTR_CC      0x00000001  /* Cache Coherency */
315 
#define SPR_ITLBTR_CI      0x00000002  /* Cache Inhibit */
316 
#define SPR_ITLBTR_WBC     0x00000004  /* Write-Back Cache */
317 
#define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
318 
#define SPR_ITLBTR_A       0x00000010  /* Accessed */
319 
#define SPR_ITLBTR_D       0x00000020  /* Dirty */
320 
#define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
321 
#define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
322 
#define SPR_ITLBTR_PPN     0xfffff000  /* Physical Page Number */
323 
 
324 
/*
325 
 * Bit definitions for Data Cache Control register
326 
 *
327 
 */
328 
#define SPR_DCCR_EW        0x000000ff  /* Enable ways */
329 
 
330 
/*
331 
 * Bit definitions for Insn Cache Control register
332 
 *
333 
 */
334 
#define SPR_ICCR_EW        0x000000ff  /* Enable ways */
335 
 
336 
/*
337 
 * Bit definitions for Data Cache Configuration Register
338 
 *
339 
 */
340 
 
341 
#define SPR_DCCFGR_NCW          0x00000007
342 
#define SPR_DCCFGR_NCS          0x00000078
343 
#define SPR_DCCFGR_CBS          0x00000080
344 
#define SPR_DCCFGR_CWS          0x00000100
345 
#define SPR_DCCFGR_CCRI         0x00000200
346 
#define SPR_DCCFGR_CBIRI        0x00000400
347 
#define SPR_DCCFGR_CBPRI        0x00000800
348 
#define SPR_DCCFGR_CBLRI        0x00001000
349 
#define SPR_DCCFGR_CBFRI        0x00002000
350 
#define SPR_DCCFGR_CBWBRI       0x00004000
351 
 
352 
#define SPR_DCCFGR_NCW_OFF      0
353 
#define SPR_DCCFGR_NCS_OFF      3
354 
#define SPR_DCCFGR_CBS_OFF      7
355 
 
356 
/*
357 
 * Bit definitions for Instruction Cache Configuration Register
358 
 *
359 
 */
360 
#define SPR_ICCFGR_NCW          0x00000007
361 
#define SPR_ICCFGR_NCS          0x00000078
362 
#define SPR_ICCFGR_CBS          0x00000080
363 
#define SPR_ICCFGR_CCRI         0x00000200
364 
#define SPR_ICCFGR_CBIRI        0x00000400
365 
#define SPR_ICCFGR_CBPRI        0x00000800
366 
#define SPR_ICCFGR_CBLRI        0x00001000
367 
 
368 
#define SPR_ICCFGR_NCW_OFF      0
369 
#define SPR_ICCFGR_NCS_OFF      3
370 
#define SPR_ICCFGR_CBS_OFF      7
371 
 
372 
/*
373 
 * Bit definitions for Data MMU Configuration Register
374 
 *
375 
 */
376 
 
377 
#define SPR_DMMUCFGR_NTW        0x00000003
378 
#define SPR_DMMUCFGR_NTS        0x0000001C
379 
#define SPR_DMMUCFGR_NAE        0x000000E0
380 
#define SPR_DMMUCFGR_CRI        0x00000100
381 
#define SPR_DMMUCFGR_PRI        0x00000200
382 
#define SPR_DMMUCFGR_TEIRI      0x00000400
383 
#define SPR_DMMUCFGR_HTR        0x00000800
384 
 
385 
#define SPR_DMMUCFGR_NTW_OFF    0
386 
#define SPR_DMMUCFGR_NTS_OFF    2
387 
 
388 
/*
389 
 * Bit definitions for Instruction MMU Configuration Register
390 
 *
391 
 */
392 
 
393 
#define SPR_IMMUCFGR_NTW        0x00000003
394 
#define SPR_IMMUCFGR_NTS        0x0000001C
395 
#define SPR_IMMUCFGR_NAE        0x000000E0
396 
#define SPR_IMMUCFGR_CRI        0x00000100
397 
#define SPR_IMMUCFGR_PRI        0x00000200
398 
#define SPR_IMMUCFGR_TEIRI      0x00000400
399 
#define SPR_IMMUCFGR_HTR        0x00000800
400 
 
401 
#define SPR_IMMUCFGR_NTW_OFF    0
402 
#define SPR_IMMUCFGR_NTS_OFF    2
403 
 
404 
/*
405 
 * Bit definitions for Debug Control registers
406 
 *
407 
 */
408 
#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
409 
#define SPR_DCR_CC      0x0000000e  /* Compare condition */
410 
#define SPR_DCR_SC      0x00000010  /* Signed compare */
411 
#define SPR_DCR_CT      0x000000e0  /* Compare to */
412 
 
413 
/* Bit results with SPR_DCR_CC mask */
414 
#define SPR_DCR_CC_MASKED 0x00000000
415 
#define SPR_DCR_CC_EQUAL  0x00000002
416 
#define SPR_DCR_CC_LESS   0x00000004
417 
#define SPR_DCR_CC_LESSE  0x00000006
418 
#define SPR_DCR_CC_GREAT  0x00000008
419 
#define SPR_DCR_CC_GREATE 0x0000000a
420 
#define SPR_DCR_CC_NEQUAL 0x0000000c
421 
 
422 
/* Bit results with SPR_DCR_CT mask */
423 
#define SPR_DCR_CT_DISABLED 0x00000000
424 
#define SPR_DCR_CT_IFEA     0x00000020
425 
#define SPR_DCR_CT_LEA      0x00000040
426 
#define SPR_DCR_CT_SEA      0x00000060
427 
#define SPR_DCR_CT_LD       0x00000080
428 
#define SPR_DCR_CT_SD       0x000000a0
429 
#define SPR_DCR_CT_LSEA     0x000000c0
430 
#define SPR_DCR_CT_LSD      0x000000e0
431 
/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
432 
 
433 
/*
434 
 * Bit definitions for Debug Mode 1 register
435 
 *
436 
 */
437 
#define SPR_DMR1_CW       0x000fffff  /* Chain register pair data */
438 
#define SPR_DMR1_CW0_AND  0x00000001
439 
#define SPR_DMR1_CW0_OR   0x00000002
440 
#define SPR_DMR1_CW0      (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
441 
#define SPR_DMR1_CW1_AND  0x00000004
442 
#define SPR_DMR1_CW1_OR   0x00000008
443 
#define SPR_DMR1_CW1      (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
444 
#define SPR_DMR1_CW2_AND  0x00000010
445 
#define SPR_DMR1_CW2_OR   0x00000020
446 
#define SPR_DMR1_CW2      (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
447 
#define SPR_DMR1_CW3_AND  0x00000040
448 
#define SPR_DMR1_CW3_OR   0x00000080
449 
#define SPR_DMR1_CW3      (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
450 
#define SPR_DMR1_CW4_AND  0x00000100
451 
#define SPR_DMR1_CW4_OR   0x00000200
452 
#define SPR_DMR1_CW4      (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
453 
#define SPR_DMR1_CW5_AND  0x00000400
454 
#define SPR_DMR1_CW5_OR   0x00000800
455 
#define SPR_DMR1_CW5      (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
456 
#define SPR_DMR1_CW6_AND  0x00001000
457 
#define SPR_DMR1_CW6_OR   0x00002000
458 
#define SPR_DMR1_CW6      (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
459 
#define SPR_DMR1_CW7_AND  0x00004000
460 
#define SPR_DMR1_CW7_OR   0x00008000
461 
#define SPR_DMR1_CW7      (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
462 
#define SPR_DMR1_CW8_AND  0x00010000
463 
#define SPR_DMR1_CW8_OR   0x00020000
464 
#define SPR_DMR1_CW8      (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
465 
#define SPR_DMR1_CW9_AND  0x00040000
466 
#define SPR_DMR1_CW9_OR   0x00080000
467 
#define SPR_DMR1_CW9      (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
468 
#define SPR_DMR1_RES1      0x00300000  /* Reserved */
469 
#define SPR_DMR1_ST       0x00400000  /* Single-step trace*/
470 
#define SPR_DMR1_BT       0x00800000  /* Branch trace */
471 
#define SPR_DMR1_RES2     0xff000000  /* Reserved */
472 
 
473 
/*
474 
 * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
475 
 *
476 
 */
477 
#define SPR_DMR2_WCE0      0x00000001  /* Watchpoint counter 0 enable */
478 
#define SPR_DMR2_WCE1      0x00000002  /* Watchpoint counter 0 enable */
479 
#define SPR_DMR2_AWTC      0x00000ffc  /* Assign watchpoints to counters */
480 
#define SPR_DMR2_AWTC_OFF           2  /* Bit offset to AWTC field */
481 
#define SPR_DMR2_WGB       0x003ff000  /* Watchpoints generating breakpoint */
482 
#define SPR_DMR2_WGB_OFF           12  /* Bit offset to WGB field */
483 
#define SPR_DMR2_WBS       0xffc00000  /* JPB: Watchpoint status */
484 
#define SPR_DMR2_WBS_OFF           22  /* Bit offset to WBS field */
485 
 
486 
/*
487 
 * Bit definitions for Debug watchpoint counter registers
488 
 *
489 
 */
490 
#define SPR_DWCR_COUNT      0x0000ffff  /* Count */
491 
#define SPR_DWCR_MATCH      0xffff0000  /* Match */
492 
#define SPR_DWCR_MATCH_OFF          16  /* Match bit offset */
493 
 
494 
/*
495 
 * Bit definitions for Debug stop register
496 
 *
497 
 */
498 
#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
499 
#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
500 
#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
501 
#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
502 
#define SPR_DSR_TTE     0x00000010  /* Tick Timer exception */
503 
#define SPR_DSR_AE      0x00000020  /* Alignment exception */
504 
#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
505 
#define SPR_DSR_IE      0x00000080  /* Interrupt exception */
506 
#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
507 
#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
508 
#define SPR_DSR_RE      0x00000400  /* Range exception */
509 
#define SPR_DSR_SCE     0x00000800  /* System call exception */
510 
#define SPR_DSR_FPE     0x00001000  /* Floating Point Exception */
511 
#define SPR_DSR_TE      0x00002000  /* Trap exception */
512 
 
513 
/*
514 
 * Bit definitions for Debug reason register
515 
 *
516 
 */
517 
#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
518 
#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
519 
#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
520 
#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
521 
#define SPR_DRR_TTE     0x00000010  /* Tick Timer exception */
522 
#define SPR_DRR_AE      0x00000020  /* Alignment exception */
523 
#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
524 
#define SPR_DRR_IE      0x00000080  /* Interrupt exception */
525 
#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
526 
#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
527 
#define SPR_DRR_RE      0x00000400  /* Range exception */
528 
#define SPR_DRR_SCE     0x00000800  /* System call exception */
529 
#define SPR_DRR_FPE     0x00001000  /* Floating Point Exception */
530 
#define SPR_DRR_TE      0x00002000  /* Trap exception */
531 
 
532 
/*
533 
 * Bit definitions for Performance counters mode registers
534 
 *
535 
 */
536 
#define SPR_PCMR_CP     0x00000001  /* Counter present */
537 
#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
538 
#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
539 
#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
540 
#define SPR_PCMR_LA     0x00000010  /* Load access event */
541 
#define SPR_PCMR_SA     0x00000020  /* Store access event */
542 
#define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/
543 
#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
544 
#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
545 
#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
546 
#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
547 
#define SPR_PCMR_BS     0x00000800  /* Branch stall event */
548 
#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
549 
#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
550 
#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
551 
#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
552 
 
553 
/*
554 
 * Bit definitions for the Power management register
555 
 *
556 
 */
557 
#define SPR_PMR_SDF     0x0000000f  /* Slow down factor */
558 
#define SPR_PMR_DME     0x00000010  /* Doze mode enable */
559 
#define SPR_PMR_SME     0x00000020  /* Sleep mode enable */
560 
#define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
561 
#define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
562 
 
563 
/*
564 
 * Bit definitions for PICMR
565 
 *
566 
 */
567 
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
568 
 
569 
/*
570 
 * Bit definitions for PICPR
571 
 *
572 
 */
573 
#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
574 
 
575 
/*
576 
 * Bit definitions for PICSR
577 
 *
578 
 */
579 
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
580 
 
581 
/*
582 
 * Bit definitions for Tick Timer Control Register
583 
 *
584 
 */
585 
#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
586 
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
587 
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
588 
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
589 
#define SPR_TTMR_RT     0x40000000  /* Restart tick */
590 
#define SPR_TTMR_SR     0x80000000  /* Single run */
591 
#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
592 
#define SPR_TTMR_M      0xc0000000  /* Tick mode */
593 
 
594 
/*
595 
 * l.nop constants
596 
 *
597 
 */
598 82 jeremybenn 
#define NOP_NOP          0x0000      /* Normal nop instruction */
599 
#define NOP_EXIT         0x0001      /* End of simulation */
600 
#define NOP_REPORT       0x0002      /* Simple report */
601 
/*#define NOP_PRINTF       0x0003       Simprintf instruction (obsolete)*/
602 
#define NOP_PUTC         0x0004      /* JPB: Simputc instruction */
603 
#define NOP_CNT_RESET    0x0005      /* Reset statistics counters */
604 
#define NOP_GET_TICKS    0x0006      /* JPB: Get # ticks running */
605 
#define NOP_GET_PS       0x0007      /* JPB: Get picosecs/cycle */
606 
#define NOP_REPORT_FIRST 0x0400      /* Report with number */
607 
#define NOP_REPORT_LAST  0x03ff      /* Report with number */
608 19 jeremybenn 
 
609 
#endif  /* SPR_DEFS__H */

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