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jeremybenn |
/* sprs.c -- Simulation of OR1K special-purpose registers
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "port.h"
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/* System includes */
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#include <stdlib.h>
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#include <stdio.h>
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#include <errno.h>
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/* Package includes */
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#include "sprs.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "execute.h"
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#include "spr-defs.h"
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#include "tick.h"
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#include "dcache-model.h"
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#include "icache-model.h"
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#include "dmmu.h"
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#include "immu.h"
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#include "toplevel-support.h"
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#include "pic.h"
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DECLARE_DEBUG_CHANNEL(immu);
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/* Set a specific SPR with a value. */
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void mtspr(uint16_t regno, const uorreg_t value)
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{
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uorreg_t prev_val;
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prev_val = cpu_state.sprs[regno];
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cpu_state.sprs[regno] = value;
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/* MM: Register hooks. */
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switch (regno) {
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case SPR_TTCR:
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spr_write_ttcr (value);
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break;
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case SPR_TTMR:
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spr_write_ttmr (prev_val);
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break;
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/* Data cache simulateing stuff */
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case SPR_DCBPR:
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/* FIXME: This is not correct. The arch. manual states: "Memory accesses
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* are not recorded (Unlike load or store instructions) and cannot invoke
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* any exception". If the physical address is invalid a bus error will be
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* generated. Also if the effective address is not resident in the mmu
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* the read will happen from address 0, which is naturally not correct. */
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dc_simulate_read(peek_into_dtlb(value, 0, 1), value, 4);
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cpu_state.sprs[SPR_DCBPR] = 0;
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break;
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case SPR_DCBFR:
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dc_inv(value);
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cpu_state.sprs[SPR_DCBFR] = -1;
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break;
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case SPR_DCBIR:
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dc_inv(value);
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cpu_state.sprs[SPR_DCBIR] = 0;
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break;
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case SPR_DCBWR:
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cpu_state.sprs[SPR_DCBWR] = 0;
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break;
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case SPR_DCBLR:
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cpu_state.sprs[SPR_DCBLR] = 0;
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break;
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/* Instruction cache simulateing stuff */
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case SPR_ICBPR:
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/* FIXME: The arch manual does not say what happens when an invalid memory
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* location is specified. I guess the same as for the DCBPR register */
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ic_simulate_fetch(peek_into_itlb(value), value);
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cpu_state.sprs[SPR_ICBPR] = 0;
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break;
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case SPR_ICBIR:
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ic_inv(value);
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cpu_state.sprs[SPR_ICBIR] = 0;
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break;
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case SPR_ICBLR:
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cpu_state.sprs[SPR_ICBLR] = 0;
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break;
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case SPR_SR:
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cpu_state.sprs[regno] |= SPR_SR_FO;
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if((value & SPR_SR_IEE) && !(prev_val & SPR_SR_IEE))
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pic_ints_en();
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#if DYNAMIC_EXECUTION
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if((value & SPR_SR_IME) && !(prev_val & SPR_SR_IME)) {
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TRACE_(immu)("IMMU just became enabled (%lli).\n", runtime.sim.cycles);
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recheck_immu(IMMU_GOT_ENABLED);
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} else if(!(value & SPR_SR_IME) && (prev_val & SPR_SR_IME)) {
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TRACE_(immu)("Remove counting of mmu hit delay with cycles (%lli)\n",
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runtime.sim.cycles);
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recheck_immu(IMMU_GOT_DISABLED);
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}
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#endif
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break;
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case SPR_NPC:
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{
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/* The debugger has redirected us to a new address */
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/* This is usually done to reissue an instruction
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which just caused a breakpoint exception. */
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/* JPB patch. When GDB stepi, this may be used to set the PC to the
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value it is already at. If this is the case, then we do nothing (in
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particular we do not trash a delayed branch) */
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if (value != cpu_state.pc)
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{
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cpu_state.pc = value;
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if(!value && config.sim.verbose)
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PRINTF("WARNING: PC just set to 0!\n");
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/* Clear any pending delay slot jumps also */
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cpu_state.delay_insn = 0;
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pcnext = value + 4;
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/* Further JPB patch. If the processor is stalled, then subsequent
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reads of the NPC should return 0 until the processor is
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unstalled. If the processor is stalled, note that the NPC has
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been updated while the processor was stalled. */
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if (runtime.cpu.stalled)
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{
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cpu_state.npc_not_valid = 1;
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}
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}
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}
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break;
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case SPR_PICSR:
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if(!config.pic.edge_trigger)
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cpu_state.sprs[SPR_PICSR] = prev_val;
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break;
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case SPR_PICMR:
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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pic_ints_en();
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break;
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case SPR_PMR:
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/* PMR[SDF] and PMR[DCGE] are ignored completely. */
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if (config.pm.enabled && (value & SPR_PMR_SUME)) {
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PRINTF ("SUSPEND: PMR[SUME] bit was set.\n");
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sim_done();
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}
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break;
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default:
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/* Mask reserved bits in DTLBMR and DTLBMR registers */
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if ( (regno >= SPR_DTLBMR_BASE(0)) && (regno < SPR_DTLBTR_LAST(3))) {
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if((regno & 0xff) < 0x80)
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cpu_state.sprs[regno] = DADDR_PAGE(value) |
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(value & (SPR_DTLBMR_V | SPR_DTLBMR_PL1 | SPR_DTLBMR_CID | SPR_DTLBMR_LRU));
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else
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cpu_state.sprs[regno] = DADDR_PAGE(value) |
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(value & (SPR_DTLBTR_CC | SPR_DTLBTR_CI | SPR_DTLBTR_WBC | SPR_DTLBTR_WOM |
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SPR_DTLBTR_A | SPR_DTLBTR_D | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE |
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SPR_DTLBTR_SWE));
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}
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/* Mask reseved bits in ITLBMR and ITLBMR registers */
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if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) {
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if((regno & 0xff) < 0x80)
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cpu_state.sprs[regno] = IADDR_PAGE(value) |
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(value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU));
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else
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cpu_state.sprs[regno] = IADDR_PAGE(value) |
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(value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM |
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SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE));
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#if DYNAMIC_EXECUTION
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IME) {
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/* The immu got reconfigured. Recheck if the current page in execution
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* is resident in the immu ways. This check would be done during the
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* instruction fetch but since the dynamic execution model does not do
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* instruction fetchs, do it now. */
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recheck_immu(0);
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}
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#endif
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}
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/* Links to GPRS */
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if(regno >= 0x0400 && regno < 0x0420) {
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cpu_state.reg[regno - 0x0400] = value;
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}
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break;
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}
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}
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/* Get a specific SPR. */
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uorreg_t mfspr(const uint16_t regno)
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{
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uorreg_t ret;
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ret = cpu_state.sprs[regno];
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switch (regno) {
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case SPR_NPC:
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/* The NPC is the program counter UNLESS the NPC has been changed and we
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are stalled, which will have flushed the pipeline, so the value is
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zero. Currently this is optional behavior, since it breaks GDB.
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*/
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if (config.sim.strict_npc && cpu_state.npc_not_valid)
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{
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ret = 0;
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}
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else
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{
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ret = cpu_state.pc;
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}
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break;
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case SPR_TTCR:
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ret = spr_read_ttcr();
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break;
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226 |
julius |
case SPR_FPCSR:
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// If hard floating point is disabled - return 0
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if (!config.cpu.hardfloat)
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ret = 0;
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break;
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19 |
jeremybenn |
default:
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/* Links to GPRS */
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if(regno >= 0x0400 && regno < 0x0420)
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ret = cpu_state.reg[regno - 0x0400];
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}
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return ret;
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}
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/* Show status of important SPRs. */
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void sprs_status(void)
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{
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PRINTF("VR : 0x%"PRIxREG" UPR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_VR],
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cpu_state.sprs[SPR_UPR]);
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PRINTF("SR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_SR]);
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PRINTF("MACLO: 0x%"PRIxREG" MACHI: 0x%"PRIxREG"\n",
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cpu_state.sprs[SPR_MACLO], cpu_state.sprs[SPR_MACHI]);
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PRINTF("EPCR0: 0x%"PRIxADDR" EPCR1: 0x%"PRIxADDR"\n",
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cpu_state.sprs[SPR_EPCR_BASE], cpu_state.sprs[SPR_EPCR_BASE+1]);
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PRINTF("EEAR0: 0x%"PRIxADDR" EEAR1: 0x%"PRIxADDR"\n",
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cpu_state.sprs[SPR_EEAR_BASE], cpu_state.sprs[SPR_EEAR_BASE+1]);
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PRINTF("ESR0 : 0x%"PRIxREG" ESR1 : 0x%"PRIxREG"\n",
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cpu_state.sprs[SPR_ESR_BASE], cpu_state.sprs[SPR_ESR_BASE+1]);
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PRINTF("TTMR : 0x%"PRIxREG" TTCR : 0x%"PRIxREG"\n",
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cpu_state.sprs[SPR_TTMR], cpu_state.sprs[SPR_TTCR]);
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PRINTF("PICMR: 0x%"PRIxREG" PICSR: 0x%"PRIxREG"\n",
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cpu_state.sprs[SPR_PICMR], cpu_state.sprs[SPR_PICSR]);
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PRINTF("PPC: 0x%"PRIxADDR" NPC : 0x%"PRIxADDR"\n",
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cpu_state.sprs[SPR_PPC], cpu_state.sprs[SPR_NPC]);
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}
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