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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 100

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Line No. Rev Author Line
1 19 jeremybenn 
/* insnset.c -- Instruction specific functions.
2 
 
3 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4 
                 2000-2002 Marko Mlinar, markom@opencores.org
5 
   Copyright (C) 2008 Embecosm Limited
6 100 julius 
   Copyright (C) 2009 Jungsook yang, jungsook.yang@uci.edu
7 19 jeremybenn 
 
8 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
9 100 julius 
   Contributor Julius Baxter julius@orsoc.se
10 
 
11 19 jeremybenn 
   This file is part of OpenRISC 1000 Architectural Simulator.
12 
 
13 
   This program is free software; you can redistribute it and/or modify it
14 
   under the terms of the GNU General Public License as published by the Free
15 
   Software Foundation; either version 3 of the License, or (at your option)
16 
   any later version.
17 
 
18 
   This program is distributed in the hope that it will be useful, but WITHOUT
19 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
21 
   more details.
22 
 
23 
   You should have received a copy of the GNU General Public License along
24 
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
25 
 
26 
/* This program is commented throughout in a fashion suitable for processing
27 
   with Doxygen. */
28 
 
29 
 
30 
INSTRUCTION (l_add) {
31 
  orreg_t temp1, temp2, temp3;
32 
  int8_t temp4;
33 
 
34 
  temp2 = (orreg_t)PARAM2;
35 
  temp3 = (orreg_t)PARAM1;
36 
  temp1 = temp2 + temp3;
37 
  SET_PARAM0(temp1);
38 
  SET_OV_FLAG_FN (temp1);
39 
  if (ARITH_SET_FLAG) {
40 
    if(!temp1)
41 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
42 
    else
43 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
44 
  }
45 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
46 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
47 
  else
48 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
49 
 
50 
  temp4 = temp1;
51 
  if (temp4 == temp1)
52 
    or1k_mstats.byteadd++;
53 
}
54 
INSTRUCTION (l_addc) {
55 
  orreg_t temp1, temp2, temp3;
56 
  int8_t temp4;
57 
 
58 
  temp2 = (orreg_t)PARAM2;
59 
  temp3 = (orreg_t)PARAM1;
60 
  temp1 = temp2 + temp3;
61 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
62 
    temp1++;
63 
  SET_PARAM0(temp1);
64 
  SET_OV_FLAG_FN (temp1);
65 
  if (ARITH_SET_FLAG) {
66 
    if(!temp1)
67 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
68 
    else
69 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
70 
  }
71 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
72 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
73 
  else
74 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
75 
 
76 
  temp4 = temp1;
77 
  if (temp4 == temp1)
78 
    or1k_mstats.byteadd++;
79 
}
80 
INSTRUCTION (l_sw) {
81 
  int old_cyc = 0;
82 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
83 
  set_mem32(PARAM0, PARAM1, &breakpoint);
84 
  if (config.cpu.sbuf_len) {
85 
    int t = runtime.sim.mem_cycles;
86 
    runtime.sim.mem_cycles = old_cyc;
87 
    sbuf_store (t - old_cyc);
88 
  }
89 
}
90 
INSTRUCTION (l_sb) {
91 
  int old_cyc = 0;
92 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
93 
  set_mem8(PARAM0, PARAM1, &breakpoint);
94 
  if (config.cpu.sbuf_len) {
95 
    int t = runtime.sim.mem_cycles;
96 
    runtime.sim.mem_cycles = old_cyc;
97 
    sbuf_store (t- old_cyc);
98 
  }
99 
}
100 
INSTRUCTION (l_sh) {
101 
  int old_cyc = 0;
102 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
103 
  set_mem16(PARAM0, PARAM1, &breakpoint);
104 
  if (config.cpu.sbuf_len) {
105 
    int t = runtime.sim.mem_cycles;
106 
    runtime.sim.mem_cycles = old_cyc;
107 
    sbuf_store (t - old_cyc);
108 
  }
109 
}
110 
INSTRUCTION (l_lwz) {
111 
  uint32_t val;
112 
  if (config.cpu.sbuf_len) sbuf_load ();
113 
  val = eval_mem32(PARAM1, &breakpoint);
114 
  /* If eval operand produced exception don't set anything. JPB changed to
115 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
116 
  if (!(except_pending || breakpoint))
117 
    SET_PARAM0(val);
118 
}
119 
INSTRUCTION (l_lbs) {
120 
  int8_t val;
121 
  if (config.cpu.sbuf_len) sbuf_load ();
122 
  val = eval_mem8(PARAM1, &breakpoint);
123 
  /* If eval operand produced exception don't set anything. JPB changed to
124 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
125 
  if (!(except_pending || breakpoint))
126 
    SET_PARAM0(val);
127 
}
128 
INSTRUCTION (l_lbz) {
129 
  uint8_t val;
130 
  if (config.cpu.sbuf_len) sbuf_load ();
131 
  val = eval_mem8(PARAM1, &breakpoint);
132 
  /* If eval operand produced exception don't set anything. JPB changed to
133 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
134 
  if (!(except_pending || breakpoint))
135 
    SET_PARAM0(val);
136 
}
137 
INSTRUCTION (l_lhs) {
138 
  int16_t val;
139 
  if (config.cpu.sbuf_len) sbuf_load ();
140 
  val = eval_mem16(PARAM1, &breakpoint);
141 
  /* If eval operand produced exception don't set anything. JPB changed to
142 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
143 
  if (!(except_pending || breakpoint))
144 
    SET_PARAM0(val);
145 
}
146 
INSTRUCTION (l_lhz) {
147 
  uint16_t val;
148 
  if (config.cpu.sbuf_len) sbuf_load ();
149 
  val = eval_mem16(PARAM1, &breakpoint);
150 
  /* If eval operand produced exception don't set anything. JPB changed to
151 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
152 
  if (!(except_pending || breakpoint))
153 
    SET_PARAM0(val);
154 
}
155 
INSTRUCTION (l_movhi) {
156 
  SET_PARAM0(PARAM1 << 16);
157 
}
158 
INSTRUCTION (l_and) {
159 
  uorreg_t temp1;
160 
  temp1 = PARAM1 & PARAM2;
161 
  SET_OV_FLAG_FN (temp1);
162 
  SET_PARAM0(temp1);
163 
  if (ARITH_SET_FLAG) {
164 
    if(!temp1)
165 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
166 
    else
167 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
168 
  }
169 
}
170 
INSTRUCTION (l_or) {
171 
  uorreg_t temp1;
172 
  temp1 = PARAM1 | PARAM2;
173 
  SET_OV_FLAG_FN (temp1);
174 
  SET_PARAM0(temp1);
175 
}
176 
INSTRUCTION (l_xor) {
177 
  uorreg_t temp1;
178 
  temp1 = PARAM1 ^ PARAM2;
179 
  SET_OV_FLAG_FN (temp1);
180 
  SET_PARAM0(temp1);
181 
}
182 
INSTRUCTION (l_sub) {
183 
  orreg_t temp1;
184 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
185 
  SET_OV_FLAG_FN (temp1);
186 
  SET_PARAM0(temp1);
187 
}
188 
/*int mcount = 0;*/
189 
INSTRUCTION (l_mul) {
190 
  orreg_t temp1;
191 
 
192 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
193 
  SET_OV_FLAG_FN (temp1);
194 
  SET_PARAM0(temp1);
195 
  /*if (!(mcount++ & 1023)) {
196 
    PRINTF ("[%i]\n",mcount);
197 
    }*/
198 
}
199 
INSTRUCTION (l_div) {
200 
  orreg_t temp3, temp2, temp1;
201 
 
202 
  temp3 = PARAM2;
203 
  temp2 = PARAM1;
204 
  if (temp3)
205 
    temp1 = temp2 / temp3;
206 
  else {
207 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
208 
    return;
209 
  }
210 
  SET_OV_FLAG_FN (temp1);
211 
  SET_PARAM0(temp1);
212 
}
213 
INSTRUCTION (l_divu) {
214 
  uorreg_t temp3, temp2, temp1;
215 
 
216 
  temp3 = PARAM2;
217 
  temp2 = PARAM1;
218 
  if (temp3)
219 
    temp1 = temp2 / temp3;
220 
  else {
221 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
222 
    return;
223 
  }
224 
  SET_OV_FLAG_FN (temp1);
225 
  SET_PARAM0(temp1);
226 
  /* runtime.sim.cycles += 16; */
227 
}
228 
INSTRUCTION (l_sll) {
229 
  uorreg_t temp1;
230 
 
231 
  temp1 = PARAM1 << PARAM2;
232 
  SET_OV_FLAG_FN (temp1);
233 
  SET_PARAM0(temp1);
234 
  /* runtime.sim.cycles += 2; */
235 
}
236 
INSTRUCTION (l_sra) {
237 
  orreg_t temp1;
238 
 
239 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
240 
  SET_OV_FLAG_FN (temp1);
241 
  SET_PARAM0(temp1);
242 
  /* runtime.sim.cycles += 2; */
243 
}
244 
INSTRUCTION (l_srl) {
245 
  uorreg_t temp1;
246 
  temp1 = PARAM1 >> PARAM2;
247 
  SET_OV_FLAG_FN (temp1);
248 
  SET_PARAM0(temp1);
249 
  /* runtime.sim.cycles += 2; */
250 
}
251 
INSTRUCTION (l_bf) {
252 
  if (config.bpb.enabled) {
253 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
254 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
255 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
256 
  }
257 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
258 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
259 
    btic_update(pcnext);
260 
    next_delay_insn = 1;
261 
  } else {
262 
    btic_update(cpu_state.pc);
263 
  }
264 
}
265 
INSTRUCTION (l_bnf) {
266 
  if (config.bpb.enabled) {
267 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
268 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
269 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
270 
  }
271 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
272 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
273 
    btic_update(pcnext);
274 
    next_delay_insn = 1;
275 
  } else {
276 
    btic_update(cpu_state.pc);
277 
  }
278 
}
279 
INSTRUCTION (l_j) {
280 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
281 
  next_delay_insn = 1;
282 
}
283 
INSTRUCTION (l_jal) {
284 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
285 
 
286 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
287 
  next_delay_insn = 1;
288 
  if (config.sim.profile) {
289 
    struct label_entry *tmp;
290 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
291 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
292 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
293 
               tmp->name);
294 
    else
295 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
296 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
297 
               cpu_state.pc_delay);
298 
  }
299 
}
300 
INSTRUCTION (l_jalr) {
301 
  cpu_state.pc_delay = PARAM0;
302 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
303 
  next_delay_insn = 1;
304 
}
305 
INSTRUCTION (l_jr) {
306 
  cpu_state.pc_delay = PARAM0;
307 
  next_delay_insn = 1;
308 
  if (config.sim.profile)
309 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
310 
             cpu_state.pc_delay);
311 
}
312 
INSTRUCTION (l_rfe) {
313 
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
314 
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
315 
}
316 
INSTRUCTION (l_nop) {
317 
  uint32_t k = PARAM0;
318 
  switch (k) {
319 
    case NOP_NOP:
320 
      break;
321 
    case NOP_EXIT:
322 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
323 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
324 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
325 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
326 
              runtime.cpu.instructions);
327 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
328 
              runtime.sim.cycles - runtime.sim.reset_cycles,
329 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
330 
      if (config.debug.gdb_enabled)
331 
        set_stall_state (1);
332 
      else
333 
        sim_done();
334 
      break;
335 
    case NOP_CNT_RESET:
336 
      PRINTF("****************** counters reset ******************\n");
337 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
338 
      PRINTF("****************** counters reset ******************\n");
339 
      runtime.sim.reset_cycles = runtime.sim.cycles;
340 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
341 
      break;
342 
    case NOP_PUTC:              /*JPB */
343 
      printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
344 
      fflush( stdout );
345 
      break;
346 82 jeremybenn 
    case NOP_GET_TICKS:
347 
      cpu_state.reg[11] = runtime.sim.cycles & 0xffffffff;
348 
      cpu_state.reg[12] = runtime.sim.cycles >> 32;
349 
      break;
350 
    case NOP_GET_PS:
351 
      cpu_state.reg[11] = config.sim.clkcycle_ps;
352 
      break;
353 19 jeremybenn 
    case NOP_REPORT:
354 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
355 
    default:
356 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
357 
      PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
358 
             evalsim_reg(3));
359 
      break;
360 
  }
361 
}
362 
INSTRUCTION (l_sfeq) {
363 
  if(PARAM0 == PARAM1)
364 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
365 
  else
366 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
367 
}
368 
INSTRUCTION (l_sfne) {
369 
  if(PARAM0 != PARAM1)
370 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
371 
  else
372 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
373 
}
374 
INSTRUCTION (l_sfgts) {
375 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
376 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
377 
  else
378 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
379 
}
380 
INSTRUCTION (l_sfges) {
381 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
382 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
383 
  else
384 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
385 
}
386 
INSTRUCTION (l_sflts) {
387 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
388 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
389 
  else
390 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
391 
}
392 
INSTRUCTION (l_sfles) {
393 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
394 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
395 
  else
396 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
397 
}
398 
INSTRUCTION (l_sfgtu) {
399 
  if(PARAM0 > PARAM1)
400 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
401 
  else
402 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
403 
}
404 
INSTRUCTION (l_sfgeu) {
405 
  if(PARAM0 >= PARAM1)
406 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
407 
  else
408 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
409 
}
410 
INSTRUCTION (l_sfltu) {
411 
  if(PARAM0 < PARAM1)
412 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
413 
  else
414 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
415 
}
416 
INSTRUCTION (l_sfleu) {
417 
  if(PARAM0 <= PARAM1)
418 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
419 
  else
420 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
421 
}
422 
INSTRUCTION (l_extbs) {
423 
  int8_t x;
424 
  x = PARAM1;
425 
  SET_PARAM0((orreg_t)x);
426 
}
427 
INSTRUCTION (l_extbz) {
428 
  uint8_t x;
429 
  x = PARAM1;
430 
  SET_PARAM0((uorreg_t)x);
431 
}
432 
INSTRUCTION (l_exths) {
433 
  int16_t x;
434 
  x = PARAM1;
435 
  SET_PARAM0((orreg_t)x);
436 
}
437 
INSTRUCTION (l_exthz) {
438 
  uint16_t x;
439 
  x = PARAM1;
440 
  SET_PARAM0((uorreg_t)x);
441 
}
442 
INSTRUCTION (l_extws) {
443 
  int32_t x;
444 
  x = PARAM1;
445 
  SET_PARAM0((orreg_t)x);
446 
}
447 
INSTRUCTION (l_extwz) {
448 
  uint32_t x;
449 
  x = PARAM1;
450 
  SET_PARAM0((uorreg_t)x);
451 
}
452 
INSTRUCTION (l_mtspr) {
453 
  uint16_t regno = PARAM0 + PARAM2;
454 
  uorreg_t value = PARAM1;
455 
 
456 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
457 
    mtspr(regno, value);
458 
  else {
459 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
460 
    sim_done();
461 
  }
462 
}
463 
INSTRUCTION (l_mfspr) {
464 
  uint16_t regno = PARAM1 + PARAM2;
465 
  uorreg_t value = mfspr(regno);
466 
 
467 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
468 
    SET_PARAM0(value);
469 
  else {
470 
    SET_PARAM0(0);
471 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
472 
    sim_done();
473 
  }
474 
}
475 
INSTRUCTION (l_sys) {
476 
  except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
477 
}
478 
INSTRUCTION (l_trap) {
479 
  /* TODO: some SR related code here! */
480 
  except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
481 
}
482 
INSTRUCTION (l_mac) {
483 
  uorreg_t lo, hi;
484 
  LONGEST l;
485 
  orreg_t x, y;
486 
 
487 
  lo = cpu_state.sprs[SPR_MACLO];
488 
  hi = cpu_state.sprs[SPR_MACHI];
489 
  x = PARAM0;
490 
  y = PARAM1;
491 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
492 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
493 
  l += (LONGEST) x * (LONGEST) y;
494 
 
495 
  /* This implementation is very fast - it needs only one cycle for mac.  */
496 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
497 
  hi = ((LONGEST)l) >> 32;
498 
  cpu_state.sprs[SPR_MACLO] = lo;
499 
  cpu_state.sprs[SPR_MACHI] = hi;
500 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo); */
501 
}
502 
INSTRUCTION (l_msb) {
503 
  uorreg_t lo, hi;
504 
  LONGEST l;
505 
  orreg_t x, y;
506 
 
507 
  lo = cpu_state.sprs[SPR_MACLO];
508 
  hi = cpu_state.sprs[SPR_MACHI];
509 
  x = PARAM0;
510 
  y = PARAM1;
511 
 
512 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
513 
 
514 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
515 
  l -= x * y;
516 
 
517 
  /* This implementation is very fast - it needs only one cycle for msb.  */
518 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
519 
  hi = ((LONGEST)l) >> 32;
520 
  cpu_state.sprs[SPR_MACLO] = lo;
521 
  cpu_state.sprs[SPR_MACHI] = hi;
522 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
523 
}
524 
INSTRUCTION (l_macrc) {
525 
  uorreg_t lo, hi;
526 
  LONGEST l;
527 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
528 
  lo =  cpu_state.sprs[SPR_MACLO];
529 
  hi =  cpu_state.sprs[SPR_MACHI];
530 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
531 
  l >>= 28;
532 
  //PRINTF ("<%08x>\n", (unsigned long)l);
533 
  SET_PARAM0((orreg_t)l);
534 
  cpu_state.sprs[SPR_MACLO] = 0;
535 
  cpu_state.sprs[SPR_MACHI] = 0;
536 
}
537 
INSTRUCTION (l_cmov) {
538 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
539 
}
540 
INSTRUCTION (l_ff1) {
541 
  SET_PARAM0(ffs(PARAM1));
542 
}
543 
/******* Floating point instructions *******/
544 
/* Single precision */
545 
INSTRUCTION (lf_add_s) {
546 100 julius 
  if (config.cpu.hardfloat) {
547 
  FLOAT param0, param1, param2;
548 
  param1.hval = (uorreg_t)PARAM1;
549 
  param2.hval = (uorreg_t)PARAM2;
550 
  param0.fval = param1.fval + param2.fval;
551 
  SET_PARAM0(param0.hval);
552 
  } else l_invalid();
553 19 jeremybenn 
}
554 
INSTRUCTION (lf_div_s) {
555 100 julius 
  if (config.cpu.hardfloat) {
556 
  FLOAT param0, param1, param2;
557 
  param1.hval = (uorreg_t)PARAM1;
558 
  param2.hval = (uorreg_t)PARAM2;
559 
  param0.fval = param1.fval / param2.fval;
560 
  SET_PARAM0(param0.hval);
561 
  } else l_invalid();
562 19 jeremybenn 
}
563 
INSTRUCTION (lf_ftoi_s) {
564 100 julius 
  if (config.cpu.hardfloat) {
565 
    // no other way appeared to work --jb
566 
    float tmp_f; memcpy((void*)&tmp_f, (void*)&PARAM1, sizeof(float));
567 
    SET_PARAM0((int)tmp_f);
568 
  } else l_invalid();
569 19 jeremybenn 
}
570 
INSTRUCTION (lf_itof_s) {
571 100 julius 
  if (config.cpu.hardfloat) {
572 
  FLOAT param0;
573 
  param0.fval = (float)((int)PARAM1);
574 
  SET_PARAM0(param0.hval);
575 
  } else l_invalid();
576 19 jeremybenn 
}
577 
INSTRUCTION (lf_madd_s) {
578 100 julius 
  if (config.cpu.hardfloat) {
579 
  FLOAT param0,param1, param2;
580 
  param0.hval = PARAM0;
581 
  param1.hval = PARAM1;
582 
  param2.hval = PARAM2;
583 
  param0.fval += param1.fval * param2.fval;
584 
  SET_PARAM0(param0.hval);
585 
  } else l_invalid();
586 19 jeremybenn 
}
587 
INSTRUCTION (lf_mul_s) {
588 100 julius 
  if (config.cpu.hardfloat) {
589 
  FLOAT param0, param1, param2;
590 
  param1.hval = (uorreg_t)PARAM1;
591 
  param2.hval = (uorreg_t)PARAM2;
592 
  param0.fval = param1.fval * param2.fval;
593 
  SET_PARAM0(param0.hval);
594 
  } else l_invalid();
595 19 jeremybenn 
}
596 
INSTRUCTION (lf_rem_s) {
597 100 julius 
  if (config.cpu.hardfloat) {
598 
  FLOAT param0, param1, param2;
599 
  param1.hval = PARAM1;
600 
  param2.hval = PARAM2;
601 
  param0.fval = param1.fval / param2.fval;
602 
  SET_PARAM0(param0.hval);
603 
  } else l_invalid();
604 19 jeremybenn 
}
605 
INSTRUCTION (lf_sfeq_s) {
606 100 julius 
  if (config.cpu.hardfloat) {
607 
  FLOAT param0, param1;
608 
  param0.hval = PARAM0;
609 
  param1.hval = PARAM1;
610 
  if(param0.fval == param1.fval)
611 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
612 
  else
613 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
614 100 julius 
  } else l_invalid();
615 19 jeremybenn 
}
616 
INSTRUCTION (lf_sfge_s) {
617 100 julius 
  if (config.cpu.hardfloat) {
618 
  FLOAT param0, param1;
619 
  param0.hval = PARAM0;
620 
  param1.hval = PARAM1;
621 
  if(param0.fval >= param1.fval)
622 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
623 
  else
624 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
625 100 julius 
  } else l_invalid();
626 19 jeremybenn 
}
627 
INSTRUCTION (lf_sfgt_s) {
628 100 julius 
  if (config.cpu.hardfloat) {
629 
  FLOAT param0, param1;
630 
  param0.hval = PARAM0;
631 
  param1.hval = PARAM1;
632 
  if(param0.fval > param1.fval)
633 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
634 
  else
635 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
636 100 julius 
  } else l_invalid();
637 19 jeremybenn 
}
638 
INSTRUCTION (lf_sfle_s) {
639 100 julius 
  if (config.cpu.hardfloat) {
640 
  FLOAT param0, param1;
641 
  param0.hval = PARAM0;
642 
  param1.hval = PARAM1;
643 
  if(param0.fval <= param1.fval)
644 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
645 
  else
646 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
647 100 julius 
  } else l_invalid();
648 19 jeremybenn 
}
649 
INSTRUCTION (lf_sflt_s) {
650 100 julius 
  if (config.cpu.hardfloat) {
651 
  FLOAT param0, param1;
652 
  param0.hval = PARAM0;
653 
  param1.hval = PARAM1;
654 
  if(param0.fval < param1.fval)
655 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
656 
  else
657 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
658 100 julius 
  } else l_invalid();
659 19 jeremybenn 
}
660 
INSTRUCTION (lf_sfne_s) {
661 100 julius 
  if (config.cpu.hardfloat) {
662 
  FLOAT param0, param1;
663 
  param0.hval = PARAM0;
664 
  param1.hval = PARAM1;
665 
  if(param0.fval != param1.fval)
666 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
667 
  else
668 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
669 100 julius 
  } else l_invalid();
670 19 jeremybenn 
}
671 
INSTRUCTION (lf_sub_s) {
672 100 julius 
  if (config.cpu.hardfloat) {
673 
  FLOAT param0, param1, param2;
674 
  param1.hval = PARAM1;
675 
  param2.hval = PARAM2;
676 
  param0.fval = param1.fval - param2.fval;
677 
  SET_PARAM0(param0.hval);
678 
  } else l_invalid();
679 19 jeremybenn 
}
680 
 
681 
/******* Custom instructions *******/
682 
INSTRUCTION (l_cust1) {
683 
  /*int destr = current->insn >> 21;
684 
    int src1r = current->insn >> 15;
685 
    int src2r = current->insn >> 9;*/
686 
}
687 
INSTRUCTION (l_cust2) {
688 
}
689 
INSTRUCTION (l_cust3) {
690 
}
691 
INSTRUCTION (l_cust4) {
692 
}
693 100 julius 
INSTRUCTION (lf_cust1) {
694 
}
695 
INSTRUCTION (lf_cust2) {
696 
}
697 
INSTRUCTION (lf_cust3) {
698 
}
699 
INSTRUCTION (lf_cust4) {
700 
}

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