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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 107

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Line No. Rev Author Line
1 19 jeremybenn 
/* insnset.c -- Instruction specific functions.
2 
 
3 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4 
                 2000-2002 Marko Mlinar, markom@opencores.org
5 
   Copyright (C) 2008 Embecosm Limited
6 100 julius 
   Copyright (C) 2009 Jungsook yang, jungsook.yang@uci.edu
7 19 jeremybenn 
 
8 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
9 100 julius 
   Contributor Julius Baxter julius@orsoc.se
10 
 
11 19 jeremybenn 
   This file is part of OpenRISC 1000 Architectural Simulator.
12 
 
13 
   This program is free software; you can redistribute it and/or modify it
14 
   under the terms of the GNU General Public License as published by the Free
15 
   Software Foundation; either version 3 of the License, or (at your option)
16 
   any later version.
17 
 
18 
   This program is distributed in the hope that it will be useful, but WITHOUT
19 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
21 
   more details.
22 
 
23 
   You should have received a copy of the GNU General Public License along
24 
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
25 
 
26 
/* This program is commented throughout in a fashion suitable for processing
27 
   with Doxygen. */
28 
 
29 
 
30 
INSTRUCTION (l_add) {
31 
  orreg_t temp1, temp2, temp3;
32 
  int8_t temp4;
33 
 
34 
  temp2 = (orreg_t)PARAM2;
35 
  temp3 = (orreg_t)PARAM1;
36 
  temp1 = temp2 + temp3;
37 
  SET_PARAM0(temp1);
38 
  SET_OV_FLAG_FN (temp1);
39 
  if (ARITH_SET_FLAG) {
40 
    if(!temp1)
41 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
42 
    else
43 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
44 
  }
45 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
46 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
47 
  else
48 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
49 
 
50 
  temp4 = temp1;
51 
  if (temp4 == temp1)
52 
    or1k_mstats.byteadd++;
53 
}
54 
INSTRUCTION (l_addc) {
55 
  orreg_t temp1, temp2, temp3;
56 
  int8_t temp4;
57 
 
58 
  temp2 = (orreg_t)PARAM2;
59 
  temp3 = (orreg_t)PARAM1;
60 
  temp1 = temp2 + temp3;
61 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
62 
    temp1++;
63 
  SET_PARAM0(temp1);
64 
  SET_OV_FLAG_FN (temp1);
65 
  if (ARITH_SET_FLAG) {
66 
    if(!temp1)
67 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
68 
    else
69 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
70 
  }
71 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
72 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
73 
  else
74 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
75 
 
76 
  temp4 = temp1;
77 
  if (temp4 == temp1)
78 
    or1k_mstats.byteadd++;
79 
}
80 
INSTRUCTION (l_sw) {
81 
  int old_cyc = 0;
82 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
83 
  set_mem32(PARAM0, PARAM1, &breakpoint);
84 
  if (config.cpu.sbuf_len) {
85 
    int t = runtime.sim.mem_cycles;
86 
    runtime.sim.mem_cycles = old_cyc;
87 
    sbuf_store (t - old_cyc);
88 
  }
89 
}
90 
INSTRUCTION (l_sb) {
91 
  int old_cyc = 0;
92 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
93 
  set_mem8(PARAM0, PARAM1, &breakpoint);
94 
  if (config.cpu.sbuf_len) {
95 
    int t = runtime.sim.mem_cycles;
96 
    runtime.sim.mem_cycles = old_cyc;
97 
    sbuf_store (t- old_cyc);
98 
  }
99 
}
100 
INSTRUCTION (l_sh) {
101 
  int old_cyc = 0;
102 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
103 
  set_mem16(PARAM0, PARAM1, &breakpoint);
104 
  if (config.cpu.sbuf_len) {
105 
    int t = runtime.sim.mem_cycles;
106 
    runtime.sim.mem_cycles = old_cyc;
107 
    sbuf_store (t - old_cyc);
108 
  }
109 
}
110 104 jeremybenn 
INSTRUCTION (l_lws) {
111 
  uint32_t val;
112 
  if (config.cpu.sbuf_len) sbuf_load ();
113 
  val = eval_mem32(PARAM1, &breakpoint);
114 
  /* If eval operand produced exception don't set anything. JPB changed to
115 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
116 
  if (!(except_pending || breakpoint))
117 
    SET_PARAM0(val);
118 
}
119 19 jeremybenn 
INSTRUCTION (l_lwz) {
120 
  uint32_t val;
121 
  if (config.cpu.sbuf_len) sbuf_load ();
122 
  val = eval_mem32(PARAM1, &breakpoint);
123 
  /* If eval operand produced exception don't set anything. JPB changed to
124 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
125 
  if (!(except_pending || breakpoint))
126 
    SET_PARAM0(val);
127 
}
128 
INSTRUCTION (l_lbs) {
129 
  int8_t val;
130 
  if (config.cpu.sbuf_len) sbuf_load ();
131 
  val = eval_mem8(PARAM1, &breakpoint);
132 
  /* If eval operand produced exception don't set anything. JPB changed to
133 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
134 
  if (!(except_pending || breakpoint))
135 
    SET_PARAM0(val);
136 
}
137 
INSTRUCTION (l_lbz) {
138 
  uint8_t val;
139 
  if (config.cpu.sbuf_len) sbuf_load ();
140 
  val = eval_mem8(PARAM1, &breakpoint);
141 
  /* If eval operand produced exception don't set anything. JPB changed to
142 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
143 
  if (!(except_pending || breakpoint))
144 
    SET_PARAM0(val);
145 
}
146 
INSTRUCTION (l_lhs) {
147 
  int16_t val;
148 
  if (config.cpu.sbuf_len) sbuf_load ();
149 
  val = eval_mem16(PARAM1, &breakpoint);
150 
  /* If eval operand produced exception don't set anything. JPB changed to
151 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
152 
  if (!(except_pending || breakpoint))
153 
    SET_PARAM0(val);
154 
}
155 
INSTRUCTION (l_lhz) {
156 
  uint16_t val;
157 
  if (config.cpu.sbuf_len) sbuf_load ();
158 
  val = eval_mem16(PARAM1, &breakpoint);
159 
  /* If eval operand produced exception don't set anything. JPB changed to
160 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
161 
  if (!(except_pending || breakpoint))
162 
    SET_PARAM0(val);
163 
}
164 
INSTRUCTION (l_movhi) {
165 
  SET_PARAM0(PARAM1 << 16);
166 
}
167 
INSTRUCTION (l_and) {
168 
  uorreg_t temp1;
169 
  temp1 = PARAM1 & PARAM2;
170 
  SET_OV_FLAG_FN (temp1);
171 
  SET_PARAM0(temp1);
172 
  if (ARITH_SET_FLAG) {
173 
    if(!temp1)
174 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
175 
    else
176 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
177 
  }
178 
}
179 
INSTRUCTION (l_or) {
180 
  uorreg_t temp1;
181 
  temp1 = PARAM1 | PARAM2;
182 
  SET_OV_FLAG_FN (temp1);
183 
  SET_PARAM0(temp1);
184 
}
185 
INSTRUCTION (l_xor) {
186 
  uorreg_t temp1;
187 
  temp1 = PARAM1 ^ PARAM2;
188 
  SET_OV_FLAG_FN (temp1);
189 
  SET_PARAM0(temp1);
190 
}
191 
INSTRUCTION (l_sub) {
192 
  orreg_t temp1;
193 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
194 
  SET_OV_FLAG_FN (temp1);
195 
  SET_PARAM0(temp1);
196 
}
197 
/*int mcount = 0;*/
198 
INSTRUCTION (l_mul) {
199 
  orreg_t temp1;
200 
 
201 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
202 
  SET_OV_FLAG_FN (temp1);
203 
  SET_PARAM0(temp1);
204 
  /*if (!(mcount++ & 1023)) {
205 
    PRINTF ("[%i]\n",mcount);
206 
    }*/
207 
}
208 
INSTRUCTION (l_div) {
209 
  orreg_t temp3, temp2, temp1;
210 
 
211 
  temp3 = PARAM2;
212 
  temp2 = PARAM1;
213 
  if (temp3)
214 
    temp1 = temp2 / temp3;
215 
  else {
216 107 jeremybenn 
    mtspr (SPR_SR, SPR_SR_CY | mfspr (SPR_SR)); /* Div by zero sets carry */
217 
    except_handle (EXCEPT_RANGE, cpu_state.pc);
218 19 jeremybenn 
    return;
219 
  }
220 
  SET_OV_FLAG_FN (temp1);
221 
  SET_PARAM0(temp1);
222 
}
223 
INSTRUCTION (l_divu) {
224 
  uorreg_t temp3, temp2, temp1;
225 
 
226 
  temp3 = PARAM2;
227 
  temp2 = PARAM1;
228 
  if (temp3)
229 
    temp1 = temp2 / temp3;
230 
  else {
231 107 jeremybenn 
    mtspr (SPR_SR, SPR_SR_CY | mfspr (SPR_SR)); /* Div by zero sets carry */
232 
    except_handle(EXCEPT_RANGE, cpu_state.pc);
233 19 jeremybenn 
    return;
234 
  }
235 
  SET_OV_FLAG_FN (temp1);
236 
  SET_PARAM0(temp1);
237 
  /* runtime.sim.cycles += 16; */
238 
}
239 
INSTRUCTION (l_sll) {
240 
  uorreg_t temp1;
241 
 
242 
  temp1 = PARAM1 << PARAM2;
243 
  SET_OV_FLAG_FN (temp1);
244 
  SET_PARAM0(temp1);
245 
  /* runtime.sim.cycles += 2; */
246 
}
247 
INSTRUCTION (l_sra) {
248 
  orreg_t temp1;
249 
 
250 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
251 
  SET_OV_FLAG_FN (temp1);
252 
  SET_PARAM0(temp1);
253 
  /* runtime.sim.cycles += 2; */
254 
}
255 
INSTRUCTION (l_srl) {
256 
  uorreg_t temp1;
257 
  temp1 = PARAM1 >> PARAM2;
258 
  SET_OV_FLAG_FN (temp1);
259 
  SET_PARAM0(temp1);
260 
  /* runtime.sim.cycles += 2; */
261 
}
262 
INSTRUCTION (l_bf) {
263 
  if (config.bpb.enabled) {
264 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
265 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
266 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
267 
  }
268 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
269 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
270 
    btic_update(pcnext);
271 
    next_delay_insn = 1;
272 
  } else {
273 
    btic_update(cpu_state.pc);
274 
  }
275 
}
276 
INSTRUCTION (l_bnf) {
277 
  if (config.bpb.enabled) {
278 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
279 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
280 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
281 
  }
282 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
283 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
284 
    btic_update(pcnext);
285 
    next_delay_insn = 1;
286 
  } else {
287 
    btic_update(cpu_state.pc);
288 
  }
289 
}
290 
INSTRUCTION (l_j) {
291 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
292 
  next_delay_insn = 1;
293 
}
294 
INSTRUCTION (l_jal) {
295 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
296 
 
297 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
298 
  next_delay_insn = 1;
299 
  if (config.sim.profile) {
300 
    struct label_entry *tmp;
301 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
302 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
303 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
304 
               tmp->name);
305 
    else
306 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
307 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
308 
               cpu_state.pc_delay);
309 
  }
310 
}
311 
INSTRUCTION (l_jalr) {
312 
  cpu_state.pc_delay = PARAM0;
313 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
314 
  next_delay_insn = 1;
315 
}
316 
INSTRUCTION (l_jr) {
317 
  cpu_state.pc_delay = PARAM0;
318 
  next_delay_insn = 1;
319 
  if (config.sim.profile)
320 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
321 
             cpu_state.pc_delay);
322 
}
323 
INSTRUCTION (l_rfe) {
324 
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
325 
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
326 
}
327 
INSTRUCTION (l_nop) {
328 
  uint32_t k = PARAM0;
329 
  switch (k) {
330 
    case NOP_NOP:
331 
      break;
332 
    case NOP_EXIT:
333 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
334 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
335 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
336 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
337 
              runtime.cpu.instructions);
338 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
339 
              runtime.sim.cycles - runtime.sim.reset_cycles,
340 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
341 
      if (config.debug.gdb_enabled)
342 
        set_stall_state (1);
343 
      else
344 
        sim_done();
345 
      break;
346 
    case NOP_CNT_RESET:
347 
      PRINTF("****************** counters reset ******************\n");
348 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
349 
      PRINTF("****************** counters reset ******************\n");
350 
      runtime.sim.reset_cycles = runtime.sim.cycles;
351 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
352 
      break;
353 
    case NOP_PUTC:              /*JPB */
354 
      printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
355 
      fflush( stdout );
356 
      break;
357 82 jeremybenn 
    case NOP_GET_TICKS:
358 
      cpu_state.reg[11] = runtime.sim.cycles & 0xffffffff;
359 
      cpu_state.reg[12] = runtime.sim.cycles >> 32;
360 
      break;
361 
    case NOP_GET_PS:
362 
      cpu_state.reg[11] = config.sim.clkcycle_ps;
363 
      break;
364 19 jeremybenn 
    case NOP_REPORT:
365 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
366 
    default:
367 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
368 
      PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
369 
             evalsim_reg(3));
370 
      break;
371 
  }
372 
}
373 
INSTRUCTION (l_sfeq) {
374 
  if(PARAM0 == PARAM1)
375 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
376 
  else
377 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
378 
}
379 
INSTRUCTION (l_sfne) {
380 
  if(PARAM0 != PARAM1)
381 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
382 
  else
383 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
384 
}
385 
INSTRUCTION (l_sfgts) {
386 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
387 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
388 
  else
389 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
390 
}
391 
INSTRUCTION (l_sfges) {
392 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
393 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
394 
  else
395 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
396 
}
397 
INSTRUCTION (l_sflts) {
398 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
399 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
400 
  else
401 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
402 
}
403 
INSTRUCTION (l_sfles) {
404 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
405 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
406 
  else
407 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
408 
}
409 
INSTRUCTION (l_sfgtu) {
410 
  if(PARAM0 > PARAM1)
411 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
412 
  else
413 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
414 
}
415 
INSTRUCTION (l_sfgeu) {
416 
  if(PARAM0 >= PARAM1)
417 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
418 
  else
419 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
420 
}
421 
INSTRUCTION (l_sfltu) {
422 
  if(PARAM0 < PARAM1)
423 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
424 
  else
425 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
426 
}
427 
INSTRUCTION (l_sfleu) {
428 
  if(PARAM0 <= PARAM1)
429 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
430 
  else
431 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
432 
}
433 
INSTRUCTION (l_extbs) {
434 
  int8_t x;
435 
  x = PARAM1;
436 
  SET_PARAM0((orreg_t)x);
437 
}
438 
INSTRUCTION (l_extbz) {
439 
  uint8_t x;
440 
  x = PARAM1;
441 
  SET_PARAM0((uorreg_t)x);
442 
}
443 
INSTRUCTION (l_exths) {
444 
  int16_t x;
445 
  x = PARAM1;
446 
  SET_PARAM0((orreg_t)x);
447 
}
448 
INSTRUCTION (l_exthz) {
449 
  uint16_t x;
450 
  x = PARAM1;
451 
  SET_PARAM0((uorreg_t)x);
452 
}
453 
INSTRUCTION (l_extws) {
454 
  int32_t x;
455 
  x = PARAM1;
456 
  SET_PARAM0((orreg_t)x);
457 
}
458 
INSTRUCTION (l_extwz) {
459 
  uint32_t x;
460 
  x = PARAM1;
461 
  SET_PARAM0((uorreg_t)x);
462 
}
463 
INSTRUCTION (l_mtspr) {
464 
  uint16_t regno = PARAM0 + PARAM2;
465 
  uorreg_t value = PARAM1;
466 
 
467 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
468 
    mtspr(regno, value);
469 
  else {
470 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
471 
    sim_done();
472 
  }
473 
}
474 
INSTRUCTION (l_mfspr) {
475 
  uint16_t regno = PARAM1 + PARAM2;
476 
  uorreg_t value = mfspr(regno);
477 
 
478 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
479 
    SET_PARAM0(value);
480 
  else {
481 
    SET_PARAM0(0);
482 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
483 
    sim_done();
484 
  }
485 
}
486 
INSTRUCTION (l_sys) {
487 
  except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
488 
}
489 
INSTRUCTION (l_trap) {
490 
  /* TODO: some SR related code here! */
491 
  except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
492 
}
493 
INSTRUCTION (l_mac) {
494 
  uorreg_t lo, hi;
495 
  LONGEST l;
496 
  orreg_t x, y;
497 
 
498 
  lo = cpu_state.sprs[SPR_MACLO];
499 
  hi = cpu_state.sprs[SPR_MACHI];
500 
  x = PARAM0;
501 
  y = PARAM1;
502 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
503 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
504 
  l += (LONGEST) x * (LONGEST) y;
505 
 
506 
  /* This implementation is very fast - it needs only one cycle for mac.  */
507 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
508 
  hi = ((LONGEST)l) >> 32;
509 
  cpu_state.sprs[SPR_MACLO] = lo;
510 
  cpu_state.sprs[SPR_MACHI] = hi;
511 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo); */
512 
}
513 
INSTRUCTION (l_msb) {
514 
  uorreg_t lo, hi;
515 
  LONGEST l;
516 
  orreg_t x, y;
517 
 
518 
  lo = cpu_state.sprs[SPR_MACLO];
519 
  hi = cpu_state.sprs[SPR_MACHI];
520 
  x = PARAM0;
521 
  y = PARAM1;
522 
 
523 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
524 
 
525 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
526 
  l -= x * y;
527 
 
528 
  /* This implementation is very fast - it needs only one cycle for msb.  */
529 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
530 
  hi = ((LONGEST)l) >> 32;
531 
  cpu_state.sprs[SPR_MACLO] = lo;
532 
  cpu_state.sprs[SPR_MACHI] = hi;
533 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
534 
}
535 
INSTRUCTION (l_macrc) {
536 
  uorreg_t lo, hi;
537 
  LONGEST l;
538 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
539 
  lo =  cpu_state.sprs[SPR_MACLO];
540 
  hi =  cpu_state.sprs[SPR_MACHI];
541 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
542 
  l >>= 28;
543 
  //PRINTF ("<%08x>\n", (unsigned long)l);
544 
  SET_PARAM0((orreg_t)l);
545 
  cpu_state.sprs[SPR_MACLO] = 0;
546 
  cpu_state.sprs[SPR_MACHI] = 0;
547 
}
548 
INSTRUCTION (l_cmov) {
549 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
550 
}
551 
INSTRUCTION (l_ff1) {
552 
  SET_PARAM0(ffs(PARAM1));
553 
}
554 
/******* Floating point instructions *******/
555 
/* Single precision */
556 
INSTRUCTION (lf_add_s) {
557 100 julius 
  if (config.cpu.hardfloat) {
558 
  FLOAT param0, param1, param2;
559 
  param1.hval = (uorreg_t)PARAM1;
560 
  param2.hval = (uorreg_t)PARAM2;
561 
  param0.fval = param1.fval + param2.fval;
562 
  SET_PARAM0(param0.hval);
563 
  } else l_invalid();
564 19 jeremybenn 
}
565 
INSTRUCTION (lf_div_s) {
566 100 julius 
  if (config.cpu.hardfloat) {
567 
  FLOAT param0, param1, param2;
568 
  param1.hval = (uorreg_t)PARAM1;
569 
  param2.hval = (uorreg_t)PARAM2;
570 
  param0.fval = param1.fval / param2.fval;
571 
  SET_PARAM0(param0.hval);
572 
  } else l_invalid();
573 19 jeremybenn 
}
574 
INSTRUCTION (lf_ftoi_s) {
575 100 julius 
  if (config.cpu.hardfloat) {
576 
    // no other way appeared to work --jb
577 
    float tmp_f; memcpy((void*)&tmp_f, (void*)&PARAM1, sizeof(float));
578 
    SET_PARAM0((int)tmp_f);
579 
  } else l_invalid();
580 19 jeremybenn 
}
581 
INSTRUCTION (lf_itof_s) {
582 100 julius 
  if (config.cpu.hardfloat) {
583 
  FLOAT param0;
584 
  param0.fval = (float)((int)PARAM1);
585 
  SET_PARAM0(param0.hval);
586 
  } else l_invalid();
587 19 jeremybenn 
}
588 
INSTRUCTION (lf_madd_s) {
589 100 julius 
  if (config.cpu.hardfloat) {
590 
  FLOAT param0,param1, param2;
591 104 jeremybenn 
  param0.hval = (uorreg_t)PARAM0;
592 
  param1.hval = (uorreg_t)PARAM1;
593 100 julius 
  param2.hval = PARAM2;
594 
  param0.fval += param1.fval * param2.fval;
595 
  SET_PARAM0(param0.hval);
596 
  } else l_invalid();
597 19 jeremybenn 
}
598 
INSTRUCTION (lf_mul_s) {
599 100 julius 
  if (config.cpu.hardfloat) {
600 
  FLOAT param0, param1, param2;
601 
  param1.hval = (uorreg_t)PARAM1;
602 
  param2.hval = (uorreg_t)PARAM2;
603 
  param0.fval = param1.fval * param2.fval;
604 
  SET_PARAM0(param0.hval);
605 
  } else l_invalid();
606 19 jeremybenn 
}
607 
INSTRUCTION (lf_rem_s) {
608 100 julius 
  if (config.cpu.hardfloat) {
609 
  FLOAT param0, param1, param2;
610 
  param1.hval = PARAM1;
611 
  param2.hval = PARAM2;
612 104 jeremybenn 
  param0.fval = fmodf (param1.fval, param2.fval);
613 100 julius 
  SET_PARAM0(param0.hval);
614 
  } else l_invalid();
615 19 jeremybenn 
}
616 
INSTRUCTION (lf_sfeq_s) {
617 100 julius 
  if (config.cpu.hardfloat) {
618 
  FLOAT param0, param1;
619 
  param0.hval = PARAM0;
620 
  param1.hval = PARAM1;
621 
  if(param0.fval == param1.fval)
622 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
623 
  else
624 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
625 100 julius 
  } else l_invalid();
626 19 jeremybenn 
}
627 
INSTRUCTION (lf_sfge_s) {
628 100 julius 
  if (config.cpu.hardfloat) {
629 
  FLOAT param0, param1;
630 
  param0.hval = PARAM0;
631 
  param1.hval = PARAM1;
632 
  if(param0.fval >= param1.fval)
633 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
634 
  else
635 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
636 100 julius 
  } else l_invalid();
637 19 jeremybenn 
}
638 
INSTRUCTION (lf_sfgt_s) {
639 100 julius 
  if (config.cpu.hardfloat) {
640 
  FLOAT param0, param1;
641 
  param0.hval = PARAM0;
642 
  param1.hval = PARAM1;
643 
  if(param0.fval > param1.fval)
644 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
645 
  else
646 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
647 100 julius 
  } else l_invalid();
648 19 jeremybenn 
}
649 
INSTRUCTION (lf_sfle_s) {
650 100 julius 
  if (config.cpu.hardfloat) {
651 
  FLOAT param0, param1;
652 
  param0.hval = PARAM0;
653 
  param1.hval = PARAM1;
654 
  if(param0.fval <= param1.fval)
655 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
656 
  else
657 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
658 100 julius 
  } else l_invalid();
659 19 jeremybenn 
}
660 
INSTRUCTION (lf_sflt_s) {
661 100 julius 
  if (config.cpu.hardfloat) {
662 
  FLOAT param0, param1;
663 
  param0.hval = PARAM0;
664 
  param1.hval = PARAM1;
665 
  if(param0.fval < param1.fval)
666 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
667 
  else
668 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
669 100 julius 
  } else l_invalid();
670 19 jeremybenn 
}
671 
INSTRUCTION (lf_sfne_s) {
672 100 julius 
  if (config.cpu.hardfloat) {
673 
  FLOAT param0, param1;
674 
  param0.hval = PARAM0;
675 
  param1.hval = PARAM1;
676 
  if(param0.fval != param1.fval)
677 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
678 
  else
679 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
680 100 julius 
  } else l_invalid();
681 19 jeremybenn 
}
682 
INSTRUCTION (lf_sub_s) {
683 100 julius 
  if (config.cpu.hardfloat) {
684 
  FLOAT param0, param1, param2;
685 
  param1.hval = PARAM1;
686 
  param2.hval = PARAM2;
687 
  param0.fval = param1.fval - param2.fval;
688 
  SET_PARAM0(param0.hval);
689 
  } else l_invalid();
690 19 jeremybenn 
}
691 
 
692 
/******* Custom instructions *******/
693 
INSTRUCTION (l_cust1) {
694 
  /*int destr = current->insn >> 21;
695 
    int src1r = current->insn >> 15;
696 
    int src2r = current->insn >> 9;*/
697 
}
698 
INSTRUCTION (l_cust2) {
699 
}
700 
INSTRUCTION (l_cust3) {
701 
}
702 
INSTRUCTION (l_cust4) {
703 
}
704 100 julius 
INSTRUCTION (lf_cust1) {
705 
}

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