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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 22

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Line No. Rev Author Line
1 19 jeremybenn 
/* insnset.c -- Instruction specific functions.
2 
 
3 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4 
                 2000-2002 Marko Mlinar, markom@opencores.org
5 
   Copyright (C) 2008 Embecosm Limited
6 
 
7 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8 
 
9 
   This file is part of OpenRISC 1000 Architectural Simulator.
10 
 
11 
   This program is free software; you can redistribute it and/or modify it
12 
   under the terms of the GNU General Public License as published by the Free
13 
   Software Foundation; either version 3 of the License, or (at your option)
14 
   any later version.
15 
 
16 
   This program is distributed in the hope that it will be useful, but WITHOUT
17 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19 
   more details.
20 
 
21 
   You should have received a copy of the GNU General Public License along
22 
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
23 
 
24 
/* This program is commented throughout in a fashion suitable for processing
25 
   with Doxygen. */
26 
 
27 
 
28 
INSTRUCTION (l_add) {
29 
  orreg_t temp1, temp2, temp3;
30 
  int8_t temp4;
31 
 
32 
  temp2 = (orreg_t)PARAM2;
33 
  temp3 = (orreg_t)PARAM1;
34 
  temp1 = temp2 + temp3;
35 
  SET_PARAM0(temp1);
36 
  SET_OV_FLAG_FN (temp1);
37 
  if (ARITH_SET_FLAG) {
38 
    if(!temp1)
39 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
40 
    else
41 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
42 
  }
43 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
44 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
45 
  else
46 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
47 
 
48 
  temp4 = temp1;
49 
  if (temp4 == temp1)
50 
    or1k_mstats.byteadd++;
51 
}
52 
INSTRUCTION (l_addc) {
53 
  orreg_t temp1, temp2, temp3;
54 
  int8_t temp4;
55 
 
56 
  temp2 = (orreg_t)PARAM2;
57 
  temp3 = (orreg_t)PARAM1;
58 
  temp1 = temp2 + temp3;
59 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
60 
    temp1++;
61 
  SET_PARAM0(temp1);
62 
  SET_OV_FLAG_FN (temp1);
63 
  if (ARITH_SET_FLAG) {
64 
    if(!temp1)
65 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
66 
    else
67 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
68 
  }
69 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
70 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
71 
  else
72 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
73 
 
74 
  temp4 = temp1;
75 
  if (temp4 == temp1)
76 
    or1k_mstats.byteadd++;
77 
}
78 
INSTRUCTION (l_sw) {
79 
  int old_cyc = 0;
80 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
81 
  set_mem32(PARAM0, PARAM1, &breakpoint);
82 
  if (config.cpu.sbuf_len) {
83 
    int t = runtime.sim.mem_cycles;
84 
    runtime.sim.mem_cycles = old_cyc;
85 
    sbuf_store (t - old_cyc);
86 
  }
87 
}
88 
INSTRUCTION (l_sb) {
89 
  int old_cyc = 0;
90 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
91 
  set_mem8(PARAM0, PARAM1, &breakpoint);
92 
  if (config.cpu.sbuf_len) {
93 
    int t = runtime.sim.mem_cycles;
94 
    runtime.sim.mem_cycles = old_cyc;
95 
    sbuf_store (t- old_cyc);
96 
  }
97 
}
98 
INSTRUCTION (l_sh) {
99 
  int old_cyc = 0;
100 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
101 
  set_mem16(PARAM0, PARAM1, &breakpoint);
102 
  if (config.cpu.sbuf_len) {
103 
    int t = runtime.sim.mem_cycles;
104 
    runtime.sim.mem_cycles = old_cyc;
105 
    sbuf_store (t - old_cyc);
106 
  }
107 
}
108 
INSTRUCTION (l_lwz) {
109 
  uint32_t val;
110 
  if (config.cpu.sbuf_len) sbuf_load ();
111 
  val = eval_mem32(PARAM1, &breakpoint);
112 
  /* If eval operand produced exception don't set anything. JPB changed to
113 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
114 
  if (!(except_pending || breakpoint))
115 
    SET_PARAM0(val);
116 
}
117 
INSTRUCTION (l_lbs) {
118 
  int8_t val;
119 
  if (config.cpu.sbuf_len) sbuf_load ();
120 
  val = eval_mem8(PARAM1, &breakpoint);
121 
  /* If eval operand produced exception don't set anything. JPB changed to
122 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
123 
  if (!(except_pending || breakpoint))
124 
    SET_PARAM0(val);
125 
}
126 
INSTRUCTION (l_lbz) {
127 
  uint8_t val;
128 
  if (config.cpu.sbuf_len) sbuf_load ();
129 
  val = eval_mem8(PARAM1, &breakpoint);
130 
  /* If eval operand produced exception don't set anything. JPB changed to
131 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
132 
  if (!(except_pending || breakpoint))
133 
    SET_PARAM0(val);
134 
}
135 
INSTRUCTION (l_lhs) {
136 
  int16_t val;
137 
  if (config.cpu.sbuf_len) sbuf_load ();
138 
  val = eval_mem16(PARAM1, &breakpoint);
139 
  /* If eval operand produced exception don't set anything. JPB changed to
140 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
141 
  if (!(except_pending || breakpoint))
142 
    SET_PARAM0(val);
143 
}
144 
INSTRUCTION (l_lhz) {
145 
  uint16_t val;
146 
  if (config.cpu.sbuf_len) sbuf_load ();
147 
  val = eval_mem16(PARAM1, &breakpoint);
148 
  /* If eval operand produced exception don't set anything. JPB changed to
149 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
150 
  if (!(except_pending || breakpoint))
151 
    SET_PARAM0(val);
152 
}
153 
INSTRUCTION (l_movhi) {
154 
  SET_PARAM0(PARAM1 << 16);
155 
}
156 
INSTRUCTION (l_and) {
157 
  uorreg_t temp1;
158 
  temp1 = PARAM1 & PARAM2;
159 
  SET_OV_FLAG_FN (temp1);
160 
  SET_PARAM0(temp1);
161 
  if (ARITH_SET_FLAG) {
162 
    if(!temp1)
163 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
164 
    else
165 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
166 
  }
167 
}
168 
INSTRUCTION (l_or) {
169 
  uorreg_t temp1;
170 
  temp1 = PARAM1 | PARAM2;
171 
  SET_OV_FLAG_FN (temp1);
172 
  SET_PARAM0(temp1);
173 
}
174 
INSTRUCTION (l_xor) {
175 
  uorreg_t temp1;
176 
  temp1 = PARAM1 ^ PARAM2;
177 
  SET_OV_FLAG_FN (temp1);
178 
  SET_PARAM0(temp1);
179 
}
180 
INSTRUCTION (l_sub) {
181 
  orreg_t temp1;
182 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
183 
  SET_OV_FLAG_FN (temp1);
184 
  SET_PARAM0(temp1);
185 
}
186 
/*int mcount = 0;*/
187 
INSTRUCTION (l_mul) {
188 
  orreg_t temp1;
189 
 
190 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
191 
  SET_OV_FLAG_FN (temp1);
192 
  SET_PARAM0(temp1);
193 
  /*if (!(mcount++ & 1023)) {
194 
    PRINTF ("[%i]\n",mcount);
195 
    }*/
196 
}
197 
INSTRUCTION (l_div) {
198 
  orreg_t temp3, temp2, temp1;
199 
 
200 
  temp3 = PARAM2;
201 
  temp2 = PARAM1;
202 
  if (temp3)
203 
    temp1 = temp2 / temp3;
204 
  else {
205 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
206 
    return;
207 
  }
208 
  SET_OV_FLAG_FN (temp1);
209 
  SET_PARAM0(temp1);
210 
}
211 
INSTRUCTION (l_divu) {
212 
  uorreg_t temp3, temp2, temp1;
213 
 
214 
  temp3 = PARAM2;
215 
  temp2 = PARAM1;
216 
  if (temp3)
217 
    temp1 = temp2 / temp3;
218 
  else {
219 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
220 
    return;
221 
  }
222 
  SET_OV_FLAG_FN (temp1);
223 
  SET_PARAM0(temp1);
224 
  /* runtime.sim.cycles += 16; */
225 
}
226 
INSTRUCTION (l_sll) {
227 
  uorreg_t temp1;
228 
 
229 
  temp1 = PARAM1 << PARAM2;
230 
  SET_OV_FLAG_FN (temp1);
231 
  SET_PARAM0(temp1);
232 
  /* runtime.sim.cycles += 2; */
233 
}
234 
INSTRUCTION (l_sra) {
235 
  orreg_t temp1;
236 
 
237 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
238 
  SET_OV_FLAG_FN (temp1);
239 
  SET_PARAM0(temp1);
240 
  /* runtime.sim.cycles += 2; */
241 
}
242 
INSTRUCTION (l_srl) {
243 
  uorreg_t temp1;
244 
  temp1 = PARAM1 >> PARAM2;
245 
  SET_OV_FLAG_FN (temp1);
246 
  SET_PARAM0(temp1);
247 
  /* runtime.sim.cycles += 2; */
248 
}
249 
INSTRUCTION (l_bf) {
250 
  if (config.bpb.enabled) {
251 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
252 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
253 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
254 
  }
255 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
256 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
257 
    btic_update(pcnext);
258 
    next_delay_insn = 1;
259 
  } else {
260 
    btic_update(cpu_state.pc);
261 
  }
262 
}
263 
INSTRUCTION (l_bnf) {
264 
  if (config.bpb.enabled) {
265 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
266 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
267 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
268 
  }
269 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
270 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
271 
    btic_update(pcnext);
272 
    next_delay_insn = 1;
273 
  } else {
274 
    btic_update(cpu_state.pc);
275 
  }
276 
}
277 
INSTRUCTION (l_j) {
278 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
279 
  next_delay_insn = 1;
280 
}
281 
INSTRUCTION (l_jal) {
282 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
283 
 
284 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
285 
  next_delay_insn = 1;
286 
  if (config.sim.profile) {
287 
    struct label_entry *tmp;
288 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
289 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
290 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
291 
               tmp->name);
292 
    else
293 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
294 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
295 
               cpu_state.pc_delay);
296 
  }
297 
}
298 
INSTRUCTION (l_jalr) {
299 
  cpu_state.pc_delay = PARAM0;
300 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
301 
  next_delay_insn = 1;
302 
}
303 
INSTRUCTION (l_jr) {
304 
  cpu_state.pc_delay = PARAM0;
305 
  next_delay_insn = 1;
306 
  if (config.sim.profile)
307 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
308 
             cpu_state.pc_delay);
309 
}
310 
INSTRUCTION (l_rfe) {
311 
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
312 
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
313 
}
314 
INSTRUCTION (l_nop) {
315 
  oraddr_t stackaddr;
316 
  uint32_t k = PARAM0;
317 
  switch (k) {
318 
    case NOP_NOP:
319 
      break;
320 
    case NOP_EXIT:
321 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
322 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
323 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
324 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
325 
              runtime.cpu.instructions);
326 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
327 
              runtime.sim.cycles - runtime.sim.reset_cycles,
328 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
329 
      if (config.debug.gdb_enabled)
330 
        set_stall_state (1);
331 
      else
332 
        sim_done();
333 
      break;
334 
    case NOP_CNT_RESET:
335 
      PRINTF("****************** counters reset ******************\n");
336 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
337 
      PRINTF("****************** counters reset ******************\n");
338 
      runtime.sim.reset_cycles = runtime.sim.cycles;
339 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
340 
      break;
341 
    case NOP_PRINTF:
342 
      stackaddr = evalsim_reg(4);
343 
      simprintf(stackaddr, evalsim_reg(3));
344 
      break;
345 
    case NOP_PUTC:              /*JPB */
346 
      printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
347 
      fflush( stdout );
348 
      break;
349 
    case NOP_REPORT:
350 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
351 
    default:
352 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
353 
      PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
354 
             evalsim_reg(3));
355 
      break;
356 
  }
357 
}
358 
INSTRUCTION (l_sfeq) {
359 
  if(PARAM0 == PARAM1)
360 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
361 
  else
362 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
363 
}
364 
INSTRUCTION (l_sfne) {
365 
  if(PARAM0 != PARAM1)
366 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
367 
  else
368 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
369 
}
370 
INSTRUCTION (l_sfgts) {
371 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
372 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
373 
  else
374 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
375 
}
376 
INSTRUCTION (l_sfges) {
377 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
378 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
379 
  else
380 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
381 
}
382 
INSTRUCTION (l_sflts) {
383 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
384 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
385 
  else
386 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
387 
}
388 
INSTRUCTION (l_sfles) {
389 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
390 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
391 
  else
392 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
393 
}
394 
INSTRUCTION (l_sfgtu) {
395 
  if(PARAM0 > PARAM1)
396 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
397 
  else
398 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
399 
}
400 
INSTRUCTION (l_sfgeu) {
401 
  if(PARAM0 >= PARAM1)
402 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
403 
  else
404 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
405 
}
406 
INSTRUCTION (l_sfltu) {
407 
  if(PARAM0 < PARAM1)
408 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
409 
  else
410 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
411 
}
412 
INSTRUCTION (l_sfleu) {
413 
  if(PARAM0 <= PARAM1)
414 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
415 
  else
416 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
417 
}
418 
INSTRUCTION (l_extbs) {
419 
  int8_t x;
420 
  x = PARAM1;
421 
  SET_PARAM0((orreg_t)x);
422 
}
423 
INSTRUCTION (l_extbz) {
424 
  uint8_t x;
425 
  x = PARAM1;
426 
  SET_PARAM0((uorreg_t)x);
427 
}
428 
INSTRUCTION (l_exths) {
429 
  int16_t x;
430 
  x = PARAM1;
431 
  SET_PARAM0((orreg_t)x);
432 
}
433 
INSTRUCTION (l_exthz) {
434 
  uint16_t x;
435 
  x = PARAM1;
436 
  SET_PARAM0((uorreg_t)x);
437 
}
438 
INSTRUCTION (l_extws) {
439 
  int32_t x;
440 
  x = PARAM1;
441 
  SET_PARAM0((orreg_t)x);
442 
}
443 
INSTRUCTION (l_extwz) {
444 
  uint32_t x;
445 
  x = PARAM1;
446 
  SET_PARAM0((uorreg_t)x);
447 
}
448 
INSTRUCTION (l_mtspr) {
449 
  uint16_t regno = PARAM0 + PARAM2;
450 
  uorreg_t value = PARAM1;
451 
 
452 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
453 
    mtspr(regno, value);
454 
  else {
455 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
456 
    sim_done();
457 
  }
458 
}
459 
INSTRUCTION (l_mfspr) {
460 
  uint16_t regno = PARAM1 + PARAM2;
461 
  uorreg_t value = mfspr(regno);
462 
 
463 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
464 
    SET_PARAM0(value);
465 
  else {
466 
    SET_PARAM0(0);
467 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
468 
    sim_done();
469 
  }
470 
}
471 
INSTRUCTION (l_sys) {
472 
  except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
473 
}
474 
INSTRUCTION (l_trap) {
475 
  /* TODO: some SR related code here! */
476 
  except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
477 
}
478 
INSTRUCTION (l_mac) {
479 
  uorreg_t lo, hi;
480 
  LONGEST l;
481 
  orreg_t x, y;
482 
 
483 
  lo = cpu_state.sprs[SPR_MACLO];
484 
  hi = cpu_state.sprs[SPR_MACHI];
485 
  x = PARAM0;
486 
  y = PARAM1;
487 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
488 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
489 
  l += (LONGEST) x * (LONGEST) y;
490 
 
491 
  /* This implementation is very fast - it needs only one cycle for mac.  */
492 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
493 
  hi = ((LONGEST)l) >> 32;
494 
  cpu_state.sprs[SPR_MACLO] = lo;
495 
  cpu_state.sprs[SPR_MACHI] = hi;
496 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo); */
497 
}
498 
INSTRUCTION (l_msb) {
499 
  uorreg_t lo, hi;
500 
  LONGEST l;
501 
  orreg_t x, y;
502 
 
503 
  lo = cpu_state.sprs[SPR_MACLO];
504 
  hi = cpu_state.sprs[SPR_MACHI];
505 
  x = PARAM0;
506 
  y = PARAM1;
507 
 
508 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
509 
 
510 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
511 
  l -= x * y;
512 
 
513 
  /* This implementation is very fast - it needs only one cycle for msb.  */
514 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
515 
  hi = ((LONGEST)l) >> 32;
516 
  cpu_state.sprs[SPR_MACLO] = lo;
517 
  cpu_state.sprs[SPR_MACHI] = hi;
518 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
519 
}
520 
INSTRUCTION (l_macrc) {
521 
  uorreg_t lo, hi;
522 
  LONGEST l;
523 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
524 
  lo =  cpu_state.sprs[SPR_MACLO];
525 
  hi =  cpu_state.sprs[SPR_MACHI];
526 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
527 
  l >>= 28;
528 
  //PRINTF ("<%08x>\n", (unsigned long)l);
529 
  SET_PARAM0((orreg_t)l);
530 
  cpu_state.sprs[SPR_MACLO] = 0;
531 
  cpu_state.sprs[SPR_MACHI] = 0;
532 
}
533 
INSTRUCTION (l_cmov) {
534 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
535 
}
536 
INSTRUCTION (l_ff1) {
537 
  SET_PARAM0(ffs(PARAM1));
538 
}
539 
/******* Floating point instructions *******/
540 
/* Single precision */
541 
INSTRUCTION (lf_add_s) {
542 
  SET_PARAM0((float)PARAM1 + (float)PARAM2);
543 
}
544 
INSTRUCTION (lf_div_s) {
545 
  SET_PARAM0((float)PARAM1 / (float)PARAM2);
546 
}
547 
INSTRUCTION (lf_ftoi_s) {
548 
//  set_operand32(0, freg[get_operand(1)], &breakpoint);
549 
}
550 
INSTRUCTION (lf_itof_s) {
551 
//  freg[get_operand(0)] = eval_operand32(1, &breakpoint);
552 
}
553 
INSTRUCTION (lf_madd_s) {
554 
  SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2);
555 
}
556 
INSTRUCTION (lf_mul_s) {
557 
  SET_PARAM0((float)PARAM1 * (float)PARAM2);
558 
}
559 
INSTRUCTION (lf_rem_s) {
560 
  float temp = (float)PARAM1 / (float)PARAM2;
561 
  SET_PARAM0(temp - (uint32_t)temp);
562 
}
563 
INSTRUCTION (lf_sfeq_s) {
564 
  if((float)PARAM0 == (float)PARAM1)
565 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
566 
  else
567 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
568 
}
569 
INSTRUCTION (lf_sfge_s) {
570 
  if((float)PARAM0 >= (float)PARAM1)
571 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
572 
  else
573 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
574 
}
575 
INSTRUCTION (lf_sfgt_s) {
576 
  if((float)PARAM0 > (float)PARAM1)
577 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
578 
  else
579 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
580 
}
581 
INSTRUCTION (lf_sfle_s) {
582 
  if((float)PARAM0 <= (float)PARAM1)
583 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
584 
  else
585 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
586 
}
587 
INSTRUCTION (lf_sflt_s) {
588 
  if((float)PARAM0 < (float)PARAM1)
589 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
590 
  else
591 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
592 
}
593 
INSTRUCTION (lf_sfne_s) {
594 
  if((float)PARAM0 != (float)PARAM1)
595 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
596 
  else
597 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
598 
}
599 
INSTRUCTION (lf_sub_s) {
600 
  SET_PARAM0((float)PARAM1 - (float)PARAM2);
601 
}
602 
 
603 
/******* Custom instructions *******/
604 
INSTRUCTION (l_cust1) {
605 
  /*int destr = current->insn >> 21;
606 
    int src1r = current->insn >> 15;
607 
    int src2r = current->insn >> 9;*/
608 
}
609 
INSTRUCTION (l_cust2) {
610 
}
611 
INSTRUCTION (l_cust3) {
612 
}
613 
INSTRUCTION (l_cust4) {
614 
}

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