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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 417

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Line No. Rev Author Line
1 19 jeremybenn 
/* insnset.c -- Instruction specific functions.
2 
 
3 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4 
                 2000-2002 Marko Mlinar, markom@opencores.org
5 
   Copyright (C) 2008 Embecosm Limited
6 100 julius 
   Copyright (C) 2009 Jungsook yang, jungsook.yang@uci.edu
7 19 jeremybenn 
 
8 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
9 100 julius 
   Contributor Julius Baxter julius@orsoc.se
10 
 
11 19 jeremybenn 
   This file is part of OpenRISC 1000 Architectural Simulator.
12 
 
13 
   This program is free software; you can redistribute it and/or modify it
14 
   under the terms of the GNU General Public License as published by the Free
15 
   Software Foundation; either version 3 of the License, or (at your option)
16 
   any later version.
17 
 
18 
   This program is distributed in the hope that it will be useful, but WITHOUT
19 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
21 
   more details.
22 
 
23 
   You should have received a copy of the GNU General Public License along
24 
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
25 
 
26 
/* This program is commented throughout in a fashion suitable for processing
27 
   with Doxygen. */
28 
 
29 
 
30 
INSTRUCTION (l_add) {
31 
  orreg_t temp1, temp2, temp3;
32 
  int8_t temp4;
33 
 
34 
  temp2 = (orreg_t)PARAM2;
35 
  temp3 = (orreg_t)PARAM1;
36 
  temp1 = temp2 + temp3;
37 124 jeremybenn 
  SET_PARAM0 (temp1);
38 112 jeremybenn 
 
39 
  /* Set overflow if two negative values gave a positive sum, or if two
40 
     positive values gave a negative sum. Otherwise clear it */
41 
  if ((((long int) temp2 <  0) &&
42 
       ((long int) temp3 <  0) &&
43 
       ((long int) temp1 >= 0)) ||
44 
      (((long int) temp2 >= 0) &&
45 
       ((long int) temp3 >= 0) &&
46 
       ((long int) temp1 <  0)))
47 
    {
48 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
49 
    }
50 
  else
51 
    {
52 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
53 
    }
54 
 
55 
  /* Set the carry flag if (as unsigned values) the result is smaller than
56 
     either operand (if it smaller than one, it will be smaller than both, so
57 
     we need only test one). */
58 19 jeremybenn 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
59 112 jeremybenn 
    {
60 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
61 
    }
62 19 jeremybenn 
  else
63 112 jeremybenn 
    {
64 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
65 
    }
66 19 jeremybenn 
 
67 112 jeremybenn 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
68 
     is set. */
69 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
70 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
71 
    {
72 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
73 
    }
74 
 
75 19 jeremybenn 
  temp4 = temp1;
76 
  if (temp4 == temp1)
77 
    or1k_mstats.byteadd++;
78 
}
79 
INSTRUCTION (l_addc) {
80 
  orreg_t temp1, temp2, temp3;
81 
  int8_t temp4;
82 114 jeremybenn 
  int    carry_in = (cpu_state.sprs[SPR_SR] & SPR_SR_CY) == SPR_SR_CY;
83 
 
84 19 jeremybenn 
  temp2 = (orreg_t)PARAM2;
85 
  temp3 = (orreg_t)PARAM1;
86 
  temp1 = temp2 + temp3;
87 114 jeremybenn 
 
88 
  if(carry_in)
89 
    {
90 
      temp1++;                          /* Add in the carry bit */
91 
    }
92 
 
93 19 jeremybenn 
  SET_PARAM0(temp1);
94 114 jeremybenn 
 
95 
  /* Set overflow if two negative values gave a positive sum, or if two
96 
     positive values gave a negative sum. Otherwise clear it. There are no
97 
     corner cases with the extra bit carried in (unlike the carry flag - see
98 
     below). */
99 
  if ((((long int) temp2 <  0) &&
100 
       ((long int) temp3 <  0) &&
101 
       ((long int) temp1 >= 0)) ||
102 
      (((long int) temp2 >= 0) &&
103 
       ((long int) temp3 >= 0) &&
104 
       ((long int) temp1 <  0)))
105 
    {
106 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
107 
    }
108 19 jeremybenn 
  else
109 114 jeremybenn 
    {
110 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
111 
    }
112 19 jeremybenn 
 
113 114 jeremybenn 
  /* Set the carry flag if (as unsigned values) the result is smaller than
114 
     either operand (if it smaller than one, it will be smaller than both, so
115 
     we need only test one). If there is a carry in, the test should be less
116 
     than or equal, to deal with the 0 + 0xffffffff + c = 0 case (which
117 
     generates a carry). */
118 
  if ((carry_in && ((uorreg_t) temp1 <= (uorreg_t) temp2)) ||
119 
      ((uorreg_t) temp1 < (uorreg_t) temp2))
120 
    {
121 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
122 
    }
123 
  else
124 
    {
125 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
126 
    }
127 
 
128 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
129 
     is set. */
130 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
131 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
132 
    {
133 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
134 
    }
135 
 
136 19 jeremybenn 
  temp4 = temp1;
137 
  if (temp4 == temp1)
138 
    or1k_mstats.byteadd++;
139 
}
140 
INSTRUCTION (l_sw) {
141 
  int old_cyc = 0;
142 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
143 
  set_mem32(PARAM0, PARAM1, &breakpoint);
144 
  if (config.cpu.sbuf_len) {
145 
    int t = runtime.sim.mem_cycles;
146 
    runtime.sim.mem_cycles = old_cyc;
147 
    sbuf_store (t - old_cyc);
148 
  }
149 
}
150 
INSTRUCTION (l_sb) {
151 
  int old_cyc = 0;
152 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
153 
  set_mem8(PARAM0, PARAM1, &breakpoint);
154 
  if (config.cpu.sbuf_len) {
155 
    int t = runtime.sim.mem_cycles;
156 
    runtime.sim.mem_cycles = old_cyc;
157 
    sbuf_store (t- old_cyc);
158 
  }
159 
}
160 
INSTRUCTION (l_sh) {
161 
  int old_cyc = 0;
162 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
163 
  set_mem16(PARAM0, PARAM1, &breakpoint);
164 
  if (config.cpu.sbuf_len) {
165 
    int t = runtime.sim.mem_cycles;
166 
    runtime.sim.mem_cycles = old_cyc;
167 
    sbuf_store (t - old_cyc);
168 
  }
169 
}
170 104 jeremybenn 
INSTRUCTION (l_lws) {
171 
  uint32_t val;
172 
  if (config.cpu.sbuf_len) sbuf_load ();
173 
  val = eval_mem32(PARAM1, &breakpoint);
174 
  /* If eval operand produced exception don't set anything. JPB changed to
175 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
176 
  if (!(except_pending || breakpoint))
177 
    SET_PARAM0(val);
178 
}
179 19 jeremybenn 
INSTRUCTION (l_lwz) {
180 
  uint32_t val;
181 
  if (config.cpu.sbuf_len) sbuf_load ();
182 
  val = eval_mem32(PARAM1, &breakpoint);
183 
  /* If eval operand produced exception don't set anything. JPB changed to
184 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
185 
  if (!(except_pending || breakpoint))
186 
    SET_PARAM0(val);
187 
}
188 
INSTRUCTION (l_lbs) {
189 
  int8_t val;
190 
  if (config.cpu.sbuf_len) sbuf_load ();
191 
  val = eval_mem8(PARAM1, &breakpoint);
192 
  /* If eval operand produced exception don't set anything. JPB changed to
193 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
194 
  if (!(except_pending || breakpoint))
195 
    SET_PARAM0(val);
196 
}
197 
INSTRUCTION (l_lbz) {
198 
  uint8_t val;
199 
  if (config.cpu.sbuf_len) sbuf_load ();
200 
  val = eval_mem8(PARAM1, &breakpoint);
201 
  /* If eval operand produced exception don't set anything. JPB changed to
202 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
203 
  if (!(except_pending || breakpoint))
204 
    SET_PARAM0(val);
205 
}
206 
INSTRUCTION (l_lhs) {
207 
  int16_t val;
208 
  if (config.cpu.sbuf_len) sbuf_load ();
209 
  val = eval_mem16(PARAM1, &breakpoint);
210 
  /* If eval operand produced exception don't set anything. JPB changed to
211 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
212 
  if (!(except_pending || breakpoint))
213 
    SET_PARAM0(val);
214 
}
215 
INSTRUCTION (l_lhz) {
216 
  uint16_t val;
217 
  if (config.cpu.sbuf_len) sbuf_load ();
218 
  val = eval_mem16(PARAM1, &breakpoint);
219 
  /* If eval operand produced exception don't set anything. JPB changed to
220 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
221 
  if (!(except_pending || breakpoint))
222 
    SET_PARAM0(val);
223 
}
224 
INSTRUCTION (l_movhi) {
225 
  SET_PARAM0(PARAM1 << 16);
226 
}
227 
INSTRUCTION (l_and) {
228 
  uorreg_t temp1;
229 
  temp1 = PARAM1 & PARAM2;
230 
  SET_PARAM0(temp1);
231 
}
232 
INSTRUCTION (l_or) {
233 
  uorreg_t temp1;
234 
  temp1 = PARAM1 | PARAM2;
235 
  SET_PARAM0(temp1);
236 
}
237 
INSTRUCTION (l_xor) {
238 127 jeremybenn 
  /* The argument is now specified as unsigned, but historically OR1K has
239 
     always treated the argument as signed (so l.xori rD,rA,-1 can be used in
240 
     the absence of l.not). Use this as the default behavior. This is
241 
     controlled from or32.c. */
242 
  uorreg_t  temp1 = PARAM1 ^ PARAM2;
243 19 jeremybenn 
  SET_PARAM0(temp1);
244 
}
245 
INSTRUCTION (l_sub) {
246 124 jeremybenn 
  orreg_t temp1, temp2, temp3;
247 
 
248 
  temp3 = (orreg_t)PARAM2;
249 
  temp2 = (orreg_t)PARAM1;
250 
  temp1 = temp2 - temp3;
251 
  SET_PARAM0 (temp1);
252 
 
253 
  /* Set overflow if a negative value minus a positive value gave a positive
254 
     sum, or if a positive value minus a negative value gave a negative
255 
     sum. Otherwise clear it */
256 
  if ((((long int) temp2 <  0) &&
257 
       ((long int) temp3 >= 0) &&
258 
       ((long int) temp1 >= 0)) ||
259 
      (((long int) temp2 >= 0) &&
260 
       ((long int) temp3 <  0) &&
261 
       ((long int) temp1 <  0)))
262 
    {
263 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
264 
    }
265 
  else
266 
    {
267 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
268 
    }
269 
 
270 
  /* Set the carry flag if (as unsigned values) the second operand is greater
271 
     than the first. */
272 
  if ((uorreg_t) temp3 > (uorreg_t) temp2)
273 
    {
274 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
275 
    }
276 
  else
277 
    {
278 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
279 
    }
280 
 
281 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
282 
     is set. */
283 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
284 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
285 
    {
286 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
287 
    }
288 19 jeremybenn 
}
289 
/*int mcount = 0;*/
290 
INSTRUCTION (l_mul) {
291 118 jeremybenn 
  orreg_t   temp0, temp1, temp2;
292 
  LONGEST   ltemp0, ltemp1, ltemp2;
293 
  ULONGEST  ultemp0, ultemp1, ultemp2;
294 
 
295 
  /* Args in 32-bit */
296 
  temp2 = (orreg_t) PARAM2;
297 
  temp1 = (orreg_t) PARAM1;
298 
 
299 
  /* Compute initially in 64-bit */
300 
  ltemp1 = (LONGEST) temp1;
301 
  ltemp2 = (LONGEST) temp2;
302 
  ltemp0 = ltemp1 * ltemp2;
303 
 
304 
  temp0  = (orreg_t) (ltemp0  & 0xffffffffLL);
305 
  SET_PARAM0 (temp0);
306 
 
307 
  /* We have 2's complement overflow, if the result is less than the smallest
308 
     possible 32-bit negative number, or greater than the largest possible
309 
     32-bit positive number. */
310 
  if ((ltemp0 < (LONGEST) INT32_MIN) || (ltemp0 > (LONGEST) INT32_MAX))
311 
    {
312 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
313 
    }
314 
  else
315 
    {
316 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
317 
    }
318 
 
319 
  /* We have 1's complement overflow, if, as an unsigned operation, the result
320 
     is greater than the largest possible 32-bit unsigned number. This is
321 
     probably quicker than unpicking the bits of the signed result. */
322 
  ultemp1 = (ULONGEST) temp1 & 0xffffffffULL;
323 
  ultemp2 = (ULONGEST) temp2 & 0xffffffffULL;
324 
  ultemp0 = ultemp1 * ultemp2;
325 
 
326 
  if (ultemp0 > (ULONGEST) UINT32_MAX)
327 
    {
328 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
329 
    }
330 
  else
331 
    {
332 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
333 
    }
334 
 
335 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
336 
     is set. */
337 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
338 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
339 
    {
340 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
341 
    }
342 19 jeremybenn 
}
343 118 jeremybenn 
INSTRUCTION (l_mulu) {
344 
  uorreg_t   temp0, temp1, temp2;
345 
  ULONGEST  ultemp0, ultemp1, ultemp2;
346 
 
347 
  /* Args in 32-bit */
348 
  temp2 = (uorreg_t) PARAM2;
349 
  temp1 = (uorreg_t) PARAM1;
350 
 
351 
  /* Compute initially in 64-bit */
352 
  ultemp1 = (ULONGEST) temp1 & 0xffffffffULL;
353 
  ultemp2 = (ULONGEST) temp2 & 0xffffffffULL;
354 
  ultemp0 = ultemp1 * ultemp2;
355 
 
356 
  temp0  = (uorreg_t) (ultemp0  & 0xffffffffULL);
357 
  SET_PARAM0 (temp0);
358 
 
359 
  /* We never have 2's complement overflow */
360 
  cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
361 
 
362 
  /* We have 1's complement overflow, if the result is greater than the
363 
     largest possible 32-bit unsigned number. */
364 
  if (ultemp0 > (ULONGEST) UINT32_MAX)
365 
    {
366 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
367 
    }
368 
  else
369 
    {
370 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
371 
    }
372 
}
373 19 jeremybenn 
INSTRUCTION (l_div) {
374 118 jeremybenn 
  orreg_t  temp3, temp2, temp1;
375 19 jeremybenn 
 
376 118 jeremybenn 
  temp3 = (orreg_t) PARAM2;
377 
  temp2 = (orreg_t) PARAM1;
378 
 
379 
 /* Check for divide by zero (sets carry) */
380 
  if (0 == temp3)
381 
    {
382 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
383 
    }
384 
  else
385 
    {
386 
      temp1 = temp2 / temp3;
387 
      SET_PARAM0(temp1);
388 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
389 
    }
390 
 
391 
  cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV; /* Never set */
392 
 
393 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
394 
     is set. */
395 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
396 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_CY)  == SPR_SR_CY))
397 
    {
398 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
399 
    }
400 19 jeremybenn 
}
401 
INSTRUCTION (l_divu) {
402 
  uorreg_t temp3, temp2, temp1;
403 
 
404 118 jeremybenn 
  temp3 = (uorreg_t) PARAM2;
405 
  temp2 = (uorreg_t) PARAM1;
406 
 
407 
 /* Check for divide by zero (sets carry) */
408 
  if (0 == temp3)
409 
    {
410 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
411 
    }
412 
  else
413 
    {
414 
      temp1 = temp2 / temp3;
415 
      SET_PARAM0(temp1);
416 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
417 
    }
418 
 
419 
  cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV; /* Never set */
420 
 
421 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
422 
     is set. */
423 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
424 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_CY)  == SPR_SR_CY))
425 
    {
426 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
427 
    }
428 19 jeremybenn 
}
429 
INSTRUCTION (l_sll) {
430 
  uorreg_t temp1;
431 
 
432 
  temp1 = PARAM1 << PARAM2;
433 
  SET_PARAM0(temp1);
434 
  /* runtime.sim.cycles += 2; */
435 
}
436 
INSTRUCTION (l_sra) {
437 
  orreg_t temp1;
438 
 
439 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
440 
  SET_PARAM0(temp1);
441 
  /* runtime.sim.cycles += 2; */
442 
}
443 
INSTRUCTION (l_srl) {
444 
  uorreg_t temp1;
445 
  temp1 = PARAM1 >> PARAM2;
446 
  SET_PARAM0(temp1);
447 
  /* runtime.sim.cycles += 2; */
448 
}
449 122 jeremybenn 
INSTRUCTION (l_ror) {
450 
  uorreg_t temp1;
451 
  temp1  = PARAM1 >> (PARAM2 & 0x1f);
452 
  temp1 |= PARAM1 << (32 - (PARAM2 & 0x1f));
453 
  SET_PARAM0(temp1);
454 
}
455 19 jeremybenn 
INSTRUCTION (l_bf) {
456 
  if (config.bpb.enabled) {
457 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
458 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
459 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
460 
  }
461 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
462 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
463 
    btic_update(pcnext);
464 
    next_delay_insn = 1;
465 
  } else {
466 
    btic_update(cpu_state.pc);
467 
  }
468 
}
469 
INSTRUCTION (l_bnf) {
470 
  if (config.bpb.enabled) {
471 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
472 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
473 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
474 
  }
475 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
476 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
477 
    btic_update(pcnext);
478 
    next_delay_insn = 1;
479 
  } else {
480 
    btic_update(cpu_state.pc);
481 
  }
482 
}
483 
INSTRUCTION (l_j) {
484 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
485 
  next_delay_insn = 1;
486 
}
487 
INSTRUCTION (l_jal) {
488 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
489 
 
490 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
491 
  next_delay_insn = 1;
492 
  if (config.sim.profile) {
493 
    struct label_entry *tmp;
494 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
495 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
496 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
497 
               tmp->name);
498 
    else
499 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
500 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
501 
               cpu_state.pc_delay);
502 
  }
503 
}
504 
INSTRUCTION (l_jalr) {
505 121 jeremybenn 
  /* Badly aligned destination or use of link register triggers an exception */
506 
  uorreg_t  temp1 = PARAM0;
507 
 
508 
  if (REG_PARAM0 == LINK_REGNO)
509 
    {
510 
      except_handle (EXCEPT_ILLEGAL, cpu_state.pc);
511 
    }
512 
  else if ((temp1 & 0x3) != 0)
513 
    {
514 
      except_handle (EXCEPT_ALIGN, cpu_state.pc);
515 
    }
516 
  else
517 
    {
518 
      cpu_state.pc_delay = temp1;
519 
      setsim_reg(LINK_REGNO, cpu_state.pc + 8);
520 
      next_delay_insn = 1;
521 
    }
522 19 jeremybenn 
}
523 
INSTRUCTION (l_jr) {
524 121 jeremybenn 
  /* Badly aligned destination triggers an exception */
525 
  uorreg_t  temp1 = PARAM0;
526 
 
527 
  if ((temp1 & 0x3) != 0)
528 
    {
529 
      except_handle (EXCEPT_ALIGN, cpu_state.pc);
530 
    }
531 
  else
532 
    {
533 
      cpu_state.pc_delay = temp1;
534 
      next_delay_insn = 1;
535 
 
536 
      if (config.sim.profile)
537 
        {
538 
          fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n",
539 
                   runtime.sim.cycles, cpu_state.pc_delay);
540 
        }
541 
    }
542 19 jeremybenn 
}
543 
INSTRUCTION (l_rfe) {
544 
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
545 
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
546 
}
547 
INSTRUCTION (l_nop) {
548 
  uint32_t k = PARAM0;
549 
  switch (k) {
550 
    case NOP_NOP:
551 
      break;
552 
    case NOP_EXIT:
553 220 jeremybenn 
      PRINTFQ("exit(%"PRIdREG")\n", evalsim_reg (3));
554 
      PRINTFQ("@reset : cycles %lld, insn #%lld\n",
555 19 jeremybenn 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
556 220 jeremybenn 
      PRINTFQ("@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
557 19 jeremybenn 
              runtime.cpu.instructions);
558 220 jeremybenn 
      PRINTFQ(" diff  : cycles %lld, insn #%lld\n",
559 19 jeremybenn 
              runtime.sim.cycles - runtime.sim.reset_cycles,
560 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
561 143 jeremybenn 
      if (config.sim.is_library)
562 
        {
563 
          runtime.cpu.halted = 1;
564 
          set_stall_state (1);
565 
        }
566 19 jeremybenn 
      else
567 143 jeremybenn 
        {
568 
          sim_done();
569 
        }
570 19 jeremybenn 
      break;
571 
    case NOP_CNT_RESET:
572 
      PRINTF("****************** counters reset ******************\n");
573 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
574 
      PRINTF("****************** counters reset ******************\n");
575 
      runtime.sim.reset_cycles = runtime.sim.cycles;
576 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
577 
      break;
578 
    case NOP_PUTC:              /*JPB */
579 
      printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
580 
      fflush( stdout );
581 
      break;
582 82 jeremybenn 
    case NOP_GET_TICKS:
583 
      cpu_state.reg[11] = runtime.sim.cycles & 0xffffffff;
584 
      cpu_state.reg[12] = runtime.sim.cycles >> 32;
585 
      break;
586 
    case NOP_GET_PS:
587 
      cpu_state.reg[11] = config.sim.clkcycle_ps;
588 
      break;
589 19 jeremybenn 
    case NOP_REPORT:
590 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
591 
    default:
592 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
593 
      PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
594 
             evalsim_reg(3));
595 
      break;
596 
  }
597 
}
598 
INSTRUCTION (l_sfeq) {
599 
  if(PARAM0 == PARAM1)
600 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
601 
  else
602 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
603 
}
604 
INSTRUCTION (l_sfne) {
605 
  if(PARAM0 != PARAM1)
606 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
607 
  else
608 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
609 
}
610 
INSTRUCTION (l_sfgts) {
611 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
612 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
613 
  else
614 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
615 
}
616 
INSTRUCTION (l_sfges) {
617 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
618 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
619 
  else
620 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
621 
}
622 
INSTRUCTION (l_sflts) {
623 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
624 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
625 
  else
626 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
627 
}
628 
INSTRUCTION (l_sfles) {
629 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
630 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
631 
  else
632 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
633 
}
634 
INSTRUCTION (l_sfgtu) {
635 
  if(PARAM0 > PARAM1)
636 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
637 
  else
638 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
639 
}
640 
INSTRUCTION (l_sfgeu) {
641 
  if(PARAM0 >= PARAM1)
642 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
643 
  else
644 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
645 
}
646 
INSTRUCTION (l_sfltu) {
647 
  if(PARAM0 < PARAM1)
648 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
649 
  else
650 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
651 
}
652 
INSTRUCTION (l_sfleu) {
653 
  if(PARAM0 <= PARAM1)
654 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
655 
  else
656 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
657 
}
658 
INSTRUCTION (l_extbs) {
659 
  int8_t x;
660 
  x = PARAM1;
661 
  SET_PARAM0((orreg_t)x);
662 
}
663 
INSTRUCTION (l_extbz) {
664 
  uint8_t x;
665 
  x = PARAM1;
666 
  SET_PARAM0((uorreg_t)x);
667 
}
668 
INSTRUCTION (l_exths) {
669 
  int16_t x;
670 
  x = PARAM1;
671 
  SET_PARAM0((orreg_t)x);
672 
}
673 
INSTRUCTION (l_exthz) {
674 
  uint16_t x;
675 
  x = PARAM1;
676 
  SET_PARAM0((uorreg_t)x);
677 
}
678 
INSTRUCTION (l_extws) {
679 
  int32_t x;
680 
  x = PARAM1;
681 
  SET_PARAM0((orreg_t)x);
682 
}
683 
INSTRUCTION (l_extwz) {
684 
  uint32_t x;
685 
  x = PARAM1;
686 
  SET_PARAM0((uorreg_t)x);
687 
}
688 
INSTRUCTION (l_mtspr) {
689 123 jeremybenn 
  uint16_t regno = PARAM0 | PARAM2;
690 19 jeremybenn 
  uorreg_t value = PARAM1;
691 
 
692 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
693 
    mtspr(regno, value);
694 
  else {
695 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
696 
    sim_done();
697 
  }
698 
}
699 
INSTRUCTION (l_mfspr) {
700 123 jeremybenn 
  uint16_t regno = PARAM1 | PARAM2;
701 19 jeremybenn 
  uorreg_t value = mfspr(regno);
702 
 
703 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
704 
    SET_PARAM0(value);
705 
  else {
706 
    SET_PARAM0(0);
707 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
708 
    sim_done();
709 
  }
710 
}
711 
INSTRUCTION (l_sys) {
712 
  except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
713 
}
714 
INSTRUCTION (l_trap) {
715 
  /* TODO: some SR related code here! */
716 
  except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
717 
}
718 
INSTRUCTION (l_mac) {
719 
  uorreg_t lo, hi;
720 
  LONGEST l;
721 116 jeremybenn 
  orreg_t x, y, t;
722 19 jeremybenn 
 
723 
  lo = cpu_state.sprs[SPR_MACLO];
724 
  hi = cpu_state.sprs[SPR_MACHI];
725 
  x = PARAM0;
726 
  y = PARAM1;
727 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
728 116 jeremybenn 
 
729 
  /* Compute the temporary as (signed) 32-bits, then sign-extend to 64 when
730 
     adding in. */
731 19 jeremybenn 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
732 116 jeremybenn 
  t = x * y;
733 
  l += (LONGEST) t;
734 19 jeremybenn 
 
735 
  /* This implementation is very fast - it needs only one cycle for mac.  */
736 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
737 
  hi = ((LONGEST)l) >> 32;
738 
  cpu_state.sprs[SPR_MACLO] = lo;
739 
  cpu_state.sprs[SPR_MACHI] = hi;
740 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo); */
741 
}
742 
INSTRUCTION (l_msb) {
743 
  uorreg_t lo, hi;
744 
  LONGEST l;
745 
  orreg_t x, y;
746 
 
747 
  lo = cpu_state.sprs[SPR_MACLO];
748 
  hi = cpu_state.sprs[SPR_MACHI];
749 
  x = PARAM0;
750 
  y = PARAM1;
751 
 
752 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
753 
 
754 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
755 
  l -= x * y;
756 
 
757 
  /* This implementation is very fast - it needs only one cycle for msb.  */
758 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
759 
  hi = ((LONGEST)l) >> 32;
760 
  cpu_state.sprs[SPR_MACLO] = lo;
761 
  cpu_state.sprs[SPR_MACHI] = hi;
762 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
763 
}
764 
INSTRUCTION (l_macrc) {
765 116 jeremybenn 
  orreg_t lo;
766 19 jeremybenn 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
767 
  lo =  cpu_state.sprs[SPR_MACLO];
768 
  //PRINTF ("<%08x>\n", (unsigned long)l);
769 116 jeremybenn 
  SET_PARAM0(lo);
770 19 jeremybenn 
  cpu_state.sprs[SPR_MACLO] = 0;
771 
  cpu_state.sprs[SPR_MACHI] = 0;
772 
}
773 
INSTRUCTION (l_cmov) {
774 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
775 
}
776 
INSTRUCTION (l_ff1) {
777 
  SET_PARAM0(ffs(PARAM1));
778 
}
779 115 jeremybenn 
INSTRUCTION (l_fl1) {
780 
  orreg_t t = (orreg_t)PARAM1;
781 
 
782 
  /* Reverse the word and use ffs */
783 
  t = (((t & 0xaaaaaaaa) >> 1) | ((t & 0x55555555) << 1));
784 
  t = (((t & 0xcccccccc) >> 2) | ((t & 0x33333333) << 2));
785 
  t = (((t & 0xf0f0f0f0) >> 4) | ((t & 0x0f0f0f0f) << 4));
786 
  t = (((t & 0xff00ff00) >> 8) | ((t & 0x00ff00ff) << 8));
787 
  t = ffs ((t >> 16) | (t << 16));
788 
 
789 
  SET_PARAM0 (0 == t ? t : 33 - t);
790 
}
791 19 jeremybenn 
/******* Floating point instructions *******/
792 226 julius 
/* Do calculation, and update FPCSR as required */
793 19 jeremybenn 
/* Single precision */
794 
INSTRUCTION (lf_add_s) {
795 233 julius 
  if (config.cpu.hardfloat) {
796 
  float_set_rm();
797 
  SET_PARAM0(float32_add((unsigned int)PARAM1,(unsigned int)PARAM2));
798 
  float_set_flags();
799 100 julius 
  } else l_invalid();
800 19 jeremybenn 
}
801 
INSTRUCTION (lf_div_s) {
802 100 julius 
  if (config.cpu.hardfloat) {
803 233 julius 
  float_set_rm();
804 
  SET_PARAM0(float32_div((unsigned int)PARAM1,(unsigned int)PARAM2));
805 
  float_set_flags();
806 100 julius 
  } else l_invalid();
807 19 jeremybenn 
}
808 
INSTRUCTION (lf_ftoi_s) {
809 100 julius 
  if (config.cpu.hardfloat) {
810 233 julius 
  float_set_rm();
811 
  SET_PARAM0(float32_to_int32((unsigned int)PARAM1));
812 
  float_set_flags();
813 100 julius 
  } else l_invalid();
814 19 jeremybenn 
}
815 
INSTRUCTION (lf_itof_s) {
816 100 julius 
  if (config.cpu.hardfloat) {
817 233 julius 
  float_set_rm();
818 
  SET_PARAM0(int32_to_float32((unsigned int)PARAM1));
819 
  float_set_flags();
820 100 julius 
  } else l_invalid();
821 19 jeremybenn 
}
822 
INSTRUCTION (lf_madd_s) {
823 100 julius 
  if (config.cpu.hardfloat) {
824 233 julius 
  float_set_rm();
825 
  SET_PARAM0(float32_add((unsigned int)PARAM0, float32_mul((unsigned int)PARAM1,(unsigned int)PARAM2)));
826 
  // Note: this ignores flags from the multiply!
827 
  float_set_flags();
828 100 julius 
  } else l_invalid();
829 19 jeremybenn 
}
830 
INSTRUCTION (lf_mul_s) {
831 100 julius 
  if (config.cpu.hardfloat) {
832 233 julius 
  float_set_rm();
833 
  SET_PARAM0(float32_mul((unsigned int)PARAM1,(unsigned int)PARAM2));
834 
  float_set_flags();
835 100 julius 
  } else l_invalid();
836 19 jeremybenn 
}
837 
INSTRUCTION (lf_rem_s) {
838 100 julius 
  if (config.cpu.hardfloat) {
839 233 julius 
  float_set_rm();
840 
  SET_PARAM0(float32_rem((unsigned int)PARAM1,(unsigned int)PARAM2));
841 
  float_set_flags();
842 100 julius 
  } else l_invalid();
843 19 jeremybenn 
}
844 
INSTRUCTION (lf_sfeq_s) {
845 100 julius 
  if (config.cpu.hardfloat) {
846 233 julius 
  float_set_rm();
847 
  if(float32_eq((unsigned int)PARAM0, (unsigned int)PARAM1))
848 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
849 
  else
850 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
851 233 julius 
  float_set_flags();
852 100 julius 
  } else l_invalid();
853 19 jeremybenn 
}
854 
INSTRUCTION (lf_sfge_s) {
855 100 julius 
  if (config.cpu.hardfloat) {
856 233 julius 
  float_set_rm();
857 
  if((!float32_lt((unsigned int)PARAM0, (unsigned int)PARAM1) &
858 
      !float32_is_nan( (unsigned int)PARAM0) &
859 
      !float32_is_nan( (unsigned int)PARAM1) ) )
860 226 julius 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
861 19 jeremybenn 
  else
862 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
863 233 julius 
  float_set_flags();
864 100 julius 
  } else l_invalid();
865 19 jeremybenn 
}
866 
INSTRUCTION (lf_sfgt_s) {
867 100 julius 
  if (config.cpu.hardfloat) {
868 233 julius 
  float_set_rm();
869 
  if((!float32_le((unsigned int)PARAM0, (unsigned int)PARAM1)  &
870 
      !float32_is_nan( (unsigned int)PARAM0) &
871 
      !float32_is_nan( (unsigned int)PARAM1) ) )
872 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
873 
  else
874 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
875 233 julius 
  float_set_flags();
876 100 julius 
  } else l_invalid();
877 19 jeremybenn 
}
878 
INSTRUCTION (lf_sfle_s) {
879 100 julius 
  if (config.cpu.hardfloat) {
880 233 julius 
  float_set_rm();
881 
  if((float32_le((unsigned int)PARAM0, (unsigned int)PARAM1) &
882 
      !float32_is_nan( (unsigned int)PARAM0) &
883 
      !float32_is_nan( (unsigned int)PARAM1) ) )
884 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
885 
  else
886 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
887 233 julius 
  float_set_flags();
888 100 julius 
  } else l_invalid();
889 19 jeremybenn 
}
890 
INSTRUCTION (lf_sflt_s) {
891 100 julius 
  if (config.cpu.hardfloat) {
892 233 julius 
  float_set_rm();
893 
  if(( float32_lt((unsigned int)PARAM0, (unsigned int)PARAM1) &
894 
       !float32_is_nan( (unsigned int)PARAM0) &
895 
       !float32_is_nan( (unsigned int)PARAM1) ) )
896 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
897 
  else
898 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
899 233 julius 
  float_set_flags();
900 100 julius 
  } else l_invalid();
901 19 jeremybenn 
}
902 
INSTRUCTION (lf_sfne_s) {
903 100 julius 
  if (config.cpu.hardfloat) {
904 233 julius 
  float_set_rm();
905 
  if(!float32_eq((unsigned int)PARAM0, (unsigned int)PARAM1))
906 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
907 
  else
908 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
909 233 julius 
  float_set_flags();
910 100 julius 
  } else l_invalid();
911 19 jeremybenn 
}
912 
INSTRUCTION (lf_sub_s) {
913 100 julius 
  if (config.cpu.hardfloat) {
914 233 julius 
  float_set_rm();
915 
  SET_PARAM0(float32_sub((unsigned int)PARAM1,(unsigned int)PARAM2));
916 
  float_set_flags();
917 100 julius 
  } else l_invalid();
918 19 jeremybenn 
}
919 
 
920 
/******* Custom instructions *******/
921 
INSTRUCTION (l_cust1) {
922 
  /*int destr = current->insn >> 21;
923 
    int src1r = current->insn >> 15;
924 
    int src2r = current->insn >> 9;*/
925 
}
926 
INSTRUCTION (l_cust2) {
927 
}
928 
INSTRUCTION (l_cust3) {
929 
}
930 
INSTRUCTION (l_cust4) {
931 
}
932 100 julius 
INSTRUCTION (lf_cust1) {
933 
}

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