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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 716

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Line No. Rev Author Line
1 19 jeremybenn 
/* insnset.c -- Instruction specific functions.
2 
 
3 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4 
                 2000-2002 Marko Mlinar, markom@opencores.org
5 
   Copyright (C) 2008 Embecosm Limited
6 100 julius 
   Copyright (C) 2009 Jungsook yang, jungsook.yang@uci.edu
7 19 jeremybenn 
 
8 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
9 100 julius 
   Contributor Julius Baxter julius@orsoc.se
10 
 
11 19 jeremybenn 
   This file is part of OpenRISC 1000 Architectural Simulator.
12 
 
13 
   This program is free software; you can redistribute it and/or modify it
14 
   under the terms of the GNU General Public License as published by the Free
15 
   Software Foundation; either version 3 of the License, or (at your option)
16 
   any later version.
17 
 
18 
   This program is distributed in the hope that it will be useful, but WITHOUT
19 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
21 
   more details.
22 
 
23 
   You should have received a copy of the GNU General Public License along
24 
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
25 
 
26 
/* This program is commented throughout in a fashion suitable for processing
27 
   with Doxygen. */
28 
 
29 
 
30 
INSTRUCTION (l_add) {
31 
  orreg_t temp1, temp2, temp3;
32 
  int8_t temp4;
33 
 
34 
  temp2 = (orreg_t)PARAM2;
35 
  temp3 = (orreg_t)PARAM1;
36 
  temp1 = temp2 + temp3;
37 124 jeremybenn 
  SET_PARAM0 (temp1);
38 112 jeremybenn 
 
39 
  /* Set overflow if two negative values gave a positive sum, or if two
40 
     positive values gave a negative sum. Otherwise clear it */
41 
  if ((((long int) temp2 <  0) &&
42 
       ((long int) temp3 <  0) &&
43 
       ((long int) temp1 >= 0)) ||
44 
      (((long int) temp2 >= 0) &&
45 
       ((long int) temp3 >= 0) &&
46 
       ((long int) temp1 <  0)))
47 
    {
48 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
49 
    }
50 
  else
51 
    {
52 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
53 
    }
54 
 
55 
  /* Set the carry flag if (as unsigned values) the result is smaller than
56 
     either operand (if it smaller than one, it will be smaller than both, so
57 
     we need only test one). */
58 19 jeremybenn 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
59 112 jeremybenn 
    {
60 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
61 
    }
62 19 jeremybenn 
  else
63 112 jeremybenn 
    {
64 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
65 
    }
66 19 jeremybenn 
 
67 112 jeremybenn 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
68 
     is set. */
69 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
70 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
71 
    {
72 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
73 
    }
74 
 
75 19 jeremybenn 
  temp4 = temp1;
76 
  if (temp4 == temp1)
77 
    or1k_mstats.byteadd++;
78 
}
79 
INSTRUCTION (l_addc) {
80 
  orreg_t temp1, temp2, temp3;
81 
  int8_t temp4;
82 114 jeremybenn 
  int    carry_in = (cpu_state.sprs[SPR_SR] & SPR_SR_CY) == SPR_SR_CY;
83 
 
84 19 jeremybenn 
  temp2 = (orreg_t)PARAM2;
85 
  temp3 = (orreg_t)PARAM1;
86 
  temp1 = temp2 + temp3;
87 114 jeremybenn 
 
88 
  if(carry_in)
89 
    {
90 
      temp1++;                          /* Add in the carry bit */
91 
    }
92 
 
93 19 jeremybenn 
  SET_PARAM0(temp1);
94 114 jeremybenn 
 
95 
  /* Set overflow if two negative values gave a positive sum, or if two
96 
     positive values gave a negative sum. Otherwise clear it. There are no
97 
     corner cases with the extra bit carried in (unlike the carry flag - see
98 
     below). */
99 
  if ((((long int) temp2 <  0) &&
100 
       ((long int) temp3 <  0) &&
101 
       ((long int) temp1 >= 0)) ||
102 
      (((long int) temp2 >= 0) &&
103 
       ((long int) temp3 >= 0) &&
104 
       ((long int) temp1 <  0)))
105 
    {
106 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
107 
    }
108 19 jeremybenn 
  else
109 114 jeremybenn 
    {
110 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
111 
    }
112 19 jeremybenn 
 
113 114 jeremybenn 
  /* Set the carry flag if (as unsigned values) the result is smaller than
114 
     either operand (if it smaller than one, it will be smaller than both, so
115 
     we need only test one). If there is a carry in, the test should be less
116 
     than or equal, to deal with the 0 + 0xffffffff + c = 0 case (which
117 
     generates a carry). */
118 
  if ((carry_in && ((uorreg_t) temp1 <= (uorreg_t) temp2)) ||
119 
      ((uorreg_t) temp1 < (uorreg_t) temp2))
120 
    {
121 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
122 
    }
123 
  else
124 
    {
125 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
126 
    }
127 
 
128 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
129 
     is set. */
130 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
131 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
132 
    {
133 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
134 
    }
135 
 
136 19 jeremybenn 
  temp4 = temp1;
137 
  if (temp4 == temp1)
138 
    or1k_mstats.byteadd++;
139 
}
140 
INSTRUCTION (l_sw) {
141 
  int old_cyc = 0;
142 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
143 
  set_mem32(PARAM0, PARAM1, &breakpoint);
144 
  if (config.cpu.sbuf_len) {
145 
    int t = runtime.sim.mem_cycles;
146 
    runtime.sim.mem_cycles = old_cyc;
147 
    sbuf_store (t - old_cyc);
148 
  }
149 
}
150 
INSTRUCTION (l_sb) {
151 
  int old_cyc = 0;
152 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
153 
  set_mem8(PARAM0, PARAM1, &breakpoint);
154 
  if (config.cpu.sbuf_len) {
155 
    int t = runtime.sim.mem_cycles;
156 
    runtime.sim.mem_cycles = old_cyc;
157 
    sbuf_store (t- old_cyc);
158 
  }
159 
}
160 
INSTRUCTION (l_sh) {
161 
  int old_cyc = 0;
162 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
163 
  set_mem16(PARAM0, PARAM1, &breakpoint);
164 
  if (config.cpu.sbuf_len) {
165 
    int t = runtime.sim.mem_cycles;
166 
    runtime.sim.mem_cycles = old_cyc;
167 
    sbuf_store (t - old_cyc);
168 
  }
169 
}
170 104 jeremybenn 
INSTRUCTION (l_lws) {
171 
  uint32_t val;
172 
  if (config.cpu.sbuf_len) sbuf_load ();
173 
  val = eval_mem32(PARAM1, &breakpoint);
174 
  /* If eval operand produced exception don't set anything. JPB changed to
175 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
176 
  if (!(except_pending || breakpoint))
177 
    SET_PARAM0(val);
178 
}
179 19 jeremybenn 
INSTRUCTION (l_lwz) {
180 
  uint32_t val;
181 
  if (config.cpu.sbuf_len) sbuf_load ();
182 
  val = eval_mem32(PARAM1, &breakpoint);
183 
  /* If eval operand produced exception don't set anything. JPB changed to
184 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
185 
  if (!(except_pending || breakpoint))
186 
    SET_PARAM0(val);
187 
}
188 
INSTRUCTION (l_lbs) {
189 
  int8_t val;
190 
  if (config.cpu.sbuf_len) sbuf_load ();
191 
  val = eval_mem8(PARAM1, &breakpoint);
192 
  /* If eval operand produced exception don't set anything. JPB changed to
193 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
194 
  if (!(except_pending || breakpoint))
195 
    SET_PARAM0(val);
196 
}
197 
INSTRUCTION (l_lbz) {
198 
  uint8_t val;
199 
  if (config.cpu.sbuf_len) sbuf_load ();
200 
  val = eval_mem8(PARAM1, &breakpoint);
201 
  /* If eval operand produced exception don't set anything. JPB changed to
202 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
203 
  if (!(except_pending || breakpoint))
204 
    SET_PARAM0(val);
205 
}
206 
INSTRUCTION (l_lhs) {
207 
  int16_t val;
208 
  if (config.cpu.sbuf_len) sbuf_load ();
209 
  val = eval_mem16(PARAM1, &breakpoint);
210 
  /* If eval operand produced exception don't set anything. JPB changed to
211 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
212 
  if (!(except_pending || breakpoint))
213 
    SET_PARAM0(val);
214 
}
215 
INSTRUCTION (l_lhz) {
216 
  uint16_t val;
217 
  if (config.cpu.sbuf_len) sbuf_load ();
218 
  val = eval_mem16(PARAM1, &breakpoint);
219 
  /* If eval operand produced exception don't set anything. JPB changed to
220 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
221 
  if (!(except_pending || breakpoint))
222 
    SET_PARAM0(val);
223 
}
224 
INSTRUCTION (l_movhi) {
225 
  SET_PARAM0(PARAM1 << 16);
226 
}
227 
INSTRUCTION (l_and) {
228 
  uorreg_t temp1;
229 
  temp1 = PARAM1 & PARAM2;
230 
  SET_PARAM0(temp1);
231 
}
232 
INSTRUCTION (l_or) {
233 
  uorreg_t temp1;
234 
  temp1 = PARAM1 | PARAM2;
235 
  SET_PARAM0(temp1);
236 
}
237 
INSTRUCTION (l_xor) {
238 127 jeremybenn 
  /* The argument is now specified as unsigned, but historically OR1K has
239 
     always treated the argument as signed (so l.xori rD,rA,-1 can be used in
240 
     the absence of l.not). Use this as the default behavior. This is
241 
     controlled from or32.c. */
242 
  uorreg_t  temp1 = PARAM1 ^ PARAM2;
243 19 jeremybenn 
  SET_PARAM0(temp1);
244 
}
245 
INSTRUCTION (l_sub) {
246 124 jeremybenn 
  orreg_t temp1, temp2, temp3;
247 
 
248 
  temp3 = (orreg_t)PARAM2;
249 
  temp2 = (orreg_t)PARAM1;
250 
  temp1 = temp2 - temp3;
251 
  SET_PARAM0 (temp1);
252 
 
253 
  /* Set overflow if a negative value minus a positive value gave a positive
254 
     sum, or if a positive value minus a negative value gave a negative
255 
     sum. Otherwise clear it */
256 
  if ((((long int) temp2 <  0) &&
257 
       ((long int) temp3 >= 0) &&
258 
       ((long int) temp1 >= 0)) ||
259 
      (((long int) temp2 >= 0) &&
260 
       ((long int) temp3 <  0) &&
261 
       ((long int) temp1 <  0)))
262 
    {
263 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
264 
    }
265 
  else
266 
    {
267 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
268 
    }
269 
 
270 
  /* Set the carry flag if (as unsigned values) the second operand is greater
271 
     than the first. */
272 
  if ((uorreg_t) temp3 > (uorreg_t) temp2)
273 
    {
274 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
275 
    }
276 
  else
277 
    {
278 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
279 
    }
280 
 
281 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
282 
     is set. */
283 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
284 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
285 
    {
286 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
287 
    }
288 19 jeremybenn 
}
289 
/*int mcount = 0;*/
290 
INSTRUCTION (l_mul) {
291 118 jeremybenn 
  orreg_t   temp0, temp1, temp2;
292 
  LONGEST   ltemp0, ltemp1, ltemp2;
293 
  ULONGEST  ultemp0, ultemp1, ultemp2;
294 
 
295 
  /* Args in 32-bit */
296 
  temp2 = (orreg_t) PARAM2;
297 
  temp1 = (orreg_t) PARAM1;
298 
 
299 
  /* Compute initially in 64-bit */
300 
  ltemp1 = (LONGEST) temp1;
301 
  ltemp2 = (LONGEST) temp2;
302 
  ltemp0 = ltemp1 * ltemp2;
303 
 
304 
  temp0  = (orreg_t) (ltemp0  & 0xffffffffLL);
305 
  SET_PARAM0 (temp0);
306 
 
307 
  /* We have 2's complement overflow, if the result is less than the smallest
308 
     possible 32-bit negative number, or greater than the largest possible
309 
     32-bit positive number. */
310 
  if ((ltemp0 < (LONGEST) INT32_MIN) || (ltemp0 > (LONGEST) INT32_MAX))
311 
    {
312 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
313 
    }
314 
  else
315 
    {
316 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
317 
    }
318 
 
319 
  /* We have 1's complement overflow, if, as an unsigned operation, the result
320 
     is greater than the largest possible 32-bit unsigned number. This is
321 
     probably quicker than unpicking the bits of the signed result. */
322 
  ultemp1 = (ULONGEST) temp1 & 0xffffffffULL;
323 
  ultemp2 = (ULONGEST) temp2 & 0xffffffffULL;
324 
  ultemp0 = ultemp1 * ultemp2;
325 
 
326 
  if (ultemp0 > (ULONGEST) UINT32_MAX)
327 
    {
328 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
329 
    }
330 
  else
331 
    {
332 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
333 
    }
334 
 
335 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
336 
     is set. */
337 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
338 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
339 
    {
340 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
341 
    }
342 19 jeremybenn 
}
343 118 jeremybenn 
INSTRUCTION (l_mulu) {
344 
  uorreg_t   temp0, temp1, temp2;
345 
  ULONGEST  ultemp0, ultemp1, ultemp2;
346 
 
347 
  /* Args in 32-bit */
348 
  temp2 = (uorreg_t) PARAM2;
349 
  temp1 = (uorreg_t) PARAM1;
350 
 
351 
  /* Compute initially in 64-bit */
352 
  ultemp1 = (ULONGEST) temp1 & 0xffffffffULL;
353 
  ultemp2 = (ULONGEST) temp2 & 0xffffffffULL;
354 
  ultemp0 = ultemp1 * ultemp2;
355 
 
356 
  temp0  = (uorreg_t) (ultemp0  & 0xffffffffULL);
357 
  SET_PARAM0 (temp0);
358 
 
359 
  /* We never have 2's complement overflow */
360 
  cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
361 
 
362 
  /* We have 1's complement overflow, if the result is greater than the
363 
     largest possible 32-bit unsigned number. */
364 
  if (ultemp0 > (ULONGEST) UINT32_MAX)
365 
    {
366 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
367 
    }
368 
  else
369 
    {
370 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
371 
    }
372 
}
373 19 jeremybenn 
INSTRUCTION (l_div) {
374 118 jeremybenn 
  orreg_t  temp3, temp2, temp1;
375 19 jeremybenn 
 
376 118 jeremybenn 
  temp3 = (orreg_t) PARAM2;
377 
  temp2 = (orreg_t) PARAM1;
378 
 
379 
 /* Check for divide by zero (sets carry) */
380 
  if (0 == temp3)
381 
    {
382 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
383 
    }
384 
  else
385 
    {
386 
      temp1 = temp2 / temp3;
387 
      SET_PARAM0(temp1);
388 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
389 
    }
390 
 
391 
  cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV; /* Never set */
392 
 
393 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
394 
     is set. */
395 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
396 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_CY)  == SPR_SR_CY))
397 
    {
398 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
399 
    }
400 19 jeremybenn 
}
401 
INSTRUCTION (l_divu) {
402 
  uorreg_t temp3, temp2, temp1;
403 
 
404 118 jeremybenn 
  temp3 = (uorreg_t) PARAM2;
405 
  temp2 = (uorreg_t) PARAM1;
406 
 
407 
 /* Check for divide by zero (sets carry) */
408 
  if (0 == temp3)
409 
    {
410 
      cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
411 
    }
412 
  else
413 
    {
414 
      temp1 = temp2 / temp3;
415 
      SET_PARAM0(temp1);
416 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
417 
    }
418 
 
419 
  cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV; /* Never set */
420 
 
421 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
422 
     is set. */
423 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
424 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_CY)  == SPR_SR_CY))
425 
    {
426 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
427 
    }
428 19 jeremybenn 
}
429 
INSTRUCTION (l_sll) {
430 
  uorreg_t temp1;
431 
 
432 
  temp1 = PARAM1 << PARAM2;
433 
  SET_PARAM0(temp1);
434 
  /* runtime.sim.cycles += 2; */
435 
}
436 
INSTRUCTION (l_sra) {
437 
  orreg_t temp1;
438 
 
439 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
440 
  SET_PARAM0(temp1);
441 
  /* runtime.sim.cycles += 2; */
442 
}
443 
INSTRUCTION (l_srl) {
444 
  uorreg_t temp1;
445 
  temp1 = PARAM1 >> PARAM2;
446 
  SET_PARAM0(temp1);
447 
  /* runtime.sim.cycles += 2; */
448 
}
449 122 jeremybenn 
INSTRUCTION (l_ror) {
450 
  uorreg_t temp1;
451 
  temp1  = PARAM1 >> (PARAM2 & 0x1f);
452 
  temp1 |= PARAM1 << (32 - (PARAM2 & 0x1f));
453 
  SET_PARAM0(temp1);
454 
}
455 19 jeremybenn 
INSTRUCTION (l_bf) {
456 
  if (config.bpb.enabled) {
457 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
458 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
459 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
460 
  }
461 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
462 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
463 
    btic_update(pcnext);
464 
    next_delay_insn = 1;
465 
  } else {
466 
    btic_update(cpu_state.pc);
467 
  }
468 
}
469 
INSTRUCTION (l_bnf) {
470 
  if (config.bpb.enabled) {
471 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
472 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
473 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
474 
  }
475 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
476 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
477 
    btic_update(pcnext);
478 
    next_delay_insn = 1;
479 
  } else {
480 
    btic_update(cpu_state.pc);
481 
  }
482 
}
483 
INSTRUCTION (l_j) {
484 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
485 
  next_delay_insn = 1;
486 
}
487 
INSTRUCTION (l_jal) {
488 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
489 
 
490 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
491 
  next_delay_insn = 1;
492 
  if (config.sim.profile) {
493 
    struct label_entry *tmp;
494 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
495 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
496 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
497 
               tmp->name);
498 
    else
499 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
500 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
501 
               cpu_state.pc_delay);
502 
  }
503 
}
504 
INSTRUCTION (l_jalr) {
505 121 jeremybenn 
  /* Badly aligned destination or use of link register triggers an exception */
506 
  uorreg_t  temp1 = PARAM0;
507 
 
508 
  if (REG_PARAM0 == LINK_REGNO)
509 
    {
510 
      except_handle (EXCEPT_ILLEGAL, cpu_state.pc);
511 
    }
512 
  else if ((temp1 & 0x3) != 0)
513 
    {
514 
      except_handle (EXCEPT_ALIGN, cpu_state.pc);
515 
    }
516 
  else
517 
    {
518 
      cpu_state.pc_delay = temp1;
519 
      setsim_reg(LINK_REGNO, cpu_state.pc + 8);
520 
      next_delay_insn = 1;
521 
    }
522 19 jeremybenn 
}
523 
INSTRUCTION (l_jr) {
524 121 jeremybenn 
  /* Badly aligned destination triggers an exception */
525 
  uorreg_t  temp1 = PARAM0;
526 
 
527 
  if ((temp1 & 0x3) != 0)
528 
    {
529 
      except_handle (EXCEPT_ALIGN, cpu_state.pc);
530 
    }
531 
  else
532 
    {
533 
      cpu_state.pc_delay = temp1;
534 
      next_delay_insn = 1;
535 
 
536 
      if (config.sim.profile)
537 
        {
538 
          fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n",
539 
                   runtime.sim.cycles, cpu_state.pc_delay);
540 
        }
541 
    }
542 19 jeremybenn 
}
543 
INSTRUCTION (l_rfe) {
544 
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
545 
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
546 
}
547 
INSTRUCTION (l_nop) {
548 
  uint32_t k = PARAM0;
549 483 jeremybenn 
  switch (k)
550 
    {
551 19 jeremybenn 
    case NOP_NOP:
552 
      break;
553 
    case NOP_EXIT:
554 220 jeremybenn 
      PRINTFQ("exit(%"PRIdREG")\n", evalsim_reg (3));
555 
      PRINTFQ("@reset : cycles %lld, insn #%lld\n",
556 19 jeremybenn 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
557 220 jeremybenn 
      PRINTFQ("@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
558 19 jeremybenn 
              runtime.cpu.instructions);
559 220 jeremybenn 
      PRINTFQ(" diff  : cycles %lld, insn #%lld\n",
560 19 jeremybenn 
              runtime.sim.cycles - runtime.sim.reset_cycles,
561 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
562 143 jeremybenn 
      if (config.sim.is_library)
563 
        {
564 
          runtime.cpu.halted = 1;
565 
          set_stall_state (1);
566 
        }
567 19 jeremybenn 
      else
568 143 jeremybenn 
        {
569 
          sim_done();
570 
        }
571 19 jeremybenn 
      break;
572 483 jeremybenn 
    case NOP_REPORT:
573 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
574 
      break;
575 
    case NOP_PUTC:              /*JPB */
576 
      printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
577 
      fflush( stdout );
578 
      break;
579 19 jeremybenn 
    case NOP_CNT_RESET:
580 
      PRINTF("****************** counters reset ******************\n");
581 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
582 
      PRINTF("****************** counters reset ******************\n");
583 
      runtime.sim.reset_cycles = runtime.sim.cycles;
584 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
585 
      break;
586 82 jeremybenn 
    case NOP_GET_TICKS:
587 
      cpu_state.reg[11] = runtime.sim.cycles & 0xffffffff;
588 
      cpu_state.reg[12] = runtime.sim.cycles >> 32;
589 
      break;
590 
    case NOP_GET_PS:
591 
      cpu_state.reg[11] = config.sim.clkcycle_ps;
592 
      break;
593 460 jeremybenn 
    case NOP_TRACE_ON:
594 
      runtime.sim.hush = 0;
595 
      break;
596 
    case NOP_TRACE_OFF:
597 
      runtime.sim.hush = 1;
598 
      break;
599 483 jeremybenn 
    case NOP_RANDOM:
600 
      cpu_state.reg[11] = (unsigned int) (random () & 0xffffffff);
601 
      break;
602 
    case NOP_OR1KSIM:
603 
      cpu_state.reg[11] = 1;
604 
      break;
605 19 jeremybenn 
    default:
606 
      break;
607 
  }
608 
}
609 
INSTRUCTION (l_sfeq) {
610 
  if(PARAM0 == PARAM1)
611 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
612 
  else
613 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
614 
}
615 
INSTRUCTION (l_sfne) {
616 
  if(PARAM0 != PARAM1)
617 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
618 
  else
619 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
620 
}
621 
INSTRUCTION (l_sfgts) {
622 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
623 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
624 
  else
625 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
626 
}
627 
INSTRUCTION (l_sfges) {
628 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
629 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
630 
  else
631 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
632 
}
633 
INSTRUCTION (l_sflts) {
634 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
635 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
636 
  else
637 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
638 
}
639 
INSTRUCTION (l_sfles) {
640 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
641 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
642 
  else
643 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
644 
}
645 
INSTRUCTION (l_sfgtu) {
646 
  if(PARAM0 > PARAM1)
647 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
648 
  else
649 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
650 
}
651 
INSTRUCTION (l_sfgeu) {
652 
  if(PARAM0 >= PARAM1)
653 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
654 
  else
655 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
656 
}
657 
INSTRUCTION (l_sfltu) {
658 
  if(PARAM0 < PARAM1)
659 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
660 
  else
661 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
662 
}
663 
INSTRUCTION (l_sfleu) {
664 
  if(PARAM0 <= PARAM1)
665 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
666 
  else
667 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
668 
}
669 
INSTRUCTION (l_extbs) {
670 
  int8_t x;
671 
  x = PARAM1;
672 
  SET_PARAM0((orreg_t)x);
673 
}
674 
INSTRUCTION (l_extbz) {
675 
  uint8_t x;
676 
  x = PARAM1;
677 
  SET_PARAM0((uorreg_t)x);
678 
}
679 
INSTRUCTION (l_exths) {
680 
  int16_t x;
681 
  x = PARAM1;
682 
  SET_PARAM0((orreg_t)x);
683 
}
684 
INSTRUCTION (l_exthz) {
685 
  uint16_t x;
686 
  x = PARAM1;
687 
  SET_PARAM0((uorreg_t)x);
688 
}
689 
INSTRUCTION (l_extws) {
690 
  int32_t x;
691 
  x = PARAM1;
692 
  SET_PARAM0((orreg_t)x);
693 
}
694 
INSTRUCTION (l_extwz) {
695 
  uint32_t x;
696 
  x = PARAM1;
697 
  SET_PARAM0((uorreg_t)x);
698 
}
699 
INSTRUCTION (l_mtspr) {
700 123 jeremybenn 
  uint16_t regno = PARAM0 | PARAM2;
701 19 jeremybenn 
  uorreg_t value = PARAM1;
702 
 
703 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
704 
    mtspr(regno, value);
705 
  else {
706 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
707 
    sim_done();
708 
  }
709 
}
710 
INSTRUCTION (l_mfspr) {
711 123 jeremybenn 
  uint16_t regno = PARAM1 | PARAM2;
712 19 jeremybenn 
  uorreg_t value = mfspr(regno);
713 
 
714 556 julius 
  if ((cpu_state.sprs[SPR_SR] & SPR_SR_SM) ||
715 
      // TODO: Check if this SPR should actually be allowed to be read with
716 
      // SR's SM==0 and SUMRA==1
717 
      (!(cpu_state.sprs[SPR_SR] & SPR_SR_SM) &&
718 
       (cpu_state.sprs[SPR_SR] & SPR_SR_SUMRA)))
719 19 jeremybenn 
    SET_PARAM0(value);
720 556 julius 
  else
721 
    {
722 
      SET_PARAM0(0);
723 
      PRINTF("WARNING: trying to read SPR while SR[SUPV] and SR[SUMRA] is cleared.\n");
724 
      sim_done();
725 19 jeremybenn 
  }
726 
}
727 
INSTRUCTION (l_sys) {
728 
  except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
729 
}
730 
INSTRUCTION (l_trap) {
731 
  /* TODO: some SR related code here! */
732 
  except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
733 
}
734 
INSTRUCTION (l_mac) {
735 
  uorreg_t lo, hi;
736 
  LONGEST l;
737 116 jeremybenn 
  orreg_t x, y, t;
738 19 jeremybenn 
 
739 
  lo = cpu_state.sprs[SPR_MACLO];
740 
  hi = cpu_state.sprs[SPR_MACHI];
741 
  x = PARAM0;
742 
  y = PARAM1;
743 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
744 116 jeremybenn 
 
745 
  /* Compute the temporary as (signed) 32-bits, then sign-extend to 64 when
746 
     adding in. */
747 19 jeremybenn 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
748 116 jeremybenn 
  t = x * y;
749 
  l += (LONGEST) t;
750 19 jeremybenn 
 
751 
  /* This implementation is very fast - it needs only one cycle for mac.  */
752 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
753 
  hi = ((LONGEST)l) >> 32;
754 
  cpu_state.sprs[SPR_MACLO] = lo;
755 
  cpu_state.sprs[SPR_MACHI] = hi;
756 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo); */
757 
}
758 
INSTRUCTION (l_msb) {
759 
  uorreg_t lo, hi;
760 
  LONGEST l;
761 
  orreg_t x, y;
762 
 
763 
  lo = cpu_state.sprs[SPR_MACLO];
764 
  hi = cpu_state.sprs[SPR_MACHI];
765 
  x = PARAM0;
766 
  y = PARAM1;
767 
 
768 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
769 
 
770 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
771 
  l -= x * y;
772 
 
773 
  /* This implementation is very fast - it needs only one cycle for msb.  */
774 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
775 
  hi = ((LONGEST)l) >> 32;
776 
  cpu_state.sprs[SPR_MACLO] = lo;
777 
  cpu_state.sprs[SPR_MACHI] = hi;
778 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
779 
}
780 
INSTRUCTION (l_macrc) {
781 116 jeremybenn 
  orreg_t lo;
782 19 jeremybenn 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
783 
  lo =  cpu_state.sprs[SPR_MACLO];
784 
  //PRINTF ("<%08x>\n", (unsigned long)l);
785 116 jeremybenn 
  SET_PARAM0(lo);
786 19 jeremybenn 
  cpu_state.sprs[SPR_MACLO] = 0;
787 
  cpu_state.sprs[SPR_MACHI] = 0;
788 
}
789 
INSTRUCTION (l_cmov) {
790 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
791 
}
792 
INSTRUCTION (l_ff1) {
793 
  SET_PARAM0(ffs(PARAM1));
794 
}
795 115 jeremybenn 
INSTRUCTION (l_fl1) {
796 
  orreg_t t = (orreg_t)PARAM1;
797 
 
798 
  /* Reverse the word and use ffs */
799 
  t = (((t & 0xaaaaaaaa) >> 1) | ((t & 0x55555555) << 1));
800 
  t = (((t & 0xcccccccc) >> 2) | ((t & 0x33333333) << 2));
801 
  t = (((t & 0xf0f0f0f0) >> 4) | ((t & 0x0f0f0f0f) << 4));
802 
  t = (((t & 0xff00ff00) >> 8) | ((t & 0x00ff00ff) << 8));
803 
  t = ffs ((t >> 16) | (t << 16));
804 
 
805 
  SET_PARAM0 (0 == t ? t : 33 - t);
806 
}
807 19 jeremybenn 
/******* Floating point instructions *******/
808 226 julius 
/* Do calculation, and update FPCSR as required */
809 19 jeremybenn 
/* Single precision */
810 
INSTRUCTION (lf_add_s) {
811 233 julius 
  if (config.cpu.hardfloat) {
812 
  float_set_rm();
813 
  SET_PARAM0(float32_add((unsigned int)PARAM1,(unsigned int)PARAM2));
814 
  float_set_flags();
815 100 julius 
  } else l_invalid();
816 19 jeremybenn 
}
817 
INSTRUCTION (lf_div_s) {
818 100 julius 
  if (config.cpu.hardfloat) {
819 233 julius 
  float_set_rm();
820 
  SET_PARAM0(float32_div((unsigned int)PARAM1,(unsigned int)PARAM2));
821 
  float_set_flags();
822 100 julius 
  } else l_invalid();
823 19 jeremybenn 
}
824 
INSTRUCTION (lf_ftoi_s) {
825 100 julius 
  if (config.cpu.hardfloat) {
826 233 julius 
  float_set_rm();
827 
  SET_PARAM0(float32_to_int32((unsigned int)PARAM1));
828 
  float_set_flags();
829 100 julius 
  } else l_invalid();
830 19 jeremybenn 
}
831 
INSTRUCTION (lf_itof_s) {
832 100 julius 
  if (config.cpu.hardfloat) {
833 233 julius 
  float_set_rm();
834 
  SET_PARAM0(int32_to_float32((unsigned int)PARAM1));
835 
  float_set_flags();
836 100 julius 
  } else l_invalid();
837 19 jeremybenn 
}
838 
INSTRUCTION (lf_madd_s) {
839 100 julius 
  if (config.cpu.hardfloat) {
840 233 julius 
  float_set_rm();
841 
  SET_PARAM0(float32_add((unsigned int)PARAM0, float32_mul((unsigned int)PARAM1,(unsigned int)PARAM2)));
842 
  // Note: this ignores flags from the multiply!
843 
  float_set_flags();
844 100 julius 
  } else l_invalid();
845 19 jeremybenn 
}
846 
INSTRUCTION (lf_mul_s) {
847 100 julius 
  if (config.cpu.hardfloat) {
848 233 julius 
  float_set_rm();
849 
  SET_PARAM0(float32_mul((unsigned int)PARAM1,(unsigned int)PARAM2));
850 
  float_set_flags();
851 100 julius 
  } else l_invalid();
852 19 jeremybenn 
}
853 
INSTRUCTION (lf_rem_s) {
854 100 julius 
  if (config.cpu.hardfloat) {
855 233 julius 
  float_set_rm();
856 
  SET_PARAM0(float32_rem((unsigned int)PARAM1,(unsigned int)PARAM2));
857 
  float_set_flags();
858 100 julius 
  } else l_invalid();
859 19 jeremybenn 
}
860 
INSTRUCTION (lf_sfeq_s) {
861 100 julius 
  if (config.cpu.hardfloat) {
862 233 julius 
  float_set_rm();
863 
  if(float32_eq((unsigned int)PARAM0, (unsigned int)PARAM1))
864 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
865 
  else
866 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
867 233 julius 
  float_set_flags();
868 100 julius 
  } else l_invalid();
869 19 jeremybenn 
}
870 
INSTRUCTION (lf_sfge_s) {
871 100 julius 
  if (config.cpu.hardfloat) {
872 233 julius 
  float_set_rm();
873 
  if((!float32_lt((unsigned int)PARAM0, (unsigned int)PARAM1) &
874 
      !float32_is_nan( (unsigned int)PARAM0) &
875 
      !float32_is_nan( (unsigned int)PARAM1) ) )
876 226 julius 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
877 19 jeremybenn 
  else
878 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
879 233 julius 
  float_set_flags();
880 100 julius 
  } else l_invalid();
881 19 jeremybenn 
}
882 
INSTRUCTION (lf_sfgt_s) {
883 100 julius 
  if (config.cpu.hardfloat) {
884 233 julius 
  float_set_rm();
885 
  if((!float32_le((unsigned int)PARAM0, (unsigned int)PARAM1)  &
886 
      !float32_is_nan( (unsigned int)PARAM0) &
887 
      !float32_is_nan( (unsigned int)PARAM1) ) )
888 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
889 
  else
890 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
891 233 julius 
  float_set_flags();
892 100 julius 
  } else l_invalid();
893 19 jeremybenn 
}
894 
INSTRUCTION (lf_sfle_s) {
895 100 julius 
  if (config.cpu.hardfloat) {
896 233 julius 
  float_set_rm();
897 
  if((float32_le((unsigned int)PARAM0, (unsigned int)PARAM1) &
898 
      !float32_is_nan( (unsigned int)PARAM0) &
899 
      !float32_is_nan( (unsigned int)PARAM1) ) )
900 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
901 
  else
902 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
903 233 julius 
  float_set_flags();
904 100 julius 
  } else l_invalid();
905 19 jeremybenn 
}
906 
INSTRUCTION (lf_sflt_s) {
907 100 julius 
  if (config.cpu.hardfloat) {
908 233 julius 
  float_set_rm();
909 
  if(( float32_lt((unsigned int)PARAM0, (unsigned int)PARAM1) &
910 
       !float32_is_nan( (unsigned int)PARAM0) &
911 
       !float32_is_nan( (unsigned int)PARAM1) ) )
912 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
913 
  else
914 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
915 233 julius 
  float_set_flags();
916 100 julius 
  } else l_invalid();
917 19 jeremybenn 
}
918 
INSTRUCTION (lf_sfne_s) {
919 100 julius 
  if (config.cpu.hardfloat) {
920 233 julius 
  float_set_rm();
921 
  if(!float32_eq((unsigned int)PARAM0, (unsigned int)PARAM1))
922 19 jeremybenn 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
923 
  else
924 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
925 233 julius 
  float_set_flags();
926 100 julius 
  } else l_invalid();
927 19 jeremybenn 
}
928 
INSTRUCTION (lf_sub_s) {
929 100 julius 
  if (config.cpu.hardfloat) {
930 233 julius 
  float_set_rm();
931 
  SET_PARAM0(float32_sub((unsigned int)PARAM1,(unsigned int)PARAM2));
932 
  float_set_flags();
933 100 julius 
  } else l_invalid();
934 19 jeremybenn 
}
935 
 
936 
/******* Custom instructions *******/
937 
INSTRUCTION (l_cust1) {
938 
  /*int destr = current->insn >> 21;
939 
    int src1r = current->insn >> 15;
940 
    int src2r = current->insn >> 9;*/
941 
}
942 
INSTRUCTION (l_cust2) {
943 
}
944 
INSTRUCTION (l_cust3) {
945 
}
946 
INSTRUCTION (l_cust4) {
947 
}
948 100 julius 
INSTRUCTION (lf_cust1) {
949 
}

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