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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 86

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Line No. Rev Author Line
1 19 jeremybenn 
/* insnset.c -- Instruction specific functions.
2 
 
3 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4 
                 2000-2002 Marko Mlinar, markom@opencores.org
5 
   Copyright (C) 2008 Embecosm Limited
6 
 
7 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8 
 
9 
   This file is part of OpenRISC 1000 Architectural Simulator.
10 
 
11 
   This program is free software; you can redistribute it and/or modify it
12 
   under the terms of the GNU General Public License as published by the Free
13 
   Software Foundation; either version 3 of the License, or (at your option)
14 
   any later version.
15 
 
16 
   This program is distributed in the hope that it will be useful, but WITHOUT
17 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19 
   more details.
20 
 
21 
   You should have received a copy of the GNU General Public License along
22 
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
23 
 
24 
/* This program is commented throughout in a fashion suitable for processing
25 
   with Doxygen. */
26 
 
27 
 
28 
INSTRUCTION (l_add) {
29 
  orreg_t temp1, temp2, temp3;
30 
  int8_t temp4;
31 
 
32 
  temp2 = (orreg_t)PARAM2;
33 
  temp3 = (orreg_t)PARAM1;
34 
  temp1 = temp2 + temp3;
35 
  SET_PARAM0(temp1);
36 
  SET_OV_FLAG_FN (temp1);
37 
  if (ARITH_SET_FLAG) {
38 
    if(!temp1)
39 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
40 
    else
41 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
42 
  }
43 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
44 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
45 
  else
46 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
47 
 
48 
  temp4 = temp1;
49 
  if (temp4 == temp1)
50 
    or1k_mstats.byteadd++;
51 
}
52 
INSTRUCTION (l_addc) {
53 
  orreg_t temp1, temp2, temp3;
54 
  int8_t temp4;
55 
 
56 
  temp2 = (orreg_t)PARAM2;
57 
  temp3 = (orreg_t)PARAM1;
58 
  temp1 = temp2 + temp3;
59 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
60 
    temp1++;
61 
  SET_PARAM0(temp1);
62 
  SET_OV_FLAG_FN (temp1);
63 
  if (ARITH_SET_FLAG) {
64 
    if(!temp1)
65 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
66 
    else
67 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
68 
  }
69 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
70 
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
71 
  else
72 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
73 
 
74 
  temp4 = temp1;
75 
  if (temp4 == temp1)
76 
    or1k_mstats.byteadd++;
77 
}
78 
INSTRUCTION (l_sw) {
79 
  int old_cyc = 0;
80 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
81 
  set_mem32(PARAM0, PARAM1, &breakpoint);
82 
  if (config.cpu.sbuf_len) {
83 
    int t = runtime.sim.mem_cycles;
84 
    runtime.sim.mem_cycles = old_cyc;
85 
    sbuf_store (t - old_cyc);
86 
  }
87 
}
88 
INSTRUCTION (l_sb) {
89 
  int old_cyc = 0;
90 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
91 
  set_mem8(PARAM0, PARAM1, &breakpoint);
92 
  if (config.cpu.sbuf_len) {
93 
    int t = runtime.sim.mem_cycles;
94 
    runtime.sim.mem_cycles = old_cyc;
95 
    sbuf_store (t- old_cyc);
96 
  }
97 
}
98 
INSTRUCTION (l_sh) {
99 
  int old_cyc = 0;
100 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
101 
  set_mem16(PARAM0, PARAM1, &breakpoint);
102 
  if (config.cpu.sbuf_len) {
103 
    int t = runtime.sim.mem_cycles;
104 
    runtime.sim.mem_cycles = old_cyc;
105 
    sbuf_store (t - old_cyc);
106 
  }
107 
}
108 
INSTRUCTION (l_lwz) {
109 
  uint32_t val;
110 
  if (config.cpu.sbuf_len) sbuf_load ();
111 
  val = eval_mem32(PARAM1, &breakpoint);
112 
  /* If eval operand produced exception don't set anything. JPB changed to
113 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
114 
  if (!(except_pending || breakpoint))
115 
    SET_PARAM0(val);
116 
}
117 
INSTRUCTION (l_lbs) {
118 
  int8_t val;
119 
  if (config.cpu.sbuf_len) sbuf_load ();
120 
  val = eval_mem8(PARAM1, &breakpoint);
121 
  /* If eval operand produced exception don't set anything. JPB changed to
122 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
123 
  if (!(except_pending || breakpoint))
124 
    SET_PARAM0(val);
125 
}
126 
INSTRUCTION (l_lbz) {
127 
  uint8_t val;
128 
  if (config.cpu.sbuf_len) sbuf_load ();
129 
  val = eval_mem8(PARAM1, &breakpoint);
130 
  /* If eval operand produced exception don't set anything. JPB changed to
131 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
132 
  if (!(except_pending || breakpoint))
133 
    SET_PARAM0(val);
134 
}
135 
INSTRUCTION (l_lhs) {
136 
  int16_t val;
137 
  if (config.cpu.sbuf_len) sbuf_load ();
138 
  val = eval_mem16(PARAM1, &breakpoint);
139 
  /* If eval operand produced exception don't set anything. JPB changed to
140 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
141 
  if (!(except_pending || breakpoint))
142 
    SET_PARAM0(val);
143 
}
144 
INSTRUCTION (l_lhz) {
145 
  uint16_t val;
146 
  if (config.cpu.sbuf_len) sbuf_load ();
147 
  val = eval_mem16(PARAM1, &breakpoint);
148 
  /* If eval operand produced exception don't set anything. JPB changed to
149 
     trigger on breakpoint, as well as except_pending (seemed to be a bug). */
150 
  if (!(except_pending || breakpoint))
151 
    SET_PARAM0(val);
152 
}
153 
INSTRUCTION (l_movhi) {
154 
  SET_PARAM0(PARAM1 << 16);
155 
}
156 
INSTRUCTION (l_and) {
157 
  uorreg_t temp1;
158 
  temp1 = PARAM1 & PARAM2;
159 
  SET_OV_FLAG_FN (temp1);
160 
  SET_PARAM0(temp1);
161 
  if (ARITH_SET_FLAG) {
162 
    if(!temp1)
163 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
164 
    else
165 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
166 
  }
167 
}
168 
INSTRUCTION (l_or) {
169 
  uorreg_t temp1;
170 
  temp1 = PARAM1 | PARAM2;
171 
  SET_OV_FLAG_FN (temp1);
172 
  SET_PARAM0(temp1);
173 
}
174 
INSTRUCTION (l_xor) {
175 
  uorreg_t temp1;
176 
  temp1 = PARAM1 ^ PARAM2;
177 
  SET_OV_FLAG_FN (temp1);
178 
  SET_PARAM0(temp1);
179 
}
180 
INSTRUCTION (l_sub) {
181 
  orreg_t temp1;
182 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
183 
  SET_OV_FLAG_FN (temp1);
184 
  SET_PARAM0(temp1);
185 
}
186 
/*int mcount = 0;*/
187 
INSTRUCTION (l_mul) {
188 
  orreg_t temp1;
189 
 
190 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
191 
  SET_OV_FLAG_FN (temp1);
192 
  SET_PARAM0(temp1);
193 
  /*if (!(mcount++ & 1023)) {
194 
    PRINTF ("[%i]\n",mcount);
195 
    }*/
196 
}
197 
INSTRUCTION (l_div) {
198 
  orreg_t temp3, temp2, temp1;
199 
 
200 
  temp3 = PARAM2;
201 
  temp2 = PARAM1;
202 
  if (temp3)
203 
    temp1 = temp2 / temp3;
204 
  else {
205 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
206 
    return;
207 
  }
208 
  SET_OV_FLAG_FN (temp1);
209 
  SET_PARAM0(temp1);
210 
}
211 
INSTRUCTION (l_divu) {
212 
  uorreg_t temp3, temp2, temp1;
213 
 
214 
  temp3 = PARAM2;
215 
  temp2 = PARAM1;
216 
  if (temp3)
217 
    temp1 = temp2 / temp3;
218 
  else {
219 
    except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
220 
    return;
221 
  }
222 
  SET_OV_FLAG_FN (temp1);
223 
  SET_PARAM0(temp1);
224 
  /* runtime.sim.cycles += 16; */
225 
}
226 
INSTRUCTION (l_sll) {
227 
  uorreg_t temp1;
228 
 
229 
  temp1 = PARAM1 << PARAM2;
230 
  SET_OV_FLAG_FN (temp1);
231 
  SET_PARAM0(temp1);
232 
  /* runtime.sim.cycles += 2; */
233 
}
234 
INSTRUCTION (l_sra) {
235 
  orreg_t temp1;
236 
 
237 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
238 
  SET_OV_FLAG_FN (temp1);
239 
  SET_PARAM0(temp1);
240 
  /* runtime.sim.cycles += 2; */
241 
}
242 
INSTRUCTION (l_srl) {
243 
  uorreg_t temp1;
244 
  temp1 = PARAM1 >> PARAM2;
245 
  SET_OV_FLAG_FN (temp1);
246 
  SET_PARAM0(temp1);
247 
  /* runtime.sim.cycles += 2; */
248 
}
249 
INSTRUCTION (l_bf) {
250 
  if (config.bpb.enabled) {
251 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
252 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
253 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
254 
  }
255 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
256 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
257 
    btic_update(pcnext);
258 
    next_delay_insn = 1;
259 
  } else {
260 
    btic_update(cpu_state.pc);
261 
  }
262 
}
263 
INSTRUCTION (l_bnf) {
264 
  if (config.bpb.enabled) {
265 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
266 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
267 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
268 
  }
269 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
270 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
271 
    btic_update(pcnext);
272 
    next_delay_insn = 1;
273 
  } else {
274 
    btic_update(cpu_state.pc);
275 
  }
276 
}
277 
INSTRUCTION (l_j) {
278 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
279 
  next_delay_insn = 1;
280 
}
281 
INSTRUCTION (l_jal) {
282 
  cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
283 
 
284 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
285 
  next_delay_insn = 1;
286 
  if (config.sim.profile) {
287 
    struct label_entry *tmp;
288 
    if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
289 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
290 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
291 
               tmp->name);
292 
    else
293 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
294 
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
295 
               cpu_state.pc_delay);
296 
  }
297 
}
298 
INSTRUCTION (l_jalr) {
299 
  cpu_state.pc_delay = PARAM0;
300 
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
301 
  next_delay_insn = 1;
302 
}
303 
INSTRUCTION (l_jr) {
304 
  cpu_state.pc_delay = PARAM0;
305 
  next_delay_insn = 1;
306 
  if (config.sim.profile)
307 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
308 
             cpu_state.pc_delay);
309 
}
310 
INSTRUCTION (l_rfe) {
311 
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
312 
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
313 
}
314 
INSTRUCTION (l_nop) {
315 
  uint32_t k = PARAM0;
316 
  switch (k) {
317 
    case NOP_NOP:
318 
      break;
319 
    case NOP_EXIT:
320 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
321 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
322 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
323 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
324 
              runtime.cpu.instructions);
325 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
326 
              runtime.sim.cycles - runtime.sim.reset_cycles,
327 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
328 
      if (config.debug.gdb_enabled)
329 
        set_stall_state (1);
330 
      else
331 
        sim_done();
332 
      break;
333 
    case NOP_CNT_RESET:
334 
      PRINTF("****************** counters reset ******************\n");
335 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
336 
      PRINTF("****************** counters reset ******************\n");
337 
      runtime.sim.reset_cycles = runtime.sim.cycles;
338 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
339 
      break;
340 
    case NOP_PUTC:              /*JPB */
341 
      printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
342 
      fflush( stdout );
343 
      break;
344 82 jeremybenn 
    case NOP_GET_TICKS:
345 
      cpu_state.reg[11] = runtime.sim.cycles & 0xffffffff;
346 
      cpu_state.reg[12] = runtime.sim.cycles >> 32;
347 
      break;
348 
    case NOP_GET_PS:
349 
      cpu_state.reg[11] = config.sim.clkcycle_ps;
350 
      break;
351 19 jeremybenn 
    case NOP_REPORT:
352 
      PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
353 
    default:
354 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
355 
      PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
356 
             evalsim_reg(3));
357 
      break;
358 
  }
359 
}
360 
INSTRUCTION (l_sfeq) {
361 
  if(PARAM0 == PARAM1)
362 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
363 
  else
364 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
365 
}
366 
INSTRUCTION (l_sfne) {
367 
  if(PARAM0 != PARAM1)
368 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
369 
  else
370 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
371 
}
372 
INSTRUCTION (l_sfgts) {
373 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
374 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
375 
  else
376 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
377 
}
378 
INSTRUCTION (l_sfges) {
379 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
380 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
381 
  else
382 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
383 
}
384 
INSTRUCTION (l_sflts) {
385 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
386 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
387 
  else
388 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
389 
}
390 
INSTRUCTION (l_sfles) {
391 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
392 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
393 
  else
394 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
395 
}
396 
INSTRUCTION (l_sfgtu) {
397 
  if(PARAM0 > PARAM1)
398 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
399 
  else
400 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
401 
}
402 
INSTRUCTION (l_sfgeu) {
403 
  if(PARAM0 >= PARAM1)
404 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
405 
  else
406 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
407 
}
408 
INSTRUCTION (l_sfltu) {
409 
  if(PARAM0 < PARAM1)
410 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
411 
  else
412 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
413 
}
414 
INSTRUCTION (l_sfleu) {
415 
  if(PARAM0 <= PARAM1)
416 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
417 
  else
418 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
419 
}
420 
INSTRUCTION (l_extbs) {
421 
  int8_t x;
422 
  x = PARAM1;
423 
  SET_PARAM0((orreg_t)x);
424 
}
425 
INSTRUCTION (l_extbz) {
426 
  uint8_t x;
427 
  x = PARAM1;
428 
  SET_PARAM0((uorreg_t)x);
429 
}
430 
INSTRUCTION (l_exths) {
431 
  int16_t x;
432 
  x = PARAM1;
433 
  SET_PARAM0((orreg_t)x);
434 
}
435 
INSTRUCTION (l_exthz) {
436 
  uint16_t x;
437 
  x = PARAM1;
438 
  SET_PARAM0((uorreg_t)x);
439 
}
440 
INSTRUCTION (l_extws) {
441 
  int32_t x;
442 
  x = PARAM1;
443 
  SET_PARAM0((orreg_t)x);
444 
}
445 
INSTRUCTION (l_extwz) {
446 
  uint32_t x;
447 
  x = PARAM1;
448 
  SET_PARAM0((uorreg_t)x);
449 
}
450 
INSTRUCTION (l_mtspr) {
451 
  uint16_t regno = PARAM0 + PARAM2;
452 
  uorreg_t value = PARAM1;
453 
 
454 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
455 
    mtspr(regno, value);
456 
  else {
457 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
458 
    sim_done();
459 
  }
460 
}
461 
INSTRUCTION (l_mfspr) {
462 
  uint16_t regno = PARAM1 + PARAM2;
463 
  uorreg_t value = mfspr(regno);
464 
 
465 
  if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
466 
    SET_PARAM0(value);
467 
  else {
468 
    SET_PARAM0(0);
469 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
470 
    sim_done();
471 
  }
472 
}
473 
INSTRUCTION (l_sys) {
474 
  except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
475 
}
476 
INSTRUCTION (l_trap) {
477 
  /* TODO: some SR related code here! */
478 
  except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
479 
}
480 
INSTRUCTION (l_mac) {
481 
  uorreg_t lo, hi;
482 
  LONGEST l;
483 
  orreg_t x, y;
484 
 
485 
  lo = cpu_state.sprs[SPR_MACLO];
486 
  hi = cpu_state.sprs[SPR_MACHI];
487 
  x = PARAM0;
488 
  y = PARAM1;
489 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
490 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
491 
  l += (LONGEST) x * (LONGEST) y;
492 
 
493 
  /* This implementation is very fast - it needs only one cycle for mac.  */
494 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
495 
  hi = ((LONGEST)l) >> 32;
496 
  cpu_state.sprs[SPR_MACLO] = lo;
497 
  cpu_state.sprs[SPR_MACHI] = hi;
498 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo); */
499 
}
500 
INSTRUCTION (l_msb) {
501 
  uorreg_t lo, hi;
502 
  LONGEST l;
503 
  orreg_t x, y;
504 
 
505 
  lo = cpu_state.sprs[SPR_MACLO];
506 
  hi = cpu_state.sprs[SPR_MACHI];
507 
  x = PARAM0;
508 
  y = PARAM1;
509 
 
510 
/*   PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
511 
 
512 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
513 
  l -= x * y;
514 
 
515 
  /* This implementation is very fast - it needs only one cycle for msb.  */
516 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
517 
  hi = ((LONGEST)l) >> 32;
518 
  cpu_state.sprs[SPR_MACLO] = lo;
519 
  cpu_state.sprs[SPR_MACHI] = hi;
520 
/*   PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
521 
}
522 
INSTRUCTION (l_macrc) {
523 
  uorreg_t lo, hi;
524 
  LONGEST l;
525 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
526 
  lo =  cpu_state.sprs[SPR_MACLO];
527 
  hi =  cpu_state.sprs[SPR_MACHI];
528 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
529 
  l >>= 28;
530 
  //PRINTF ("<%08x>\n", (unsigned long)l);
531 
  SET_PARAM0((orreg_t)l);
532 
  cpu_state.sprs[SPR_MACLO] = 0;
533 
  cpu_state.sprs[SPR_MACHI] = 0;
534 
}
535 
INSTRUCTION (l_cmov) {
536 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
537 
}
538 
INSTRUCTION (l_ff1) {
539 
  SET_PARAM0(ffs(PARAM1));
540 
}
541 
/******* Floating point instructions *******/
542 
/* Single precision */
543 
INSTRUCTION (lf_add_s) {
544 
  SET_PARAM0((float)PARAM1 + (float)PARAM2);
545 
}
546 
INSTRUCTION (lf_div_s) {
547 
  SET_PARAM0((float)PARAM1 / (float)PARAM2);
548 
}
549 
INSTRUCTION (lf_ftoi_s) {
550 
//  set_operand32(0, freg[get_operand(1)], &breakpoint);
551 
}
552 
INSTRUCTION (lf_itof_s) {
553 
//  freg[get_operand(0)] = eval_operand32(1, &breakpoint);
554 
}
555 
INSTRUCTION (lf_madd_s) {
556 
  SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2);
557 
}
558 
INSTRUCTION (lf_mul_s) {
559 
  SET_PARAM0((float)PARAM1 * (float)PARAM2);
560 
}
561 
INSTRUCTION (lf_rem_s) {
562 
  float temp = (float)PARAM1 / (float)PARAM2;
563 
  SET_PARAM0(temp - (uint32_t)temp);
564 
}
565 
INSTRUCTION (lf_sfeq_s) {
566 
  if((float)PARAM0 == (float)PARAM1)
567 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
568 
  else
569 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
570 
}
571 
INSTRUCTION (lf_sfge_s) {
572 
  if((float)PARAM0 >= (float)PARAM1)
573 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
574 
  else
575 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
576 
}
577 
INSTRUCTION (lf_sfgt_s) {
578 
  if((float)PARAM0 > (float)PARAM1)
579 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
580 
  else
581 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
582 
}
583 
INSTRUCTION (lf_sfle_s) {
584 
  if((float)PARAM0 <= (float)PARAM1)
585 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
586 
  else
587 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
588 
}
589 
INSTRUCTION (lf_sflt_s) {
590 
  if((float)PARAM0 < (float)PARAM1)
591 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
592 
  else
593 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
594 
}
595 
INSTRUCTION (lf_sfne_s) {
596 
  if((float)PARAM0 != (float)PARAM1)
597 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
598 
  else
599 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
600 
}
601 
INSTRUCTION (lf_sub_s) {
602 
  SET_PARAM0((float)PARAM1 - (float)PARAM2);
603 
}
604 
 
605 
/******* Custom instructions *******/
606 
INSTRUCTION (l_cust1) {
607 
  /*int destr = current->insn >> 21;
608 
    int src1r = current->insn >> 15;
609 
    int src2r = current->insn >> 9;*/
610 
}
611 
INSTRUCTION (l_cust2) {
612 
}
613 
INSTRUCTION (l_cust3) {
614 
}
615 
INSTRUCTION (l_cust4) {
616 
}

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