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jeremybenn |
/* Table of opcodes for the OpenRISC 1000 ISA.
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Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
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Copyright (C) 2008 Embecosm Limited
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Contributed by Damjan Lampret (lampret@opencores.org).
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is also part of gen_or1k_isa, GDB and GAS.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "port.h"
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/* System includes */
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#include <stdlib.h>
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#include <stdio.h>
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/* Package includes */
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#include "opcode/or32.h"
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/* We treat all letters the same in encode/decode routines so
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we need to assign some characteristics to them like signess etc.*/
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CONST struct or32_letter or32_letters[] = {
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{'A', NUM_UNSIGNED},
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{'B', NUM_UNSIGNED},
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{'D', NUM_UNSIGNED},
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{'I', NUM_SIGNED},
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{'K', NUM_UNSIGNED},
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{'L', NUM_UNSIGNED},
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{'N', NUM_SIGNED},
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{'0', NUM_UNSIGNED},
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{'\0', 0} /* dummy entry */
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};
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/* Opcode encoding:
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machine[31:30]: first two bits of opcode
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00 - neither of source operands is GPR
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01 - second source operand is GPR (rB)
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10 - first source operand is GPR (rA)
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11 - both source operands are GPRs (rA and rB)
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machine[29:26]: next four bits of opcode
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machine[25:00]: instruction operands (specific to individual instruction)
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Recommendation: irrelevant instruction bits should be set with a value of
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bits in same positions of instruction preceding current instruction in the
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code (when assembling).
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*/
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#ifdef HAVE_EXECUTION
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# if SIMPLE_EXECUTION
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# define EFN &l_none
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# define EF(func) &(func)
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# define EFI &l_invalid
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# elif COMPLEX_EXECUTION
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# define EFN "l_none"
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# define EFI "l_invalid"
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# ifdef __GNUC__
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# define EF(func) #func
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# else
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# define EF(func) "func"
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# endif
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# else /* DYNAMIC_EXECUTION */
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# define EFN &l_none
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# define EF(func) &(gen_ ##func)
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# define EFI &gen_l_invalid
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# endif
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#else /* HAVE_EXECUTION */
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# define EFN &l_none
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# define EF(func) EFN
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# define EFI EFN
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#endif /* HAVE_EXECUTION */
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230 |
jeremybenn |
CONST struct or32_opcode or1ksim_or32_opcodes[] = {
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19 |
jeremybenn |
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{"l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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EF (l_j), OR32_IF_DELAY, it_jump},
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{"l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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EF (l_jal), OR32_IF_DELAY, it_jump},
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{"l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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EF (l_bnf), OR32_IF_DELAY | OR32_R_FLAG, it_branch},
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{"l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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EF (l_bf), OR32_IF_DELAY | OR32_R_FLAG, it_branch},
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{"l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK",
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EF (l_nop), 0, it_nop},
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{"l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK",
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EF (l_movhi), 0, it_movimm},
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{"l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000",
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EF (l_macrc), 0, it_mac},
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{"l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK",
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EF (l_sys), 0, it_exception},
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{"l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK",
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EF (l_trap), 0, it_exception},
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{"l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN,
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0, it_unknown},
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{"l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN,
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0, it_unknown},
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{"l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN,
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0, it_unknown},
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{"l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----",
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EF (l_rfe), 0, it_exception},
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{"lv.all_eq.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
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it_unknown},
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{"lv.all_eq.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
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it_unknown},
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{"lv.all_ge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
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it_unknown},
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{"lv.all_ge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
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it_unknown},
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| 128 |
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{"lv.all_gt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0,
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it_unknown},
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{"lv.all_gt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0,
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it_unknown},
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{"lv.all_le.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
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it_unknown},
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{"lv.all_le.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
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it_unknown},
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{"lv.all_lt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0,
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it_unknown},
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{"lv.all_lt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0,
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it_unknown},
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{"lv.all_ne.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0,
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it_unknown},
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{"lv.all_ne.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0,
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it_unknown},
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{"lv.any_eq.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0,
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it_unknown},
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{"lv.any_eq.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0,
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it_unknown},
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{"lv.any_ge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0,
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it_unknown},
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{"lv.any_ge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0,
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it_unknown},
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| 152 |
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{"lv.any_gt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0,
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it_unknown},
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| 154 |
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{"lv.any_gt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0,
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it_unknown},
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| 156 |
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{"lv.any_le.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0,
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| 157 |
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it_unknown},
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| 158 |
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{"lv.any_le.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0,
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| 159 |
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it_unknown},
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| 160 |
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{"lv.any_lt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0,
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| 161 |
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it_unknown},
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| 162 |
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{"lv.any_lt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0,
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it_unknown},
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| 164 |
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{"lv.any_ne.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0,
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| 165 |
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it_unknown},
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| 166 |
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{"lv.any_ne.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0,
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| 167 |
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it_unknown},
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| 168 |
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{"lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0,
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it_unknown},
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| 170 |
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{"lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0,
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it_unknown},
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| 172 |
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{"lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0,
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it_unknown},
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| 174 |
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{"lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0,
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| 175 |
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it_unknown},
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| 176 |
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{"lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0,
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| 177 |
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it_unknown},
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| 178 |
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{"lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0,
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| 179 |
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it_unknown},
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| 180 |
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{"lv.addus.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0,
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| 181 |
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it_unknown},
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| 182 |
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{"lv.addus.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0,
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| 183 |
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it_unknown},
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| 184 |
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{"lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0,
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| 185 |
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it_unknown},
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| 186 |
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{"lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0,
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| 187 |
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it_unknown},
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| 188 |
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{"lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0,
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| 189 |
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it_unknown},
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| 190 |
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{"lv.cmp_eq.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0,
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| 191 |
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it_unknown},
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| 192 |
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{"lv.cmp_eq.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0,
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| 193 |
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it_unknown},
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| 194 |
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{"lv.cmp_ge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0,
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| 195 |
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it_unknown},
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| 196 |
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{"lv.cmp_ge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0,
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| 197 |
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it_unknown},
|
| 198 |
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{"lv.cmp_gt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0,
|
| 199 |
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it_unknown},
|
| 200 |
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{"lv.cmp_gt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0,
|
| 201 |
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it_unknown},
|
| 202 |
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{"lv.cmp_le.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0,
|
| 203 |
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it_unknown},
|
| 204 |
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{"lv.cmp_le.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0,
|
| 205 |
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it_unknown},
|
| 206 |
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{"lv.cmp_lt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0,
|
| 207 |
|
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it_unknown},
|
| 208 |
|
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{"lv.cmp_lt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0,
|
| 209 |
|
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it_unknown},
|
| 210 |
|
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{"lv.cmp_ne.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0,
|
| 211 |
|
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it_unknown},
|
| 212 |
|
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{"lv.cmp_ne.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0,
|
| 213 |
|
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it_unknown},
|
| 214 |
|
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{"lv.madds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0,
|
| 215 |
|
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it_unknown},
|
| 216 |
|
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{"lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0,
|
| 217 |
|
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it_unknown},
|
| 218 |
|
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{"lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0,
|
| 219 |
|
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it_unknown},
|
| 220 |
|
|
{"lv.merge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0,
|
| 221 |
|
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it_unknown},
|
| 222 |
|
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{"lv.merge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0,
|
| 223 |
|
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it_unknown},
|
| 224 |
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{"lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0,
|
| 225 |
|
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it_unknown},
|
| 226 |
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{"lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0,
|
| 227 |
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it_unknown},
|
| 228 |
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{"lv.msubs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0,
|
| 229 |
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it_unknown},
|
| 230 |
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{"lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0,
|
| 231 |
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it_unknown},
|
| 232 |
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{"lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0,
|
| 233 |
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it_unknown},
|
| 234 |
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{"lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0,
|
| 235 |
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it_unknown},
|
| 236 |
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{"lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0,
|
| 237 |
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it_unknown},
|
| 238 |
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{"lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0,
|
| 239 |
|
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it_unknown},
|
| 240 |
|
|
{"lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0,
|
| 241 |
|
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it_unknown},
|
| 242 |
|
|
{"lv.packs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0,
|
| 243 |
|
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it_unknown},
|
| 244 |
|
|
{"lv.packs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0,
|
| 245 |
|
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it_unknown},
|
| 246 |
|
|
{"lv.packus.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0,
|
| 247 |
|
|
it_unknown},
|
| 248 |
|
|
{"lv.packus.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0,
|
| 249 |
|
|
it_unknown},
|
| 250 |
|
|
{"lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0,
|
| 251 |
|
|
it_unknown},
|
| 252 |
|
|
{"lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0,
|
| 253 |
|
|
it_unknown},
|
| 254 |
|
|
{"lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0,
|
| 255 |
|
|
it_unknown},
|
| 256 |
|
|
{"lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0,
|
| 257 |
|
|
it_unknown},
|
| 258 |
|
|
{"lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0,
|
| 259 |
|
|
it_unknown},
|
| 260 |
|
|
{"lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0,
|
| 261 |
|
|
it_unknown},
|
| 262 |
|
|
{"lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0,
|
| 263 |
|
|
it_unknown},
|
| 264 |
|
|
{"lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0,
|
| 265 |
|
|
it_unknown},
|
| 266 |
|
|
{"lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0,
|
| 267 |
|
|
it_unknown},
|
| 268 |
|
|
{"lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0,
|
| 269 |
|
|
it_unknown},
|
| 270 |
|
|
{"lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0,
|
| 271 |
|
|
it_unknown},
|
| 272 |
|
|
{"lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0,
|
| 273 |
|
|
it_unknown},
|
| 274 |
|
|
{"lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0,
|
| 275 |
|
|
it_unknown},
|
| 276 |
|
|
{"lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0,
|
| 277 |
|
|
it_unknown},
|
| 278 |
|
|
{"lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0,
|
| 279 |
|
|
it_unknown},
|
| 280 |
|
|
{"lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0,
|
| 281 |
|
|
it_unknown},
|
| 282 |
|
|
{"lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0,
|
| 283 |
|
|
it_unknown},
|
| 284 |
|
|
{"lv.subus.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0,
|
| 285 |
|
|
it_unknown},
|
| 286 |
|
|
{"lv.subus.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0,
|
| 287 |
|
|
it_unknown},
|
| 288 |
|
|
{"lv.unpack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0,
|
| 289 |
|
|
it_unknown},
|
| 290 |
|
|
{"lv.unpack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0,
|
| 291 |
|
|
it_unknown},
|
| 292 |
|
|
{"lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0,
|
| 293 |
|
|
it_unknown},
|
| 294 |
|
|
{"lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0,
|
| 295 |
|
|
it_unknown},
|
| 296 |
|
|
{"lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0,
|
| 297 |
|
|
it_unknown},
|
| 298 |
|
|
{"lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0,
|
| 299 |
|
|
it_unknown},
|
| 300 |
|
|
{"lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0,
|
| 301 |
|
|
it_unknown},
|
| 302 |
|
|
|
| 303 |
|
|
{"l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----",
|
| 304 |
|
|
EF (l_jr), OR32_IF_DELAY, it_jump},
|
| 305 |
|
|
{"l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----",
|
| 306 |
|
|
EF (l_jalr), OR32_IF_DELAY, it_jump},
|
| 307 |
116 |
jeremybenn |
{"l.maci", "rA,I", "01 0x3 ----- AAAAA IIII IIII IIII IIII",
|
| 308 |
19 |
jeremybenn |
EF (l_mac), 0, it_mac},
|
| 309 |
|
|
{"l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----",
|
| 310 |
|
|
EF (l_cust1), 0, it_unknown},
|
| 311 |
|
|
{"l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----",
|
| 312 |
|
|
EF (l_cust2), 0, it_unknown},
|
| 313 |
|
|
{"l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----",
|
| 314 |
|
|
EF (l_cust3), 0, it_unknown},
|
| 315 |
|
|
{"l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----",
|
| 316 |
|
|
EF (l_cust4), 0, it_unknown},
|
| 317 |
|
|
|
| 318 |
|
|
{"l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI,
|
| 319 |
|
|
0, it_load},
|
| 320 |
|
|
{"l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII",
|
| 321 |
|
|
EF (l_lwz), 0, it_load},
|
| 322 |
104 |
jeremybenn |
{"l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII",
|
| 323 |
|
|
EF (l_lws), 0, it_load},
|
| 324 |
19 |
jeremybenn |
{"l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII",
|
| 325 |
|
|
EF (l_lbz), 0, it_load},
|
| 326 |
|
|
{"l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII",
|
| 327 |
|
|
EF (l_lbs), 0, it_load},
|
| 328 |
|
|
{"l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII",
|
| 329 |
|
|
EF (l_lhz), 0, it_load},
|
| 330 |
|
|
{"l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII",
|
| 331 |
|
|
EF (l_lhs), 0, it_load},
|
| 332 |
|
|
|
| 333 |
|
|
{"l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII",
|
| 334 |
|
|
EF (l_add), OR32_W_FLAG, it_arith},
|
| 335 |
114 |
jeremybenn |
{"l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII",
|
| 336 |
|
|
EF (l_addc), OR32_W_FLAG, it_arith},
|
| 337 |
19 |
jeremybenn |
{"l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
| 338 |
|
|
EF (l_and), OR32_W_FLAG, it_arith},
|
| 339 |
|
|
{"l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
| 340 |
|
|
EF (l_or), 0, it_arith},
|
| 341 |
127 |
jeremybenn |
#if HAVE_UNSIGNED_XORI
|
| 342 |
|
|
{"l.xori", "rD,rA,K", "10 0xB DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
| 343 |
|
|
EF (l_xor), 0, it_arith},
|
| 344 |
|
|
#else
|
| 345 |
19 |
jeremybenn |
{"l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII",
|
| 346 |
|
|
EF (l_xor), 0, it_arith},
|
| 347 |
127 |
jeremybenn |
#endif
|
| 348 |
19 |
jeremybenn |
{"l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII",
|
| 349 |
|
|
EF (l_mul), 0, it_arith},
|
| 350 |
|
|
{"l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
| 351 |
|
|
EF (l_mfspr), 0, it_move},
|
| 352 |
|
|
{"l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL",
|
| 353 |
|
|
EF (l_sll), 0, it_shift},
|
| 354 |
|
|
{"l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL",
|
| 355 |
|
|
EF (l_srl), 0, it_shift},
|
| 356 |
|
|
{"l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL",
|
| 357 |
|
|
EF (l_sra), 0, it_shift},
|
| 358 |
122 |
jeremybenn |
{"l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL",
|
| 359 |
|
|
EF (l_ror), 0, it_shift},
|
| 360 |
19 |
jeremybenn |
|
| 361 |
|
|
{"l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII",
|
| 362 |
|
|
EF (l_sfeq), OR32_W_FLAG, it_compare},
|
| 363 |
|
|
{"l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII",
|
| 364 |
|
|
EF (l_sfne), OR32_W_FLAG, it_compare},
|
| 365 |
|
|
{"l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII",
|
| 366 |
|
|
EF (l_sfgtu), OR32_W_FLAG, it_compare},
|
| 367 |
|
|
{"l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII",
|
| 368 |
|
|
EF (l_sfgeu), OR32_W_FLAG, it_compare},
|
| 369 |
|
|
{"l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII",
|
| 370 |
|
|
EF (l_sfltu), OR32_W_FLAG, it_compare},
|
| 371 |
|
|
{"l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII",
|
| 372 |
|
|
EF (l_sfleu), OR32_W_FLAG, it_compare},
|
| 373 |
|
|
{"l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII",
|
| 374 |
|
|
EF (l_sfgts), OR32_W_FLAG, it_compare},
|
| 375 |
|
|
{"l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII",
|
| 376 |
|
|
EF (l_sfges), OR32_W_FLAG, it_compare},
|
| 377 |
|
|
{"l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII",
|
| 378 |
|
|
EF (l_sflts), OR32_W_FLAG, it_compare},
|
| 379 |
|
|
{"l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII",
|
| 380 |
|
|
EF (l_sfles), OR32_W_FLAG, it_compare},
|
| 381 |
|
|
|
| 382 |
|
|
{"l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK",
|
| 383 |
|
|
EF (l_mtspr), 0, it_move},
|
| 384 |
|
|
{"l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1",
|
| 385 |
|
|
EF (l_mac), 0, it_mac},
|
| 386 |
|
|
{"l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2",
|
| 387 |
|
|
EF (l_msb), 0, it_mac},
|
| 388 |
|
|
|
| 389 |
|
|
{"lf.add.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x0",
|
| 390 |
|
|
EF (lf_add_s), 0, it_float},
|
| 391 |
|
|
{"lf.sub.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x1",
|
| 392 |
|
|
EF (lf_sub_s), 0, it_float},
|
| 393 |
|
|
{"lf.mul.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x2",
|
| 394 |
|
|
EF (lf_mul_s), 0, it_float},
|
| 395 |
|
|
{"lf.div.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x3",
|
| 396 |
|
|
EF (lf_div_s), 0, it_float},
|
| 397 |
|
|
{"lf.itof.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x4",
|
| 398 |
|
|
EF (lf_itof_s), 0, it_float},
|
| 399 |
|
|
{"lf.ftoi.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x5",
|
| 400 |
|
|
EF (lf_ftoi_s), 0, it_float},
|
| 401 |
|
|
{"lf.rem.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x6",
|
| 402 |
|
|
EF (lf_rem_s), 0, it_float},
|
| 403 |
|
|
{"lf.madd.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x7",
|
| 404 |
|
|
EF (lf_madd_s), 0, it_float},
|
| 405 |
|
|
{"lf.sfeq.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x8",
|
| 406 |
|
|
EF (lf_sfeq_s), 0, it_float},
|
| 407 |
|
|
{"lf.sfne.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x9",
|
| 408 |
|
|
EF (lf_sfne_s), 0, it_float},
|
| 409 |
|
|
{"lf.sfgt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xA",
|
| 410 |
|
|
EF (lf_sfgt_s), 0, it_float},
|
| 411 |
|
|
{"lf.sfge.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xB",
|
| 412 |
|
|
EF (lf_sfge_s), 0, it_float},
|
| 413 |
|
|
{"lf.sflt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xC",
|
| 414 |
|
|
EF (lf_sflt_s), 0, it_float},
|
| 415 |
|
|
{"lf.sfle.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xD",
|
| 416 |
|
|
EF (lf_sfle_s), 0, it_float},
|
| 417 |
|
|
{"lf.cust1.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xD ----", EFI,
|
| 418 |
|
|
0, it_float},
|
| 419 |
|
|
|
| 420 |
|
|
{"lf.add.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
|
| 421 |
|
|
it_float},
|
| 422 |
|
|
{"lf.sub.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
|
| 423 |
|
|
it_float},
|
| 424 |
|
|
{"lf.mul.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
|
| 425 |
|
|
it_float},
|
| 426 |
|
|
{"lf.div.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
|
| 427 |
|
|
it_float},
|
| 428 |
|
|
{"lf.itof.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x4", EFI, 0,
|
| 429 |
|
|
it_float},
|
| 430 |
|
|
{"lf.ftoi.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x5", EFI, 0,
|
| 431 |
|
|
it_float},
|
| 432 |
|
|
{"lf.rem.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
|
| 433 |
|
|
it_float},
|
| 434 |
|
|
{"lf.madd.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
|
| 435 |
|
|
it_float},
|
| 436 |
|
|
{"lf.sfeq.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0,
|
| 437 |
|
|
it_float},
|
| 438 |
|
|
{"lf.sfne.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0,
|
| 439 |
|
|
it_float},
|
| 440 |
|
|
{"lf.sfgt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0,
|
| 441 |
|
|
it_float},
|
| 442 |
|
|
{"lf.sfge.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0,
|
| 443 |
|
|
it_float},
|
| 444 |
|
|
{"lf.sflt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0,
|
| 445 |
|
|
it_float},
|
| 446 |
|
|
{"lf.sfle.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0,
|
| 447 |
|
|
it_float},
|
| 448 |
|
|
{"lf.cust1.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xE ----", EFI, 0,
|
| 449 |
|
|
it_float},
|
| 450 |
|
|
|
| 451 |
|
|
{"l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI,
|
| 452 |
|
|
0, it_store},
|
| 453 |
|
|
{"l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII",
|
| 454 |
|
|
EF (l_sw), 0, it_store},
|
| 455 |
|
|
{"l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII",
|
| 456 |
|
|
EF (l_sb), 0, it_store},
|
| 457 |
|
|
{"l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII",
|
| 458 |
|
|
EF (l_sh), 0, it_store},
|
| 459 |
|
|
|
| 460 |
|
|
{"l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0",
|
| 461 |
|
|
EF (l_add), OR32_W_FLAG, it_arith},
|
| 462 |
|
|
{"l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1",
|
| 463 |
|
|
EF (l_addc), OR32_W_FLAG, it_arith},
|
| 464 |
|
|
{"l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2",
|
| 465 |
|
|
EF (l_sub), 0, it_arith},
|
| 466 |
|
|
{"l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3",
|
| 467 |
|
|
EF (l_and), OR32_W_FLAG, it_arith},
|
| 468 |
|
|
{"l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4",
|
| 469 |
|
|
EF (l_or), 0, it_arith},
|
| 470 |
|
|
{"l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5",
|
| 471 |
|
|
EF (l_xor), 0, it_arith},
|
| 472 |
|
|
{"l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6",
|
| 473 |
|
|
EF (l_mul), 0, it_arith},
|
| 474 |
|
|
|
| 475 |
|
|
{"l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8",
|
| 476 |
|
|
EF (l_sll), 0, it_shift},
|
| 477 |
|
|
{"l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8",
|
| 478 |
|
|
EF (l_srl), 0, it_shift},
|
| 479 |
|
|
{"l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8",
|
| 480 |
|
|
EF (l_sra), 0, it_shift},
|
| 481 |
122 |
jeremybenn |
{"l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8",
|
| 482 |
|
|
EF (l_ror), 0, it_shift},
|
| 483 |
19 |
jeremybenn |
{"l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x9",
|
| 484 |
|
|
EF (l_div), 0, it_arith},
|
| 485 |
|
|
{"l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xA",
|
| 486 |
|
|
EF (l_divu), 0, it_arith},
|
| 487 |
118 |
jeremybenn |
{"l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB",
|
| 488 |
|
|
EF (l_mulu), 0, it_arith},
|
| 489 |
19 |
jeremybenn |
{"l.extbs", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xC",
|
| 490 |
|
|
EF (l_extbs), 0, it_move},
|
| 491 |
|
|
{"l.exths", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xC",
|
| 492 |
|
|
EF (l_exths), 0, it_move},
|
| 493 |
|
|
{"l.extws", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xD",
|
| 494 |
|
|
EF (l_extws), 0, it_move},
|
| 495 |
|
|
{"l.extbz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 11-- 0xC",
|
| 496 |
|
|
EF (l_extbz), 0, it_move},
|
| 497 |
|
|
{"l.exthz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 10-- 0xC",
|
| 498 |
|
|
EF (l_exthz), 0, it_move},
|
| 499 |
|
|
{"l.extwz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xD",
|
| 500 |
|
|
EF (l_extwz), 0, it_move},
|
| 501 |
|
|
{"l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE",
|
| 502 |
|
|
EF (l_cmov), OR32_R_FLAG, it_move},
|
| 503 |
|
|
{"l.ff1", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 ---- 0xF",
|
| 504 |
|
|
EF (l_ff1), 0, it_arith},
|
| 505 |
115 |
jeremybenn |
{"l.fl1", "rD,rA", "11 0x8 DDDDD AAAAA ---- --01 ---- 0xF",
|
| 506 |
|
|
EF (l_fl1), 0, it_arith},
|
| 507 |
19 |
jeremybenn |
|
| 508 |
|
|
{"l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----",
|
| 509 |
|
|
EF (l_sfeq), OR32_W_FLAG, it_compare},
|
| 510 |
|
|
{"l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----",
|
| 511 |
|
|
EF (l_sfne), OR32_W_FLAG, it_compare},
|
| 512 |
|
|
{"l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----",
|
| 513 |
|
|
EF (l_sfgtu), OR32_W_FLAG, it_compare},
|
| 514 |
|
|
{"l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----",
|
| 515 |
|
|
EF (l_sfgeu), OR32_W_FLAG, it_compare},
|
| 516 |
|
|
{"l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----",
|
| 517 |
|
|
EF (l_sfltu), OR32_W_FLAG, it_compare},
|
| 518 |
|
|
{"l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----",
|
| 519 |
|
|
EF (l_sfleu), OR32_W_FLAG, it_compare},
|
| 520 |
|
|
{"l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----",
|
| 521 |
|
|
EF (l_sfgts), OR32_W_FLAG, it_compare},
|
| 522 |
|
|
{"l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----",
|
| 523 |
|
|
EF (l_sfges), OR32_W_FLAG, it_compare},
|
| 524 |
|
|
{"l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----",
|
| 525 |
|
|
EF (l_sflts), OR32_W_FLAG, it_compare},
|
| 526 |
|
|
{"l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----",
|
| 527 |
|
|
EF (l_sfles), OR32_W_FLAG, it_compare},
|
| 528 |
|
|
|
| 529 |
|
|
{"l.cust5", "rD,rA,rB,L,K", "11 0xC DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI,
|
| 530 |
|
|
0, it_unknown},
|
| 531 |
|
|
{"l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI,
|
| 532 |
|
|
0, it_unknown},
|
| 533 |
|
|
{"l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI,
|
| 534 |
|
|
0, it_unknown},
|
| 535 |
|
|
{"l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI,
|
| 536 |
|
|
0, it_unknown},
|
| 537 |
|
|
|
| 538 |
|
|
/* This section should not be defined in or1ksim, since it contains duplicates,
|
| 539 |
|
|
which would cause machine builder to complain. */
|
| 540 |
|
|
#ifdef HAS_CUST
|
| 541 |
|
|
{"l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI,
|
| 542 |
|
|
0, it_unknown},
|
| 543 |
|
|
{"l.cust5_2", "rD,rA", "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI,
|
| 544 |
|
|
0, it_unknown},
|
| 545 |
|
|
{"l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
| 546 |
|
|
0, it_unknown},
|
| 547 |
|
|
|
| 548 |
|
|
{"l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI,
|
| 549 |
|
|
0, it_unknown},
|
| 550 |
|
|
{"l.cust6_2", "rD,rA", "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI,
|
| 551 |
|
|
0, it_unknown},
|
| 552 |
|
|
{"l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
| 553 |
|
|
0, it_unknown},
|
| 554 |
|
|
|
| 555 |
|
|
{"l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI,
|
| 556 |
|
|
0, it_unknown},
|
| 557 |
|
|
{"l.cust7_2", "rD,rA", "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI,
|
| 558 |
|
|
0, it_unknown},
|
| 559 |
|
|
{"l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
| 560 |
|
|
0, it_unknown},
|
| 561 |
|
|
|
| 562 |
|
|
{"l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI,
|
| 563 |
|
|
0, it_unknown},
|
| 564 |
|
|
{"l.cust8_2", "rD,rA", "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI,
|
| 565 |
|
|
0, it_unknown},
|
| 566 |
|
|
{"l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
| 567 |
|
|
0, it_unknown},
|
| 568 |
|
|
#endif
|
| 569 |
|
|
|
| 570 |
|
|
{"", "", "", EFI, 0, 0} /* Dummy entry, not included in num_opcodes. This
|
| 571 |
|
|
* lets code examine entry i+1 without checking
|
| 572 |
|
|
* if we've run off the end of the table. */
|
| 573 |
|
|
};
|
| 574 |
|
|
|
| 575 |
|
|
#undef EFI
|
| 576 |
|
|
#undef EFN
|
| 577 |
|
|
#undef EF
|
| 578 |
|
|
|
| 579 |
230 |
jeremybenn |
static CONST int NUM_OPCODES =
|
| 580 |
|
|
((sizeof (or1ksim_or32_opcodes)) / (sizeof (struct or32_opcode))) - 1;
|
| 581 |
19 |
jeremybenn |
|
| 582 |
|
|
/* Calculates instruction length in bytes. Always 4 for OR32. */
|
| 583 |
|
|
int
|
| 584 |
230 |
jeremybenn |
or1ksim_insn_len (int insn_index)
|
| 585 |
19 |
jeremybenn |
{
|
| 586 |
|
|
insn_index = 0; /* Just to get rid that warning. */
|
| 587 |
|
|
return 4;
|
| 588 |
|
|
}
|
| 589 |
|
|
|
| 590 |
|
|
/* Is individual insn's operand signed or unsigned? */
|
| 591 |
230 |
jeremybenn |
static int
|
| 592 |
19 |
jeremybenn |
letter_signed (char l)
|
| 593 |
|
|
{
|
| 594 |
|
|
CONST struct or32_letter *pletter;
|
| 595 |
|
|
|
| 596 |
|
|
for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
|
| 597 |
|
|
if (pletter->letter == l)
|
| 598 |
|
|
return pletter->sign;
|
| 599 |
|
|
|
| 600 |
|
|
printf ("letter_signed(%c): Unknown letter.\n", l);
|
| 601 |
|
|
return 0;
|
| 602 |
|
|
}
|
| 603 |
|
|
|
| 604 |
|
|
/* Simple cache for letter ranges */
|
| 605 |
|
|
static int range_cache[256] = { 0 };
|
| 606 |
|
|
|
| 607 |
|
|
/* Number of letters in the individual lettered operand. */
|
| 608 |
230 |
jeremybenn |
static int
|
| 609 |
19 |
jeremybenn |
letter_range (char l)
|
| 610 |
|
|
{
|
| 611 |
|
|
CONST struct or32_opcode *pinsn;
|
| 612 |
|
|
char *enc;
|
| 613 |
|
|
int range = 0;
|
| 614 |
|
|
|
| 615 |
|
|
/* Is value cached? */
|
| 616 |
|
|
if ((range = range_cache[(unsigned char) l]))
|
| 617 |
|
|
return range;
|
| 618 |
|
|
|
| 619 |
230 |
jeremybenn |
for (pinsn = or1ksim_or32_opcodes; strlen (pinsn->name); pinsn++)
|
| 620 |
19 |
jeremybenn |
{
|
| 621 |
|
|
if (strchr (pinsn->encoding, l))
|
| 622 |
|
|
{
|
| 623 |
|
|
for (enc = pinsn->encoding; *enc != '\0'; enc++)
|
| 624 |
|
|
if ((*enc == '0') && (*(enc + 1) == 'x'))
|
| 625 |
|
|
enc += 2;
|
| 626 |
|
|
else if (*enc == l)
|
| 627 |
|
|
range++;
|
| 628 |
|
|
return range_cache[(unsigned char) l] = range;
|
| 629 |
|
|
}
|
| 630 |
|
|
}
|
| 631 |
|
|
|
| 632 |
|
|
printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
|
| 633 |
|
|
exit (1);
|
| 634 |
|
|
}
|
| 635 |
|
|
|
| 636 |
|
|
/* Returns name of the specified instruction index */
|
| 637 |
|
|
CONST char *
|
| 638 |
230 |
jeremybenn |
or1ksim_insn_name (int index)
|
| 639 |
19 |
jeremybenn |
{
|
| 640 |
230 |
jeremybenn |
if (index >= 0 && index < NUM_OPCODES)
|
| 641 |
|
|
return or1ksim_or32_opcodes[index].name;
|
| 642 |
19 |
jeremybenn |
else
|
| 643 |
|
|
return "???";
|
| 644 |
|
|
}
|
| 645 |
|
|
|
| 646 |
|
|
/*** Finite automata for instruction decoding building code ***/
|
| 647 |
|
|
|
| 648 |
|
|
/* Find symbols in encoding. */
|
| 649 |
230 |
jeremybenn |
static unsigned long
|
| 650 |
19 |
jeremybenn |
insn_extract (param_ch, enc_initial)
|
| 651 |
|
|
char param_ch;
|
| 652 |
|
|
char *enc_initial;
|
| 653 |
|
|
{
|
| 654 |
|
|
char *enc;
|
| 655 |
|
|
unsigned long ret = 0;
|
| 656 |
|
|
unsigned opc_pos = 32;
|
| 657 |
|
|
for (enc = enc_initial; *enc != '\0';)
|
| 658 |
|
|
if ((*enc == '0') && (*(enc + 1) == 'x'))
|
| 659 |
|
|
{
|
| 660 |
|
|
unsigned long tmp = strtol (enc + 2, NULL, 16);
|
| 661 |
|
|
opc_pos -= 4;
|
| 662 |
|
|
if (param_ch == '0' || param_ch == '1')
|
| 663 |
|
|
{
|
| 664 |
|
|
if (param_ch == '0')
|
| 665 |
|
|
tmp = 15 - tmp;
|
| 666 |
|
|
ret |= tmp << opc_pos;
|
| 667 |
|
|
}
|
| 668 |
|
|
enc += 3;
|
| 669 |
|
|
}
|
| 670 |
|
|
else
|
| 671 |
|
|
{
|
| 672 |
240 |
julius |
if (*enc == '0' || *enc == '1' || *enc == '-' || isalpha ((int)*enc))
|
| 673 |
19 |
jeremybenn |
{
|
| 674 |
|
|
opc_pos--;
|
| 675 |
|
|
if (param_ch == *enc)
|
| 676 |
|
|
ret |= 1 << opc_pos;
|
| 677 |
|
|
}
|
| 678 |
|
|
enc++;
|
| 679 |
|
|
}
|
| 680 |
|
|
return ret;
|
| 681 |
|
|
}
|
| 682 |
|
|
|
| 683 |
|
|
#define MAX_AUTOMATA_SIZE (1200)
|
| 684 |
|
|
#define MAX_OP_TABLE_SIZE (1200)
|
| 685 |
|
|
#define MAX_LEN (8)
|
| 686 |
|
|
|
| 687 |
|
|
#ifndef MIN
|
| 688 |
|
|
# define MIN(x,y) ((x) < (y) ? (x) : (y))
|
| 689 |
|
|
#endif
|
| 690 |
|
|
|
| 691 |
230 |
jeremybenn |
unsigned long *or1ksim_automata;
|
| 692 |
19 |
jeremybenn |
int nuncovered;
|
| 693 |
|
|
int curpass = 0;
|
| 694 |
|
|
|
| 695 |
|
|
/* MM: Struct that holds runtime build information about instructions. */
|
| 696 |
230 |
jeremybenn |
struct temp_insn_struct *or1ksim_ti;
|
| 697 |
19 |
jeremybenn |
|
| 698 |
230 |
jeremybenn |
static struct insn_op_struct *op_data;
|
| 699 |
19 |
jeremybenn |
|
| 700 |
230 |
jeremybenn |
struct insn_op_struct **or1ksim_op_start;
|
| 701 |
|
|
|
| 702 |
19 |
jeremybenn |
static void
|
| 703 |
|
|
or32_debug (int level, const char *format, ...)
|
| 704 |
|
|
{
|
| 705 |
|
|
#if DEBUG
|
| 706 |
|
|
char *p;
|
| 707 |
|
|
va_list ap;
|
| 708 |
|
|
|
| 709 |
|
|
if ((p = malloc (1000)) == NULL)
|
| 710 |
|
|
return;
|
| 711 |
|
|
va_start (ap, format);
|
| 712 |
|
|
(void) vsnprintf (p, 1000, format, ap);
|
| 713 |
|
|
va_end (ap);
|
| 714 |
|
|
printf ("%s\n", p);
|
| 715 |
|
|
fflush (stdout);
|
| 716 |
|
|
free (p);
|
| 717 |
|
|
#endif
|
| 718 |
|
|
}
|
| 719 |
|
|
|
| 720 |
|
|
/* Recursive utility function used to find best match and to build automata. */
|
| 721 |
|
|
static unsigned long *
|
| 722 |
|
|
cover_insn (unsigned long *cur, int pass, unsigned int mask)
|
| 723 |
|
|
{
|
| 724 |
|
|
int best_first = 0, best_len = 0, i, last_match = -1, ninstr = 0;
|
| 725 |
|
|
unsigned long cur_mask = mask;
|
| 726 |
|
|
unsigned long *next;
|
| 727 |
|
|
|
| 728 |
230 |
jeremybenn |
for (i = 0; i < NUM_OPCODES; i++)
|
| 729 |
|
|
if (or1ksim_ti[i].in_pass == pass)
|
| 730 |
19 |
jeremybenn |
{
|
| 731 |
230 |
jeremybenn |
cur_mask &= or1ksim_ti[i].insn_mask;
|
| 732 |
19 |
jeremybenn |
ninstr++;
|
| 733 |
|
|
last_match = i;
|
| 734 |
|
|
}
|
| 735 |
|
|
|
| 736 |
|
|
or32_debug (8, "%08X %08lX\n", mask, cur_mask);
|
| 737 |
|
|
if (ninstr == 0)
|
| 738 |
|
|
return 0;
|
| 739 |
|
|
if (ninstr == 1)
|
| 740 |
|
|
{
|
| 741 |
|
|
/* Leaf holds instruction index. */
|
| 742 |
230 |
jeremybenn |
or32_debug (8, "%i>I%i %s\n", cur - or1ksim_automata, last_match,
|
| 743 |
|
|
or1ksim_or32_opcodes[last_match].name);
|
| 744 |
19 |
jeremybenn |
*cur = LEAF_FLAG | last_match;
|
| 745 |
|
|
cur++;
|
| 746 |
|
|
nuncovered--;
|
| 747 |
|
|
}
|
| 748 |
|
|
else
|
| 749 |
|
|
{
|
| 750 |
|
|
/* Find longest match. */
|
| 751 |
|
|
for (i = 0; i < 32; i++)
|
| 752 |
|
|
{
|
| 753 |
|
|
int len;
|
| 754 |
|
|
for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
|
| 755 |
|
|
{
|
| 756 |
|
|
unsigned long m = (1UL << ((unsigned long) len)) - 1;
|
| 757 |
|
|
or32_debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)", len, m,
|
| 758 |
|
|
cur_mask, i, (cur_mask >> (unsigned) i),
|
| 759 |
|
|
(cur_mask >> (unsigned) i) & m);
|
| 760 |
|
|
if ((m & (cur_mask >> (unsigned) i)) == m)
|
| 761 |
|
|
{
|
| 762 |
|
|
best_len = len;
|
| 763 |
|
|
best_first = i;
|
| 764 |
|
|
or32_debug (9, "!");
|
| 765 |
|
|
}
|
| 766 |
|
|
else
|
| 767 |
|
|
break;
|
| 768 |
|
|
}
|
| 769 |
|
|
}
|
| 770 |
|
|
or32_debug (9, "\n");
|
| 771 |
|
|
if (!best_len)
|
| 772 |
|
|
{
|
| 773 |
|
|
fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr,
|
| 774 |
|
|
mask);
|
| 775 |
230 |
jeremybenn |
for (i = 0; i < NUM_OPCODES; i++)
|
| 776 |
|
|
if (or1ksim_ti[i].in_pass == pass)
|
| 777 |
|
|
fprintf (stderr, "%s ", or1ksim_or32_opcodes[i].name);
|
| 778 |
19 |
jeremybenn |
|
| 779 |
|
|
fprintf (stderr, "\n");
|
| 780 |
|
|
exit (1);
|
| 781 |
|
|
}
|
| 782 |
230 |
jeremybenn |
or32_debug (8, "%i> #### %i << %i (%i) ####\n", cur - or1ksim_automata, best_len,
|
| 783 |
19 |
jeremybenn |
best_first, ninstr);
|
| 784 |
|
|
*cur = best_first;
|
| 785 |
|
|
cur++;
|
| 786 |
|
|
*cur = (1 << best_len) - 1;
|
| 787 |
|
|
cur++;
|
| 788 |
|
|
next = cur;
|
| 789 |
|
|
/* Allocate space for pointers. */
|
| 790 |
|
|
cur += 1 << best_len;
|
| 791 |
|
|
cur_mask = (1 << (unsigned long) best_len) - 1;
|
| 792 |
|
|
|
| 793 |
|
|
for (i = 0; i < (1 << (unsigned long) best_len); i++)
|
| 794 |
|
|
{
|
| 795 |
|
|
int j;
|
| 796 |
|
|
unsigned long *c;
|
| 797 |
|
|
curpass++;
|
| 798 |
230 |
jeremybenn |
for (j = 0; j < NUM_OPCODES; j++)
|
| 799 |
|
|
if (or1ksim_ti[j].in_pass == pass
|
| 800 |
|
|
&& ((or1ksim_ti[j].insn >> best_first) & cur_mask) ==
|
| 801 |
19 |
jeremybenn |
(unsigned long) i
|
| 802 |
230 |
jeremybenn |
&& ((or1ksim_ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
|
| 803 |
|
|
or1ksim_ti[j].in_pass = curpass;
|
| 804 |
19 |
jeremybenn |
|
| 805 |
|
|
or32_debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first);
|
| 806 |
|
|
c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
|
| 807 |
|
|
if (c)
|
| 808 |
|
|
{
|
| 809 |
230 |
jeremybenn |
or32_debug (8, "%i> #%X -> %u\n", next - or1ksim_automata, i,
|
| 810 |
|
|
cur - or1ksim_automata);
|
| 811 |
|
|
*next = cur - or1ksim_automata;
|
| 812 |
19 |
jeremybenn |
cur = c;
|
| 813 |
|
|
}
|
| 814 |
|
|
else
|
| 815 |
|
|
{
|
| 816 |
230 |
jeremybenn |
or32_debug (8, "%i> N/A\n", next - or1ksim_automata);
|
| 817 |
19 |
jeremybenn |
*next = 0;
|
| 818 |
|
|
}
|
| 819 |
|
|
next++;
|
| 820 |
|
|
}
|
| 821 |
|
|
}
|
| 822 |
|
|
return cur;
|
| 823 |
|
|
}
|
| 824 |
|
|
|
| 825 |
|
|
/* Returns number of nonzero bits. */
|
| 826 |
|
|
static int
|
| 827 |
|
|
num_ones (unsigned long value)
|
| 828 |
|
|
{
|
| 829 |
|
|
int c = 0;
|
| 830 |
|
|
while (value)
|
| 831 |
|
|
{
|
| 832 |
|
|
if (value & 1)
|
| 833 |
|
|
c++;
|
| 834 |
|
|
value >>= 1;
|
| 835 |
|
|
}
|
| 836 |
|
|
return c;
|
| 837 |
|
|
}
|
| 838 |
|
|
|
| 839 |
|
|
/* Utility function, which converts parameters from or32_opcode format to more binary form.
|
| 840 |
230 |
jeremybenn |
Parameters are stored in or1ksim_ti struct. */
|
| 841 |
19 |
jeremybenn |
|
| 842 |
|
|
static struct insn_op_struct *
|
| 843 |
|
|
parse_params (CONST struct or32_opcode *opcode, struct insn_op_struct *cur)
|
| 844 |
|
|
{
|
| 845 |
|
|
char *args = opcode->args;
|
| 846 |
|
|
int i, type;
|
| 847 |
|
|
int num_cur_op = 0;;
|
| 848 |
|
|
|
| 849 |
|
|
i = 0;
|
| 850 |
|
|
type = 0;
|
| 851 |
|
|
/* In case we don't have any parameters, we add dummy read from r0. */
|
| 852 |
|
|
if (!(*args))
|
| 853 |
|
|
{
|
| 854 |
|
|
cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
|
| 855 |
|
|
cur->data = 0;
|
| 856 |
|
|
or32_debug (9, "#%08lX %08lX\n", cur->type, cur->data);
|
| 857 |
|
|
cur++;
|
| 858 |
|
|
return cur;
|
| 859 |
|
|
}
|
| 860 |
|
|
|
| 861 |
|
|
while (*args != '\0')
|
| 862 |
|
|
{
|
| 863 |
|
|
if (*args == 'r')
|
| 864 |
|
|
{
|
| 865 |
|
|
args++;
|
| 866 |
|
|
type |= OPTYPE_REG;
|
| 867 |
|
|
if (*args == 'D')
|
| 868 |
|
|
type |= OPTYPE_DST;
|
| 869 |
|
|
}
|
| 870 |
240 |
julius |
else if (isalpha ((int)*args))
|
| 871 |
19 |
jeremybenn |
{
|
| 872 |
|
|
unsigned long arg;
|
| 873 |
|
|
arg = insn_extract (*args, opcode->encoding);
|
| 874 |
|
|
or32_debug (9, "%s : %08lX ------\n", opcode->name, arg);
|
| 875 |
|
|
if (letter_signed (*args))
|
| 876 |
|
|
{
|
| 877 |
|
|
type |= OPTYPE_SIG;
|
| 878 |
|
|
type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
|
| 879 |
|
|
}
|
| 880 |
|
|
|
| 881 |
|
|
num_cur_op = 0;
|
| 882 |
|
|
/* Split argument to sequences of consecutive ones. */
|
| 883 |
|
|
while (arg)
|
| 884 |
|
|
{
|
| 885 |
|
|
int shr = 0;
|
| 886 |
|
|
unsigned long tmp = arg, mask = 0;
|
| 887 |
|
|
while ((tmp & 1) == 0)
|
| 888 |
|
|
{
|
| 889 |
|
|
shr++;
|
| 890 |
|
|
tmp >>= 1;
|
| 891 |
|
|
}
|
| 892 |
|
|
while (tmp & 1)
|
| 893 |
|
|
{
|
| 894 |
|
|
mask++;
|
| 895 |
|
|
tmp >>= 1;
|
| 896 |
|
|
}
|
| 897 |
|
|
cur->type = type | shr;
|
| 898 |
|
|
cur->data = mask;
|
| 899 |
|
|
arg &= ~(((1 << mask) - 1) << shr);
|
| 900 |
|
|
or32_debug (6, "|%08lX %08lX\n", cur->type, cur->data);
|
| 901 |
|
|
cur++;
|
| 902 |
|
|
num_cur_op++;
|
| 903 |
|
|
}
|
| 904 |
|
|
args++;
|
| 905 |
|
|
}
|
| 906 |
|
|
else if (*args == '(')
|
| 907 |
|
|
{
|
| 908 |
|
|
/* Next param is displacement. Later we will treat them as one operand. */
|
| 909 |
|
|
/* Set the OPTYPE_DIS flag on all insn_op_structs that belong to this
|
| 910 |
|
|
* operand */
|
| 911 |
|
|
while (num_cur_op > 0)
|
| 912 |
|
|
{
|
| 913 |
|
|
cur[-num_cur_op].type |= type | OPTYPE_DIS;
|
| 914 |
|
|
num_cur_op--;
|
| 915 |
|
|
}
|
| 916 |
|
|
cur[-1].type |= OPTYPE_OP;
|
| 917 |
|
|
or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
|
| 918 |
|
|
type = 0;
|
| 919 |
|
|
i++;
|
| 920 |
|
|
args++;
|
| 921 |
|
|
}
|
| 922 |
|
|
else if (*args == OPERAND_DELIM)
|
| 923 |
|
|
{
|
| 924 |
|
|
cur--;
|
| 925 |
|
|
cur->type = type | cur->type | OPTYPE_OP;
|
| 926 |
|
|
or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
|
| 927 |
|
|
cur++;
|
| 928 |
|
|
type = 0;
|
| 929 |
|
|
i++;
|
| 930 |
|
|
args++;
|
| 931 |
|
|
}
|
| 932 |
|
|
else if (*args == '0')
|
| 933 |
|
|
{
|
| 934 |
|
|
cur->type = type;
|
| 935 |
|
|
cur->data = 0;
|
| 936 |
|
|
or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
|
| 937 |
|
|
cur++;
|
| 938 |
|
|
type = 0;
|
| 939 |
|
|
i++;
|
| 940 |
|
|
args++;
|
| 941 |
|
|
}
|
| 942 |
|
|
else if (*args == ')')
|
| 943 |
|
|
args++;
|
| 944 |
|
|
else
|
| 945 |
|
|
{
|
| 946 |
|
|
fprintf (stderr, "%s : parse error in args.\n", opcode->name);
|
| 947 |
|
|
exit (1);
|
| 948 |
|
|
}
|
| 949 |
|
|
}
|
| 950 |
|
|
cur--;
|
| 951 |
|
|
cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
|
| 952 |
|
|
or32_debug (9, "#%08lX %08lX\n", cur->type, cur->data);
|
| 953 |
|
|
cur++;
|
| 954 |
|
|
return cur;
|
| 955 |
|
|
}
|
| 956 |
|
|
|
| 957 |
220 |
jeremybenn |
/* -------------------------------------------------------------------------- */
|
| 958 |
230 |
jeremybenn |
/*!Constructs new automata based on or1ksim_or32_opcodes array.
|
| 959 |
19 |
jeremybenn |
|
| 960 |
220 |
jeremybenn |
@param[in] quiet If non-zero (TRUE) do not print informational messages. */
|
| 961 |
|
|
/* -------------------------------------------------------------------------- */
|
| 962 |
19 |
jeremybenn |
void
|
| 963 |
230 |
jeremybenn |
or1ksim_build_automata (int quiet)
|
| 964 |
19 |
jeremybenn |
{
|
| 965 |
|
|
int i;
|
| 966 |
|
|
unsigned long *end;
|
| 967 |
|
|
struct insn_op_struct *cur;
|
| 968 |
|
|
|
| 969 |
230 |
jeremybenn |
or1ksim_automata =
|
| 970 |
19 |
jeremybenn |
(unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
|
| 971 |
230 |
jeremybenn |
or1ksim_ti =
|
| 972 |
19 |
jeremybenn |
(struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) *
|
| 973 |
230 |
jeremybenn |
NUM_OPCODES);
|
| 974 |
19 |
jeremybenn |
|
| 975 |
230 |
jeremybenn |
nuncovered = NUM_OPCODES;
|
| 976 |
19 |
jeremybenn |
|
| 977 |
|
|
#ifdef HAVE_EXECUTION
|
| 978 |
220 |
jeremybenn |
if (!quiet)
|
| 979 |
|
|
{
|
| 980 |
|
|
printf ("Building automata... ");
|
| 981 |
|
|
}
|
| 982 |
19 |
jeremybenn |
#endif
|
| 983 |
|
|
|
| 984 |
|
|
/* Build temporary information about instructions. */
|
| 985 |
230 |
jeremybenn |
for (i = 0; i < NUM_OPCODES; i++)
|
| 986 |
19 |
jeremybenn |
{
|
| 987 |
|
|
unsigned long ones, zeros;
|
| 988 |
230 |
jeremybenn |
char *encoding = or1ksim_or32_opcodes[i].encoding;
|
| 989 |
19 |
jeremybenn |
ones = insn_extract ('1', encoding);
|
| 990 |
|
|
zeros = insn_extract ('0', encoding);
|
| 991 |
230 |
jeremybenn |
or1ksim_ti[i].insn_mask = ones | zeros;
|
| 992 |
|
|
or1ksim_ti[i].insn = ones;
|
| 993 |
|
|
or1ksim_ti[i].in_pass = curpass = 0;
|
| 994 |
|
|
/*debug(9, "%s: %s %08X %08X\n", or1ksim_or32_opcodes[i].name,
|
| 995 |
|
|
or1ksim_or32_opcodes[i].encoding, or1ksim_ti[i].insn_mask, or1ksim_ti[i].insn); */
|
| 996 |
19 |
jeremybenn |
}
|
| 997 |
|
|
|
| 998 |
|
|
/* Until all are covered search for best criteria to separate them. */
|
| 999 |
230 |
jeremybenn |
end = cover_insn (or1ksim_automata, curpass, 0xFFFFFFFF);
|
| 1000 |
|
|
if (end - or1ksim_automata > MAX_AUTOMATA_SIZE)
|
| 1001 |
19 |
jeremybenn |
{
|
| 1002 |
|
|
fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
|
| 1003 |
|
|
exit (1);
|
| 1004 |
|
|
}
|
| 1005 |
|
|
#ifdef HAVE_EXECUTION
|
| 1006 |
220 |
jeremybenn |
if (!quiet)
|
| 1007 |
|
|
{
|
| 1008 |
230 |
jeremybenn |
printf ("done, num uncovered: %i/%i.\n", nuncovered, NUM_OPCODES);
|
| 1009 |
220 |
jeremybenn |
}
|
| 1010 |
19 |
jeremybenn |
#endif
|
| 1011 |
|
|
|
| 1012 |
|
|
#ifdef HAVE_EXECUTION
|
| 1013 |
220 |
jeremybenn |
if (!quiet)
|
| 1014 |
|
|
{
|
| 1015 |
|
|
printf ("Parsing operands data... ");
|
| 1016 |
|
|
}
|
| 1017 |
19 |
jeremybenn |
#endif
|
| 1018 |
|
|
op_data =
|
| 1019 |
|
|
(struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE *
|
| 1020 |
|
|
sizeof (struct insn_op_struct));
|
| 1021 |
230 |
jeremybenn |
or1ksim_op_start =
|
| 1022 |
|
|
(struct insn_op_struct **) malloc (NUM_OPCODES *
|
| 1023 |
19 |
jeremybenn |
sizeof (struct insn_op_struct *));
|
| 1024 |
|
|
cur = op_data;
|
| 1025 |
230 |
jeremybenn |
for (i = 0; i < NUM_OPCODES; i++)
|
| 1026 |
19 |
jeremybenn |
{
|
| 1027 |
230 |
jeremybenn |
or1ksim_op_start[i] = cur;
|
| 1028 |
|
|
cur = parse_params (&or1ksim_or32_opcodes[i], cur);
|
| 1029 |
19 |
jeremybenn |
if (cur - op_data > MAX_OP_TABLE_SIZE)
|
| 1030 |
|
|
{
|
| 1031 |
|
|
fprintf (stderr,
|
| 1032 |
|
|
"Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
|
| 1033 |
|
|
exit (1);
|
| 1034 |
|
|
}
|
| 1035 |
|
|
}
|
| 1036 |
|
|
#ifdef HAVE_EXECUTION
|
| 1037 |
220 |
jeremybenn |
if (!quiet)
|
| 1038 |
|
|
{
|
| 1039 |
|
|
printf ("done.\n");
|
| 1040 |
|
|
}
|
| 1041 |
19 |
jeremybenn |
#endif
|
| 1042 |
|
|
}
|
| 1043 |
|
|
|
| 1044 |
|
|
void
|
| 1045 |
230 |
jeremybenn |
or1ksim_destruct_automata ()
|
| 1046 |
19 |
jeremybenn |
{
|
| 1047 |
230 |
jeremybenn |
free (or1ksim_ti);
|
| 1048 |
|
|
free (or1ksim_automata);
|
| 1049 |
19 |
jeremybenn |
free (op_data);
|
| 1050 |
230 |
jeremybenn |
free (or1ksim_op_start);
|
| 1051 |
19 |
jeremybenn |
}
|
| 1052 |
|
|
|
| 1053 |
|
|
/* Decodes instruction and returns instruction index. */
|
| 1054 |
|
|
int
|
| 1055 |
230 |
jeremybenn |
or1ksim_insn_decode (unsigned int insn)
|
| 1056 |
19 |
jeremybenn |
{
|
| 1057 |
230 |
jeremybenn |
unsigned long *a = or1ksim_automata;
|
| 1058 |
19 |
jeremybenn |
int i;
|
| 1059 |
|
|
while (!(*a & LEAF_FLAG))
|
| 1060 |
|
|
{
|
| 1061 |
|
|
unsigned int first = *a;
|
| 1062 |
230 |
jeremybenn |
//debug(9, "%i ", a - or1ksim_automata);
|
| 1063 |
19 |
jeremybenn |
a++;
|
| 1064 |
|
|
i = (insn >> first) & *a;
|
| 1065 |
|
|
a++;
|
| 1066 |
|
|
if (!*(a + i))
|
| 1067 |
|
|
{ /* Invalid instruction found? */
|
| 1068 |
|
|
//debug(9, "XXX\n", i);
|
| 1069 |
|
|
return -1;
|
| 1070 |
|
|
}
|
| 1071 |
230 |
jeremybenn |
a = or1ksim_automata + *(a + i);
|
| 1072 |
19 |
jeremybenn |
}
|
| 1073 |
|
|
i = *a & ~LEAF_FLAG;
|
| 1074 |
|
|
//debug(9, "%i\n", i);
|
| 1075 |
|
|
/* Final check - do we have direct match?
|
| 1076 |
230 |
jeremybenn |
(based on or1ksim_or32_opcodes this should be the only possibility,
|
| 1077 |
19 |
jeremybenn |
but in case of invalid/missing instruction we must perform a check) */
|
| 1078 |
230 |
jeremybenn |
if ((or1ksim_ti[i].insn_mask & insn) == or1ksim_ti[i].insn)
|
| 1079 |
19 |
jeremybenn |
return i;
|
| 1080 |
|
|
else
|
| 1081 |
|
|
return -1;
|
| 1082 |
|
|
}
|
| 1083 |
|
|
|
| 1084 |
|
|
static char disassembled_str[50];
|
| 1085 |
230 |
jeremybenn |
char *or1ksim_disassembled = &disassembled_str[0];
|
| 1086 |
19 |
jeremybenn |
|
| 1087 |
420 |
jeremybenn |
/* trace data */
|
| 1088 |
|
|
int trace_dest_reg;
|
| 1089 |
|
|
int trace_store_addr_reg;
|
| 1090 |
|
|
unsigned int trace_store_imm;
|
| 1091 |
|
|
int trace_store_val_reg;
|
| 1092 |
|
|
int trace_store_width;
|
| 1093 |
458 |
julius |
int trace_dest_spr;
|
| 1094 |
420 |
jeremybenn |
|
| 1095 |
19 |
jeremybenn |
/* Automagically does zero- or sign- extension and also finds correct
|
| 1096 |
|
|
sign bit position if sign extension is correct extension. Which extension
|
| 1097 |
|
|
is proper is figured out from letter description. */
|
| 1098 |
|
|
|
| 1099 |
|
|
unsigned long
|
| 1100 |
230 |
jeremybenn |
or1ksim_extend_imm (unsigned long imm, char l)
|
| 1101 |
19 |
jeremybenn |
{
|
| 1102 |
|
|
unsigned long mask;
|
| 1103 |
|
|
int letter_bits;
|
| 1104 |
|
|
|
| 1105 |
|
|
/* First truncate all bits above valid range for this letter
|
| 1106 |
|
|
in case it is zero extend. */
|
| 1107 |
|
|
letter_bits = letter_range (l);
|
| 1108 |
|
|
mask = (1 << letter_bits) - 1;
|
| 1109 |
|
|
imm &= mask;
|
| 1110 |
|
|
|
| 1111 |
|
|
/* Do sign extend if this is the right one. */
|
| 1112 |
|
|
if (letter_signed (l) && (imm >> (letter_bits - 1)))
|
| 1113 |
|
|
imm |= (~mask);
|
| 1114 |
|
|
|
| 1115 |
|
|
return imm;
|
| 1116 |
|
|
}
|
| 1117 |
|
|
|
| 1118 |
|
|
unsigned long
|
| 1119 |
230 |
jeremybenn |
or1ksim_or32_extract (param_ch, enc_initial, insn)
|
| 1120 |
19 |
jeremybenn |
char param_ch;
|
| 1121 |
|
|
char *enc_initial;
|
| 1122 |
|
|
unsigned long insn;
|
| 1123 |
|
|
{
|
| 1124 |
|
|
char *enc;
|
| 1125 |
|
|
unsigned long ret = 0;
|
| 1126 |
|
|
int opc_pos = 0;
|
| 1127 |
|
|
int param_pos = 0;
|
| 1128 |
|
|
|
| 1129 |
|
|
for (enc = enc_initial; *enc != '\0'; enc++)
|
| 1130 |
|
|
if (*enc == param_ch)
|
| 1131 |
|
|
{
|
| 1132 |
|
|
if (enc - 2 >= enc_initial && (*(enc - 2) == '0')
|
| 1133 |
|
|
&& (*(enc - 1) == 'x'))
|
| 1134 |
|
|
continue;
|
| 1135 |
|
|
else
|
| 1136 |
|
|
param_pos++;
|
| 1137 |
|
|
}
|
| 1138 |
|
|
|
| 1139 |
|
|
#if DEBUG
|
| 1140 |
230 |
jeremybenn |
printf ("or1ksim_or32_extract: %x ", param_pos);
|
| 1141 |
19 |
jeremybenn |
#endif
|
| 1142 |
|
|
opc_pos = 32;
|
| 1143 |
|
|
for (enc = enc_initial; *enc != '\0';)
|
| 1144 |
|
|
if ((*enc == '0') && (*(enc + 1) == 'x'))
|
| 1145 |
|
|
{
|
| 1146 |
|
|
opc_pos -= 4;
|
| 1147 |
|
|
if ((param_ch == '0') || (param_ch == '1'))
|
| 1148 |
|
|
{
|
| 1149 |
|
|
unsigned long tmp = strtol (enc, NULL, 16);
|
| 1150 |
|
|
#if DEBUG
|
| 1151 |
|
|
printf (" enc=%s, tmp=%x ", enc, tmp);
|
| 1152 |
|
|
#endif
|
| 1153 |
|
|
if (param_ch == '0')
|
| 1154 |
|
|
tmp = 15 - tmp;
|
| 1155 |
|
|
ret |= tmp << opc_pos;
|
| 1156 |
|
|
}
|
| 1157 |
|
|
enc += 3;
|
| 1158 |
|
|
}
|
| 1159 |
|
|
else if ((*enc == '0') || (*enc == '1'))
|
| 1160 |
|
|
{
|
| 1161 |
|
|
opc_pos--;
|
| 1162 |
|
|
if (param_ch == *enc)
|
| 1163 |
|
|
ret |= 1 << opc_pos;
|
| 1164 |
|
|
enc++;
|
| 1165 |
|
|
}
|
| 1166 |
|
|
else if (*enc == param_ch)
|
| 1167 |
|
|
{
|
| 1168 |
|
|
opc_pos--;
|
| 1169 |
|
|
param_pos--;
|
| 1170 |
|
|
#if DEBUG
|
| 1171 |
|
|
printf ("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos,
|
| 1172 |
|
|
param_pos);
|
| 1173 |
|
|
#endif
|
| 1174 |
240 |
julius |
if (islower ((int) param_ch))
|
| 1175 |
19 |
jeremybenn |
ret -= ((insn >> opc_pos) & 0x1) << param_pos;
|
| 1176 |
|
|
else
|
| 1177 |
|
|
ret += ((insn >> opc_pos) & 0x1) << param_pos;
|
| 1178 |
|
|
enc++;
|
| 1179 |
|
|
}
|
| 1180 |
240 |
julius |
else if (isalpha ((int)*enc))
|
| 1181 |
19 |
jeremybenn |
{
|
| 1182 |
|
|
opc_pos--;
|
| 1183 |
|
|
enc++;
|
| 1184 |
|
|
}
|
| 1185 |
|
|
else if (*enc == '-')
|
| 1186 |
|
|
{
|
| 1187 |
|
|
opc_pos--;
|
| 1188 |
|
|
enc++;
|
| 1189 |
|
|
}
|
| 1190 |
|
|
else
|
| 1191 |
|
|
enc++;
|
| 1192 |
|
|
|
| 1193 |
|
|
#if DEBUG
|
| 1194 |
|
|
printf ("ret=%x\n", ret);
|
| 1195 |
|
|
#endif
|
| 1196 |
|
|
return ret;
|
| 1197 |
|
|
}
|
| 1198 |
|
|
|
| 1199 |
|
|
/* Print register. Used only by print_insn. */
|
| 1200 |
|
|
|
| 1201 |
|
|
static char *
|
| 1202 |
|
|
or32_print_register (dest, param_ch, encoding, insn)
|
| 1203 |
|
|
char *dest;
|
| 1204 |
|
|
char param_ch;
|
| 1205 |
|
|
char *encoding;
|
| 1206 |
|
|
unsigned long insn;
|
| 1207 |
|
|
{
|
| 1208 |
230 |
jeremybenn |
int regnum = or1ksim_or32_extract (param_ch, encoding, insn);
|
| 1209 |
19 |
jeremybenn |
|
| 1210 |
|
|
sprintf (dest, "r%d", regnum);
|
| 1211 |
|
|
while (*dest)
|
| 1212 |
|
|
dest++;
|
| 1213 |
|
|
return dest;
|
| 1214 |
|
|
}
|
| 1215 |
|
|
|
| 1216 |
|
|
/* Print immediate. Used only by print_insn. */
|
| 1217 |
|
|
|
| 1218 |
|
|
static char *
|
| 1219 |
|
|
or32_print_immediate (dest, param_ch, encoding, insn)
|
| 1220 |
|
|
char *dest;
|
| 1221 |
|
|
char param_ch;
|
| 1222 |
|
|
char *encoding;
|
| 1223 |
|
|
unsigned long insn;
|
| 1224 |
|
|
{
|
| 1225 |
230 |
jeremybenn |
int imm = or1ksim_or32_extract (param_ch, encoding, insn);
|
| 1226 |
19 |
jeremybenn |
|
| 1227 |
230 |
jeremybenn |
imm = or1ksim_extend_imm (imm, param_ch);
|
| 1228 |
19 |
jeremybenn |
|
| 1229 |
|
|
if (letter_signed (param_ch))
|
| 1230 |
|
|
{
|
| 1231 |
|
|
if (imm < 0)
|
| 1232 |
|
|
sprintf (dest, "%d", imm);
|
| 1233 |
|
|
else
|
| 1234 |
|
|
sprintf (dest, "0x%x", imm);
|
| 1235 |
|
|
}
|
| 1236 |
|
|
else
|
| 1237 |
|
|
sprintf (dest, "%#x", imm);
|
| 1238 |
|
|
while (*dest)
|
| 1239 |
|
|
dest++;
|
| 1240 |
|
|
return dest;
|
| 1241 |
|
|
}
|
| 1242 |
|
|
|
| 1243 |
|
|
/* Disassemble one instruction from insn to disassemble.
|
| 1244 |
|
|
Return the size of the instruction. */
|
| 1245 |
|
|
|
| 1246 |
|
|
int
|
| 1247 |
230 |
jeremybenn |
or1ksim_disassemble_insn (insn)
|
| 1248 |
19 |
jeremybenn |
unsigned long insn;
|
| 1249 |
|
|
{
|
| 1250 |
230 |
jeremybenn |
return or1ksim_disassemble_index (insn, or1ksim_insn_decode (insn));
|
| 1251 |
19 |
jeremybenn |
}
|
| 1252 |
|
|
|
| 1253 |
|
|
/* Disassemble one instruction from insn index.
|
| 1254 |
|
|
Return the size of the instruction. */
|
| 1255 |
|
|
|
| 1256 |
|
|
int
|
| 1257 |
230 |
jeremybenn |
or1ksim_disassemble_index (insn, index)
|
| 1258 |
19 |
jeremybenn |
unsigned long insn;
|
| 1259 |
|
|
int index;
|
| 1260 |
|
|
{
|
| 1261 |
230 |
jeremybenn |
char *dest = or1ksim_disassembled;
|
| 1262 |
19 |
jeremybenn |
if (index >= 0)
|
| 1263 |
|
|
{
|
| 1264 |
230 |
jeremybenn |
struct or32_opcode const *opcode = &or1ksim_or32_opcodes[index];
|
| 1265 |
19 |
jeremybenn |
char *s;
|
| 1266 |
|
|
|
| 1267 |
|
|
strcpy (dest, opcode->name);
|
| 1268 |
|
|
while (*dest)
|
| 1269 |
|
|
dest++;
|
| 1270 |
|
|
*dest++ = ' ';
|
| 1271 |
|
|
*dest = 0;
|
| 1272 |
|
|
|
| 1273 |
|
|
for (s = opcode->args; *s != '\0'; ++s)
|
| 1274 |
|
|
{
|
| 1275 |
|
|
switch (*s)
|
| 1276 |
|
|
{
|
| 1277 |
|
|
case '\0':
|
| 1278 |
230 |
jeremybenn |
return or1ksim_insn_len (insn);
|
| 1279 |
19 |
jeremybenn |
|
| 1280 |
|
|
case 'r':
|
| 1281 |
|
|
dest = or32_print_register (dest, *++s, opcode->encoding, insn);
|
| 1282 |
|
|
break;
|
| 1283 |
|
|
|
| 1284 |
|
|
default:
|
| 1285 |
|
|
if (strchr (opcode->encoding, *s))
|
| 1286 |
|
|
dest =
|
| 1287 |
|
|
or32_print_immediate (dest, *s, opcode->encoding, insn);
|
| 1288 |
|
|
else
|
| 1289 |
|
|
{
|
| 1290 |
|
|
*dest++ = *s;
|
| 1291 |
|
|
*dest = 0;
|
| 1292 |
|
|
}
|
| 1293 |
|
|
}
|
| 1294 |
|
|
}
|
| 1295 |
|
|
}
|
| 1296 |
|
|
else
|
| 1297 |
|
|
{
|
| 1298 |
|
|
/* This used to be %8x for binutils. */
|
| 1299 |
|
|
sprintf (dest, ".word 0x%08lx", insn);
|
| 1300 |
|
|
while (*dest)
|
| 1301 |
|
|
dest++;
|
| 1302 |
|
|
}
|
| 1303 |
230 |
jeremybenn |
return or1ksim_insn_len (insn);
|
| 1304 |
19 |
jeremybenn |
}
|
| 1305 |
420 |
jeremybenn |
|
| 1306 |
|
|
|
| 1307 |
|
|
/* -------------------------------------------------------------------------- */
|
| 1308 |
|
|
/*!Disassemble one instruction for tracing.
|
| 1309 |
|
|
|
| 1310 |
|
|
A simplified form of or1ksim_disassemble_index.
|
| 1311 |
|
|
|
| 1312 |
|
|
@param[in] insn The instruction to disassemble
|
| 1313 |
|
|
@param[in] index Index into the opcode table. */
|
| 1314 |
|
|
/* -------------------------------------------------------------------------- */
|
| 1315 |
|
|
void
|
| 1316 |
|
|
or1ksim_disassemble_trace_index (unsigned long int insn,
|
| 1317 |
|
|
int index)
|
| 1318 |
|
|
{
|
| 1319 |
|
|
int i;
|
| 1320 |
|
|
char *dest = or1ksim_disassembled;
|
| 1321 |
|
|
|
| 1322 |
|
|
/* Set trace result defaults. */
|
| 1323 |
|
|
trace_dest_reg = -1;
|
| 1324 |
458 |
julius |
trace_dest_spr = -1;
|
| 1325 |
420 |
jeremybenn |
trace_store_addr_reg = -1;
|
| 1326 |
|
|
trace_store_imm = 0;
|
| 1327 |
|
|
trace_store_val_reg = -1;
|
| 1328 |
|
|
trace_store_width = 0; /* Non-zero if we have a store */
|
| 1329 |
|
|
|
| 1330 |
|
|
if (index >= 0)
|
| 1331 |
|
|
{
|
| 1332 |
|
|
const int OPC_WIDTH = 8;
|
| 1333 |
|
|
|
| 1334 |
|
|
struct or32_opcode const *opcode = &or1ksim_or32_opcodes[index];
|
| 1335 |
|
|
char *s;
|
| 1336 |
|
|
|
| 1337 |
|
|
/* Is it a store opcode? */
|
| 1338 |
|
|
if (0 == strcmp ("l.sb", opcode->name))
|
| 1339 |
|
|
{
|
| 1340 |
|
|
trace_store_width = 1;
|
| 1341 |
|
|
}
|
| 1342 |
|
|
else if (0 == strcmp ("l.sh", opcode->name))
|
| 1343 |
|
|
{
|
| 1344 |
|
|
trace_store_width = 2;
|
| 1345 |
|
|
}
|
| 1346 |
|
|
else if (0 == strcmp ("l.sw", opcode->name))
|
| 1347 |
|
|
{
|
| 1348 |
|
|
trace_store_width = 4;
|
| 1349 |
|
|
}
|
| 1350 |
|
|
|
| 1351 |
458 |
julius |
/* Is it a move to SPR opcode? */
|
| 1352 |
|
|
if (0 == strcmp ("l.mtspr", opcode->name))
|
| 1353 |
|
|
{
|
| 1354 |
|
|
trace_dest_spr = 1;
|
| 1355 |
|
|
}
|
| 1356 |
|
|
|
| 1357 |
420 |
jeremybenn |
/* Copy the opcode and pad */
|
| 1358 |
|
|
strcpy (dest, opcode->name);
|
| 1359 |
|
|
|
| 1360 |
|
|
for (i = 0; i < OPC_WIDTH; i++)
|
| 1361 |
|
|
{
|
| 1362 |
|
|
if ('\0' == dest[0])
|
| 1363 |
|
|
{
|
| 1364 |
|
|
dest[0] = ' ';
|
| 1365 |
|
|
dest[1] = '\0';
|
| 1366 |
|
|
}
|
| 1367 |
|
|
|
| 1368 |
|
|
dest++;
|
| 1369 |
|
|
}
|
| 1370 |
|
|
|
| 1371 |
|
|
for (s = opcode->args; *s != '\0'; ++s)
|
| 1372 |
|
|
{
|
| 1373 |
|
|
switch (*s)
|
| 1374 |
|
|
{
|
| 1375 |
|
|
case '\0':
|
| 1376 |
|
|
break;
|
| 1377 |
|
|
|
| 1378 |
|
|
case 'r':
|
| 1379 |
|
|
dest = or32_print_register (dest, *++s, opcode->encoding, insn);
|
| 1380 |
|
|
|
| 1381 |
|
|
switch (*s)
|
| 1382 |
|
|
{
|
| 1383 |
|
|
case 'D':
|
| 1384 |
|
|
trace_dest_reg =
|
| 1385 |
|
|
or1ksim_or32_extract (*s, opcode->encoding, insn);
|
| 1386 |
|
|
break;
|
| 1387 |
|
|
|
| 1388 |
|
|
case 'A':
|
| 1389 |
|
|
if (0 != trace_store_width)
|
| 1390 |
|
|
{
|
| 1391 |
|
|
trace_store_addr_reg =
|
| 1392 |
|
|
or1ksim_or32_extract (*s, opcode->encoding, insn);
|
| 1393 |
|
|
}
|
| 1394 |
|
|
break;
|
| 1395 |
|
|
|
| 1396 |
|
|
case 'B':
|
| 1397 |
|
|
if (0 != trace_store_width)
|
| 1398 |
|
|
{
|
| 1399 |
|
|
trace_store_val_reg =
|
| 1400 |
|
|
or1ksim_or32_extract (*s, opcode->encoding, insn);
|
| 1401 |
|
|
}
|
| 1402 |
|
|
break;
|
| 1403 |
|
|
|
| 1404 |
|
|
}
|
| 1405 |
|
|
|
| 1406 |
|
|
break;
|
| 1407 |
|
|
|
| 1408 |
|
|
default:
|
| 1409 |
|
|
if (strchr (opcode->encoding, *s))
|
| 1410 |
|
|
{
|
| 1411 |
|
|
dest = or32_print_immediate (dest, *s, opcode->encoding,
|
| 1412 |
|
|
insn);
|
| 1413 |
|
|
|
| 1414 |
|
|
/* If we have a store instruction, save the immediate. */
|
| 1415 |
|
|
if (0 != trace_store_width)
|
| 1416 |
|
|
{
|
| 1417 |
|
|
trace_store_imm =
|
| 1418 |
|
|
or1ksim_or32_extract (*s, opcode->encoding, insn);
|
| 1419 |
|
|
trace_store_imm =
|
| 1420 |
|
|
or1ksim_extend_imm (trace_store_imm, *s);
|
| 1421 |
|
|
}
|
| 1422 |
458 |
julius |
|
| 1423 |
|
|
if (1 == trace_dest_spr)
|
| 1424 |
|
|
{
|
| 1425 |
|
|
trace_dest_spr =
|
| 1426 |
|
|
or1ksim_or32_extract ('K', opcode->encoding,
|
| 1427 |
|
|
insn);
|
| 1428 |
|
|
trace_dest_reg =
|
| 1429 |
|
|
or1ksim_or32_extract ('A', opcode->encoding,
|
| 1430 |
|
|
insn);
|
| 1431 |
|
|
}
|
| 1432 |
|
|
|
| 1433 |
420 |
jeremybenn |
}
|
| 1434 |
|
|
else
|
| 1435 |
|
|
{
|
| 1436 |
|
|
*dest++ = *s;
|
| 1437 |
|
|
*dest = 0;
|
| 1438 |
|
|
}
|
| 1439 |
|
|
}
|
| 1440 |
|
|
}
|
| 1441 |
|
|
}
|
| 1442 |
|
|
else
|
| 1443 |
|
|
{
|
| 1444 |
|
|
/* This used to be %8x for binutils. */
|
| 1445 |
|
|
sprintf (dest, ".word 0x%08lx", insn);
|
| 1446 |
|
|
while (*dest)
|
| 1447 |
|
|
dest++;
|
| 1448 |
|
|
}
|
| 1449 |
|
|
} /* or1ksim_disassemble_trace_index () */
|
