OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [or32.c] - Blame information for rev 573

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jeremybenn 
/* Table of opcodes for the OpenRISC 1000 ISA.
2 
 
3 
   Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
4 
   Copyright (C) 2008 Embecosm Limited
5 
 
6 
   Contributed by Damjan Lampret (lampret@opencores.org).
7 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8 
 
9 
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
10 
   This file is also part of gen_or1k_isa, GDB and GAS.
11 
 
12 
   This program is free software; you can redistribute it and/or modify it
13 
   under the terms of the GNU General Public License as published by the Free
14 
   Software Foundation; either version 3 of the License, or (at your option)
15 
   any later version.
16 
 
17 
   This program is distributed in the hope that it will be useful, but WITHOUT
18 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
20 
   more details.
21 
 
22 
   You should have received a copy of the GNU General Public License along
23 
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
24 
 
25 
/* This program is commented throughout in a fashion suitable for processing
26 
   with Doxygen. */
27 
 
28 
 
29 
/* Autoconf and/or portability configuration */
30 
#include "config.h"
31 
#include "port.h"
32 
 
33 
/* System includes */
34 
#include <stdlib.h>
35 
#include <stdio.h>
36 
 
37 
/* Package includes */
38 
#include "opcode/or32.h"
39 
 
40 
/* We treat all letters the same in encode/decode routines so
41 
   we need to assign some characteristics to them like signess etc.*/
42 
CONST struct or32_letter or32_letters[] = {
43 
  {'A', NUM_UNSIGNED},
44 
  {'B', NUM_UNSIGNED},
45 
  {'D', NUM_UNSIGNED},
46 
  {'I', NUM_SIGNED},
47 
  {'K', NUM_UNSIGNED},
48 
  {'L', NUM_UNSIGNED},
49 
  {'N', NUM_SIGNED},
50 
  {'0', NUM_UNSIGNED},
51 
  {'\0', 0}                      /* dummy entry */
52 
};
53 
 
54 
/* Opcode encoding:
55 
   machine[31:30]: first two bits of opcode
56 
                   00 - neither of source operands is GPR
57 
                   01 - second source operand is GPR (rB)
58 
                   10 - first source operand is GPR (rA)
59 
                   11 - both source operands are GPRs (rA and rB)
60 
   machine[29:26]: next four bits of opcode
61 
   machine[25:00]: instruction operands (specific to individual instruction)
62 
 
63 
  Recommendation: irrelevant instruction bits should be set with a value of
64 
  bits in same positions of instruction preceding current instruction in the
65 
  code (when assembling).
66 
*/
67 
 
68 
#ifdef HAVE_EXECUTION
69 
# if SIMPLE_EXECUTION
70 
#  define EFN &l_none
71 
#  define EF(func) &(func)
72 
#  define EFI &l_invalid
73 
# elif COMPLEX_EXECUTION
74 
#  define EFN "l_none"
75 
#  define EFI "l_invalid"
76 
#  ifdef __GNUC__
77 
#   define EF(func) #func
78 
#  else
79 
#   define EF(func) "func"
80 
#  endif
81 
# endif
82 
#else /* HAVE_EXECUTION */
83 
# define EFN &l_none
84 
# define EF(func) EFN
85 
# define EFI EFN
86 
#endif /* HAVE_EXECUTION */
87 
 
88 230 jeremybenn 
CONST struct or32_opcode or1ksim_or32_opcodes[] = {
89 19 jeremybenn 
 
90 
  {"l.j", "N", "00 0x0  NNNNN NNNNN NNNN NNNN NNNN NNNN",
91 
   EF (l_j), OR32_IF_DELAY, it_jump},
92 
  {"l.jal", "N", "00 0x1  NNNNN NNNNN NNNN NNNN NNNN NNNN",
93 
   EF (l_jal), OR32_IF_DELAY, it_jump},
94 
  {"l.bnf", "N", "00 0x3  NNNNN NNNNN NNNN NNNN NNNN NNNN",
95 
   EF (l_bnf), OR32_IF_DELAY | OR32_R_FLAG, it_branch},
96 
  {"l.bf", "N", "00 0x4  NNNNN NNNNN NNNN NNNN NNNN NNNN",
97 
   EF (l_bf), OR32_IF_DELAY | OR32_R_FLAG, it_branch},
98 
  {"l.nop", "K", "00 0x5  01--- ----- KKKK KKKK KKKK KKKK",
99 
   EF (l_nop), 0, it_nop},
100 
  {"l.movhi", "rD,K", "00 0x6  DDDDD ----0 KKKK KKKK KKKK KKKK",
101 
   EF (l_movhi), 0, it_movimm},
102 
  {"l.macrc", "rD", "00 0x6  DDDDD ----1 0000 0000 0000 0000",
103 
   EF (l_macrc), 0, it_mac},
104 
  {"l.sys", "K", "00 0x8  00000 00000 KKKK KKKK KKKK KKKK",
105 
   EF (l_sys), 0, it_exception},
106 
  {"l.trap", "K", "00 0x8  01000 00000 KKKK KKKK KKKK KKKK",
107 
   EF (l_trap), 0, it_exception},
108 
  {"l.msync", "", "00 0x8  10000 00000 0000 0000 0000 0000", EFN,
109 
   0, it_unknown},
110 
  {"l.psync", "", "00 0x8  10100 00000 0000 0000 0000 0000", EFN,
111 
   0, it_unknown},
112 
  {"l.csync", "", "00 0x8  11000 00000 0000 0000 0000 0000", EFN,
113 
   0, it_unknown},
114 
  {"l.rfe", "", "00 0x9  ----- ----- ---- ---- ---- ----",
115 
   EF (l_rfe), 0, it_exception},
116 
  {"lv.all_eq.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
117 
   it_unknown},
118 
  {"lv.all_eq.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
119 
   it_unknown},
120 
  {"lv.all_ge.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
121 
   it_unknown},
122 
  {"lv.all_ge.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
123 
   it_unknown},
124 
  {"lv.all_gt.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0,
125 
   it_unknown},
126 
  {"lv.all_gt.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0,
127 
   it_unknown},
128 
  {"lv.all_le.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
129 
   it_unknown},
130 
  {"lv.all_le.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
131 
   it_unknown},
132 
  {"lv.all_lt.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0,
133 
   it_unknown},
134 
  {"lv.all_lt.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0,
135 
   it_unknown},
136 
  {"lv.all_ne.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0,
137 
   it_unknown},
138 
  {"lv.all_ne.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0,
139 
   it_unknown},
140 
  {"lv.any_eq.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0,
141 
   it_unknown},
142 
  {"lv.any_eq.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0,
143 
   it_unknown},
144 
  {"lv.any_ge.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0,
145 
   it_unknown},
146 
  {"lv.any_ge.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0,
147 
   it_unknown},
148 
  {"lv.any_gt.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0,
149 
   it_unknown},
150 
  {"lv.any_gt.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0,
151 
   it_unknown},
152 
  {"lv.any_le.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0,
153 
   it_unknown},
154 
  {"lv.any_le.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0,
155 
   it_unknown},
156 
  {"lv.any_lt.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0,
157 
   it_unknown},
158 
  {"lv.any_lt.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0,
159 
   it_unknown},
160 
  {"lv.any_ne.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0,
161 
   it_unknown},
162 
  {"lv.any_ne.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0,
163 
   it_unknown},
164 
  {"lv.add.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0,
165 
   it_unknown},
166 
  {"lv.add.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0,
167 
   it_unknown},
168 
  {"lv.adds.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0,
169 
   it_unknown},
170 
  {"lv.adds.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0,
171 
   it_unknown},
172 
  {"lv.addu.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0,
173 
   it_unknown},
174 
  {"lv.addu.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0,
175 
   it_unknown},
176 
  {"lv.addus.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0,
177 
   it_unknown},
178 
  {"lv.addus.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0,
179 
   it_unknown},
180 
  {"lv.and", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0,
181 
   it_unknown},
182 
  {"lv.avg.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0,
183 
   it_unknown},
184 
  {"lv.avg.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0,
185 
   it_unknown},
186 
  {"lv.cmp_eq.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0,
187 
   it_unknown},
188 
  {"lv.cmp_eq.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0,
189 
   it_unknown},
190 
  {"lv.cmp_ge.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0,
191 
   it_unknown},
192 
  {"lv.cmp_ge.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0,
193 
   it_unknown},
194 
  {"lv.cmp_gt.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0,
195 
   it_unknown},
196 
  {"lv.cmp_gt.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0,
197 
   it_unknown},
198 
  {"lv.cmp_le.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0,
199 
   it_unknown},
200 
  {"lv.cmp_le.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0,
201 
   it_unknown},
202 
  {"lv.cmp_lt.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0,
203 
   it_unknown},
204 
  {"lv.cmp_lt.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0,
205 
   it_unknown},
206 
  {"lv.cmp_ne.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0,
207 
   it_unknown},
208 
  {"lv.cmp_ne.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0,
209 
   it_unknown},
210 
  {"lv.madds.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0,
211 
   it_unknown},
212 
  {"lv.max.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0,
213 
   it_unknown},
214 
  {"lv.max.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0,
215 
   it_unknown},
216 
  {"lv.merge.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0,
217 
   it_unknown},
218 
  {"lv.merge.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0,
219 
   it_unknown},
220 
  {"lv.min.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0,
221 
   it_unknown},
222 
  {"lv.min.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0,
223 
   it_unknown},
224 
  {"lv.msubs.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0,
225 
   it_unknown},
226 
  {"lv.muls.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0,
227 
   it_unknown},
228 
  {"lv.nand", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0,
229 
   it_unknown},
230 
  {"lv.nor", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0,
231 
   it_unknown},
232 
  {"lv.or", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0,
233 
   it_unknown},
234 
  {"lv.pack.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0,
235 
   it_unknown},
236 
  {"lv.pack.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0,
237 
   it_unknown},
238 
  {"lv.packs.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0,
239 
   it_unknown},
240 
  {"lv.packs.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0,
241 
   it_unknown},
242 
  {"lv.packus.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0,
243 
   it_unknown},
244 
  {"lv.packus.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0,
245 
   it_unknown},
246 
  {"lv.perm.n", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0,
247 
   it_unknown},
248 
  {"lv.rl.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0,
249 
   it_unknown},
250 
  {"lv.rl.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0,
251 
   it_unknown},
252 
  {"lv.sll.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0,
253 
   it_unknown},
254 
  {"lv.sll.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0,
255 
   it_unknown},
256 
  {"lv.sll", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0,
257 
   it_unknown},
258 
  {"lv.srl.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0,
259 
   it_unknown},
260 
  {"lv.srl.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0,
261 
   it_unknown},
262 
  {"lv.sra.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0,
263 
   it_unknown},
264 
  {"lv.sra.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0,
265 
   it_unknown},
266 
  {"lv.srl", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0,
267 
   it_unknown},
268 
  {"lv.sub.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0,
269 
   it_unknown},
270 
  {"lv.sub.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0,
271 
   it_unknown},
272 
  {"lv.subs.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0,
273 
   it_unknown},
274 
  {"lv.subs.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0,
275 
   it_unknown},
276 
  {"lv.subu.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0,
277 
   it_unknown},
278 
  {"lv.subu.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0,
279 
   it_unknown},
280 
  {"lv.subus.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0,
281 
   it_unknown},
282 
  {"lv.subus.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0,
283 
   it_unknown},
284 
  {"lv.unpack.b", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0,
285 
   it_unknown},
286 
  {"lv.unpack.h", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0,
287 
   it_unknown},
288 
  {"lv.xor", "rD,rA,rB", "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0,
289 
   it_unknown},
290 
  {"lv.cust1", "", "00 0xA  ----- ----- ---- ---- 0xC ----", EFI, 0,
291 
   it_unknown},
292 
  {"lv.cust2", "", "00 0xA  ----- ----- ---- ---- 0xD ----", EFI, 0,
293 
   it_unknown},
294 
  {"lv.cust3", "", "00 0xA  ----- ----- ---- ---- 0xE ----", EFI, 0,
295 
   it_unknown},
296 
  {"lv.cust4", "", "00 0xA  ----- ----- ---- ---- 0xF ----", EFI, 0,
297 
   it_unknown},
298 
 
299 
  {"l.jr", "rB", "01 0x1  ----- ----- BBBB B--- ---- ----",
300 
   EF (l_jr), OR32_IF_DELAY, it_jump},
301 
  {"l.jalr", "rB", "01 0x2  ----- ----- BBBB B--- ---- ----",
302 
   EF (l_jalr), OR32_IF_DELAY, it_jump},
303 116 jeremybenn 
  {"l.maci", "rA,I", "01 0x3  ----- AAAAA IIII IIII IIII IIII",
304 19 jeremybenn 
   EF (l_mac), 0, it_mac},
305 
  {"l.cust1", "", "01 0xC  ----- ----- ---- ---- ---- ----",
306 
   EF (l_cust1), 0, it_unknown},
307 
  {"l.cust2", "", "01 0xD  ----- ----- ---- ---- ---- ----",
308 
   EF (l_cust2), 0, it_unknown},
309 
  {"l.cust3", "", "01 0xE  ----- ----- ---- ---- ---- ----",
310 
   EF (l_cust3), 0, it_unknown},
311 
  {"l.cust4", "", "01 0xF  ----- ----- ---- ---- ---- ----",
312 
   EF (l_cust4), 0, it_unknown},
313 
 
314 
  {"l.ld", "rD,I(rA)", "10 0x0  DDDDD AAAAA IIII IIII IIII IIII", EFI,
315 
   0, it_load},
316 
  {"l.lwz", "rD,I(rA)", "10 0x1  DDDDD AAAAA IIII IIII IIII IIII",
317 
   EF (l_lwz), 0, it_load},
318 104 jeremybenn 
  {"l.lws", "rD,I(rA)", "10 0x2  DDDDD AAAAA IIII IIII IIII IIII",
319 
   EF (l_lws), 0, it_load},
320 19 jeremybenn 
  {"l.lbz", "rD,I(rA)", "10 0x3  DDDDD AAAAA IIII IIII IIII IIII",
321 
   EF (l_lbz), 0, it_load},
322 
  {"l.lbs", "rD,I(rA)", "10 0x4  DDDDD AAAAA IIII IIII IIII IIII",
323 
   EF (l_lbs), 0, it_load},
324 
  {"l.lhz", "rD,I(rA)", "10 0x5  DDDDD AAAAA IIII IIII IIII IIII",
325 
   EF (l_lhz), 0, it_load},
326 
  {"l.lhs", "rD,I(rA)", "10 0x6  DDDDD AAAAA IIII IIII IIII IIII",
327 
   EF (l_lhs), 0, it_load},
328 
 
329 
  {"l.addi", "rD,rA,I", "10 0x7  DDDDD AAAAA IIII IIII IIII IIII",
330 
   EF (l_add), OR32_W_FLAG, it_arith},
331 114 jeremybenn 
  {"l.addic", "rD,rA,I", "10 0x8  DDDDD AAAAA IIII IIII IIII IIII",
332 
   EF (l_addc), OR32_W_FLAG, it_arith},
333 19 jeremybenn 
  {"l.andi", "rD,rA,K", "10 0x9  DDDDD AAAAA KKKK KKKK KKKK KKKK",
334 
   EF (l_and), OR32_W_FLAG, it_arith},
335 
  {"l.ori", "rD,rA,K", "10 0xA  DDDDD AAAAA KKKK KKKK KKKK KKKK",
336 
   EF (l_or), 0, it_arith},
337 127 jeremybenn 
#if HAVE_UNSIGNED_XORI
338 
  {"l.xori", "rD,rA,K", "10 0xB  DDDDD AAAAA KKKK KKKK KKKK KKKK",
339 
   EF (l_xor), 0, it_arith},
340 
#else
341 19 jeremybenn 
  {"l.xori", "rD,rA,I", "10 0xB  DDDDD AAAAA IIII IIII IIII IIII",
342 
   EF (l_xor), 0, it_arith},
343 127 jeremybenn 
#endif
344 19 jeremybenn 
  {"l.muli", "rD,rA,I", "10 0xC  DDDDD AAAAA IIII IIII IIII IIII",
345 
   EF (l_mul), 0, it_arith},
346 
  {"l.mfspr", "rD,rA,K", "10 0xD  DDDDD AAAAA KKKK KKKK KKKK KKKK",
347 
   EF (l_mfspr), 0, it_move},
348 
  {"l.slli", "rD,rA,L", "10 0xE  DDDDD AAAAA ---- ---- 00LL LLLL",
349 
   EF (l_sll), 0, it_shift},
350 
  {"l.srli", "rD,rA,L", "10 0xE  DDDDD AAAAA ---- ---- 01LL LLLL",
351 
   EF (l_srl), 0, it_shift},
352 
  {"l.srai", "rD,rA,L", "10 0xE  DDDDD AAAAA ---- ---- 10LL LLLL",
353 
   EF (l_sra), 0, it_shift},
354 122 jeremybenn 
  {"l.rori", "rD,rA,L", "10 0xE  DDDDD AAAAA ---- ---- 11LL LLLL",
355 
   EF (l_ror), 0, it_shift},
356 19 jeremybenn 
 
357 
  {"l.sfeqi", "rA,I", "10 0xF  00000 AAAAA IIII IIII IIII IIII",
358 
   EF (l_sfeq), OR32_W_FLAG, it_compare},
359 
  {"l.sfnei", "rA,I", "10 0xF  00001 AAAAA IIII IIII IIII IIII",
360 
   EF (l_sfne), OR32_W_FLAG, it_compare},
361 
  {"l.sfgtui", "rA,I", "10 0xF  00010 AAAAA IIII IIII IIII IIII",
362 
   EF (l_sfgtu), OR32_W_FLAG, it_compare},
363 
  {"l.sfgeui", "rA,I", "10 0xF  00011 AAAAA IIII IIII IIII IIII",
364 
   EF (l_sfgeu), OR32_W_FLAG, it_compare},
365 
  {"l.sfltui", "rA,I", "10 0xF  00100 AAAAA IIII IIII IIII IIII",
366 
   EF (l_sfltu), OR32_W_FLAG, it_compare},
367 
  {"l.sfleui", "rA,I", "10 0xF  00101 AAAAA IIII IIII IIII IIII",
368 
   EF (l_sfleu), OR32_W_FLAG, it_compare},
369 
  {"l.sfgtsi", "rA,I", "10 0xF  01010 AAAAA IIII IIII IIII IIII",
370 
   EF (l_sfgts), OR32_W_FLAG, it_compare},
371 
  {"l.sfgesi", "rA,I", "10 0xF  01011 AAAAA IIII IIII IIII IIII",
372 
   EF (l_sfges), OR32_W_FLAG, it_compare},
373 
  {"l.sfltsi", "rA,I", "10 0xF  01100 AAAAA IIII IIII IIII IIII",
374 
   EF (l_sflts), OR32_W_FLAG, it_compare},
375 
  {"l.sflesi", "rA,I", "10 0xF  01101 AAAAA IIII IIII IIII IIII",
376 
   EF (l_sfles), OR32_W_FLAG, it_compare},
377 
 
378 
  {"l.mtspr", "rA,rB,K", "11 0x0  KKKKK AAAAA BBBB BKKK KKKK KKKK",
379 
   EF (l_mtspr), 0, it_move},
380 
  {"l.mac", "rA,rB", "11 0x1  ----- AAAAA BBBB B--- ---- 0x1",
381 
   EF (l_mac), 0, it_mac},
382 
  {"l.msb", "rA,rB", "11 0x1  ----- AAAAA BBBB B--- ---- 0x2",
383 
   EF (l_msb), 0, it_mac},
384 
 
385 
  {"lf.add.s", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x0",
386 
   EF (lf_add_s), 0, it_float},
387 
  {"lf.sub.s", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x1",
388 
   EF (lf_sub_s), 0, it_float},
389 
  {"lf.mul.s", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x2",
390 
   EF (lf_mul_s), 0, it_float},
391 
  {"lf.div.s", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x3",
392 
   EF (lf_div_s), 0, it_float},
393 
  {"lf.itof.s", "rD,rA", "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x4",
394 
   EF (lf_itof_s), 0, it_float},
395 
  {"lf.ftoi.s", "rD,rA", "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x5",
396 
   EF (lf_ftoi_s), 0, it_float},
397 
  {"lf.rem.s", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x6",
398 
   EF (lf_rem_s), 0, it_float},
399 
  {"lf.madd.s", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x7",
400 
   EF (lf_madd_s), 0, it_float},
401 
  {"lf.sfeq.s", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x0 0x8",
402 
   EF (lf_sfeq_s), 0, it_float},
403 
  {"lf.sfne.s", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x0 0x9",
404 
   EF (lf_sfne_s), 0, it_float},
405 
  {"lf.sfgt.s", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x0 0xA",
406 
   EF (lf_sfgt_s), 0, it_float},
407 
  {"lf.sfge.s", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x0 0xB",
408 
   EF (lf_sfge_s), 0, it_float},
409 
  {"lf.sflt.s", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x0 0xC",
410 
   EF (lf_sflt_s), 0, it_float},
411 
  {"lf.sfle.s", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x0 0xD",
412 
   EF (lf_sfle_s), 0, it_float},
413 
  {"lf.cust1.s", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0xD ----", EFI,
414 
   0, it_float},
415 
 
416 
  {"lf.add.d", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
417 
   it_float},
418 
  {"lf.sub.d", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
419 
   it_float},
420 
  {"lf.mul.d", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
421 
   it_float},
422 
  {"lf.div.d", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
423 
   it_float},
424 
  {"lf.itof.d", "rD,rA", "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x4", EFI, 0,
425 
   it_float},
426 
  {"lf.ftoi.d", "rD,rA", "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x5", EFI, 0,
427 
   it_float},
428 
  {"lf.rem.d", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
429 
   it_float},
430 
  {"lf.madd.d", "rD,rA,rB", "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
431 
   it_float},
432 
  {"lf.sfeq.d", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0,
433 
   it_float},
434 
  {"lf.sfne.d", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0,
435 
   it_float},
436 
  {"lf.sfgt.d", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0,
437 
   it_float},
438 
  {"lf.sfge.d", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0,
439 
   it_float},
440 
  {"lf.sflt.d", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0,
441 
   it_float},
442 
  {"lf.sfle.d", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0,
443 
   it_float},
444 
  {"lf.cust1.d", "rA,rB", "11 0x2  ----- AAAAA BBBB B--- 0xE ----", EFI, 0,
445 
   it_float},
446 
 
447 
  {"l.sd", "I(rA),rB", "11 0x4  IIIII AAAAA BBBB BIII IIII IIII", EFI,
448 
   0, it_store},
449 
  {"l.sw", "I(rA),rB", "11 0x5  IIIII AAAAA BBBB BIII IIII IIII",
450 
   EF (l_sw), 0, it_store},
451 
  {"l.sb", "I(rA),rB", "11 0x6  IIIII AAAAA BBBB BIII IIII IIII",
452 
   EF (l_sb), 0, it_store},
453 
  {"l.sh", "I(rA),rB", "11 0x7  IIIII AAAAA BBBB BIII IIII IIII",
454 
   EF (l_sh), 0, it_store},
455 
 
456 
  {"l.add", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0",
457 
   EF (l_add), OR32_W_FLAG, it_arith},
458 
  {"l.addc", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1",
459 
   EF (l_addc), OR32_W_FLAG, it_arith},
460 
  {"l.sub", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x2",
461 
   EF (l_sub), 0, it_arith},
462 
  {"l.and", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x3",
463 
   EF (l_and), OR32_W_FLAG, it_arith},
464 
  {"l.or", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x4",
465 
   EF (l_or), 0, it_arith},
466 
  {"l.xor", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x5",
467 
   EF (l_xor), 0, it_arith},
468 
  {"l.mul", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x6",
469 
   EF (l_mul), 0, it_arith},
470 
 
471 
  {"l.sll", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0x8",
472 
   EF (l_sll), 0, it_shift},
473 
  {"l.srl", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0x8",
474 
   EF (l_srl), 0, it_shift},
475 
  {"l.sra", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0x8",
476 
   EF (l_sra), 0, it_shift},
477 122 jeremybenn 
  {"l.ror", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0x8",
478 
   EF (l_ror), 0, it_shift},
479 19 jeremybenn 
  {"l.div", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x9",
480 
   EF (l_div), 0, it_arith},
481 
  {"l.divu", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xA",
482 
   EF (l_divu), 0, it_arith},
483 118 jeremybenn 
  {"l.mulu", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xB",
484 
   EF (l_mulu), 0, it_arith},
485 19 jeremybenn 
  {"l.extbs", "rD,rA", "11 0x8  DDDDD AAAAA ---- --00 01-- 0xC",
486 
   EF (l_extbs), 0, it_move},
487 
  {"l.exths", "rD,rA", "11 0x8  DDDDD AAAAA ---- --00 00-- 0xC",
488 
   EF (l_exths), 0, it_move},
489 
  {"l.extws", "rD,rA", "11 0x8  DDDDD AAAAA ---- --00 00-- 0xD",
490 
   EF (l_extws), 0, it_move},
491 
  {"l.extbz", "rD,rA", "11 0x8  DDDDD AAAAA ---- --00 11-- 0xC",
492 
   EF (l_extbz), 0, it_move},
493 
  {"l.exthz", "rD,rA", "11 0x8  DDDDD AAAAA ---- --00 10-- 0xC",
494 
   EF (l_exthz), 0, it_move},
495 
  {"l.extwz", "rD,rA", "11 0x8  DDDDD AAAAA ---- --00 01-- 0xD",
496 
   EF (l_extwz), 0, it_move},
497 
  {"l.cmov", "rD,rA,rB", "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xE",
498 
   EF (l_cmov), OR32_R_FLAG, it_move},
499 
  {"l.ff1", "rD,rA", "11 0x8  DDDDD AAAAA ---- --00 ---- 0xF",
500 
   EF (l_ff1), 0, it_arith},
501 115 jeremybenn 
  {"l.fl1", "rD,rA", "11 0x8  DDDDD AAAAA ---- --01 ---- 0xF",
502 
   EF (l_fl1), 0, it_arith},
503 19 jeremybenn 
 
504 
  {"l.sfeq", "rA,rB", "11 0x9  00000 AAAAA BBBB B--- ---- ----",
505 
   EF (l_sfeq), OR32_W_FLAG, it_compare},
506 
  {"l.sfne", "rA,rB", "11 0x9  00001 AAAAA BBBB B--- ---- ----",
507 
   EF (l_sfne), OR32_W_FLAG, it_compare},
508 
  {"l.sfgtu", "rA,rB", "11 0x9  00010 AAAAA BBBB B--- ---- ----",
509 
   EF (l_sfgtu), OR32_W_FLAG, it_compare},
510 
  {"l.sfgeu", "rA,rB", "11 0x9  00011 AAAAA BBBB B--- ---- ----",
511 
   EF (l_sfgeu), OR32_W_FLAG, it_compare},
512 
  {"l.sfltu", "rA,rB", "11 0x9  00100 AAAAA BBBB B--- ---- ----",
513 
   EF (l_sfltu), OR32_W_FLAG, it_compare},
514 
  {"l.sfleu", "rA,rB", "11 0x9  00101 AAAAA BBBB B--- ---- ----",
515 
   EF (l_sfleu), OR32_W_FLAG, it_compare},
516 
  {"l.sfgts", "rA,rB", "11 0x9  01010 AAAAA BBBB B--- ---- ----",
517 
   EF (l_sfgts), OR32_W_FLAG, it_compare},
518 
  {"l.sfges", "rA,rB", "11 0x9  01011 AAAAA BBBB B--- ---- ----",
519 
   EF (l_sfges), OR32_W_FLAG, it_compare},
520 
  {"l.sflts", "rA,rB", "11 0x9  01100 AAAAA BBBB B--- ---- ----",
521 
   EF (l_sflts), OR32_W_FLAG, it_compare},
522 
  {"l.sfles", "rA,rB", "11 0x9  01101 AAAAA BBBB B--- ---- ----",
523 
   EF (l_sfles), OR32_W_FLAG, it_compare},
524 
 
525 
  {"l.cust5", "rD,rA,rB,L,K", "11 0xC  DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI,
526 
   0, it_unknown},
527 
  {"l.cust6", "", "11 0xD  ----- ----- ---- ---- ---- ----", EFI,
528 
   0, it_unknown},
529 
  {"l.cust7", "", "11 0xE  ----- ----- ---- ---- ---- ----", EFI,
530 
   0, it_unknown},
531 
  {"l.cust8", "", "11 0xF  ----- ----- ---- ---- ---- ----", EFI,
532 
   0, it_unknown},
533 
 
534 
/* This section should not be defined in or1ksim, since it contains duplicates,
535 
   which would cause machine builder to complain.  */
536 
#ifdef HAS_CUST
537 
  {"l.cust5_1", "rD", "11 0xC  DDDDD ----- ---- ---- ---- ----", EFI,
538 
   0, it_unknown},
539 
  {"l.cust5_2", "rD,rA", "11 0xC  DDDDD AAAAA ---- ---- ---- ----", EFI,
540 
   0, it_unknown},
541 
  {"l.cust5_3", "rD,rA,rB", "11 0xC  DDDDD AAAAA BBBB B--- ---- ----", EFI,
542 
   0, it_unknown},
543 
 
544 
  {"l.cust6_1", "rD", "11 0xD  DDDDD ----- ---- ---- ---- ----", EFI,
545 
   0, it_unknown},
546 
  {"l.cust6_2", "rD,rA", "11 0xD  DDDDD AAAAA ---- ---- ---- ----", EFI,
547 
   0, it_unknown},
548 
  {"l.cust6_3", "rD,rA,rB", "11 0xD  DDDDD AAAAA BBBB B--- ---- ----", EFI,
549 
   0, it_unknown},
550 
 
551 
  {"l.cust7_1", "rD", "11 0xE  DDDDD ----- ---- ---- ---- ----", EFI,
552 
   0, it_unknown},
553 
  {"l.cust7_2", "rD,rA", "11 0xE  DDDDD AAAAA ---- ---- ---- ----", EFI,
554 
   0, it_unknown},
555 
  {"l.cust7_3", "rD,rA,rB", "11 0xE  DDDDD AAAAA BBBB B--- ---- ----", EFI,
556 
   0, it_unknown},
557 
 
558 
  {"l.cust8_1", "rD", "11 0xF  DDDDD ----- ---- ---- ---- ----", EFI,
559 
   0, it_unknown},
560 
  {"l.cust8_2", "rD,rA", "11 0xF  DDDDD AAAAA ---- ---- ---- ----", EFI,
561 
   0, it_unknown},
562 
  {"l.cust8_3", "rD,rA,rB", "11 0xF  DDDDD AAAAA BBBB B--- ---- ----", EFI,
563 
   0, it_unknown},
564 
#endif
565 
 
566 
  {"", "", "", EFI, 0, 0} /* Dummy entry, not included in num_opcodes.  This
567 
                                 * lets code examine entry i+1 without checking
568 
                                 * if we've run off the end of the table.  */
569 
};
570 
 
571 
#undef EFI
572 
#undef EFN
573 
#undef EF
574 
 
575 230 jeremybenn 
static CONST int NUM_OPCODES =
576 
  ((sizeof (or1ksim_or32_opcodes)) / (sizeof (struct or32_opcode))) - 1;
577 19 jeremybenn 
 
578 
/* Calculates instruction length in bytes. Always 4 for OR32. */
579 
int
580 230 jeremybenn 
or1ksim_insn_len (int insn_index)
581 19 jeremybenn 
{
582 
  insn_index = 0;                /* Just to get rid that warning.  */
583 
  return 4;
584 
}
585 
 
586 
/* Is individual insn's operand signed or unsigned? */
587 230 jeremybenn 
static int
588 19 jeremybenn 
letter_signed (char l)
589 
{
590 
  CONST struct or32_letter *pletter;
591 
 
592 
  for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
593 
    if (pletter->letter == l)
594 
      return pletter->sign;
595 
 
596 
  printf ("letter_signed(%c): Unknown letter.\n", l);
597 
  return 0;
598 
}
599 
 
600 
/* Simple cache for letter ranges */
601 
static int range_cache[256] = { 0 };
602 
 
603 
/* Number of letters in the individual lettered operand. */
604 230 jeremybenn 
static int
605 19 jeremybenn 
letter_range (char l)
606 
{
607 
  CONST struct or32_opcode *pinsn;
608 
  char *enc;
609 
  int range = 0;
610 
 
611 
  /* Is value cached? */
612 
  if ((range = range_cache[(unsigned char) l]))
613 
    return range;
614 
 
615 230 jeremybenn 
  for (pinsn = or1ksim_or32_opcodes; strlen (pinsn->name); pinsn++)
616 19 jeremybenn 
    {
617 
      if (strchr (pinsn->encoding, l))
618 
        {
619 
          for (enc = pinsn->encoding; *enc != '\0'; enc++)
620 
            if ((*enc == '0') && (*(enc + 1) == 'x'))
621 
              enc += 2;
622 
            else if (*enc == l)
623 
              range++;
624 
          return range_cache[(unsigned char) l] = range;
625 
        }
626 
    }
627 
 
628 
  printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
629 
  exit (1);
630 
}
631 
 
632 
/* Returns name of the specified instruction index */
633 
CONST char *
634 230 jeremybenn 
or1ksim_insn_name (int index)
635 19 jeremybenn 
{
636 230 jeremybenn 
  if (index >= 0 && index < NUM_OPCODES)
637 
    return or1ksim_or32_opcodes[index].name;
638 19 jeremybenn 
  else
639 
    return "???";
640 
}
641 
 
642 
/*** Finite automata for instruction decoding building code ***/
643 
 
644 
/* Find symbols in encoding.  */
645 230 jeremybenn 
static unsigned long
646 19 jeremybenn 
insn_extract (param_ch, enc_initial)
647 
     char param_ch;
648 
     char *enc_initial;
649 
{
650 
  char *enc;
651 
  unsigned long ret = 0;
652 
  unsigned opc_pos = 32;
653 
  for (enc = enc_initial; *enc != '\0';)
654 
    if ((*enc == '0') && (*(enc + 1) == 'x'))
655 
      {
656 
        unsigned long tmp = strtol (enc + 2, NULL, 16);
657 
        opc_pos -= 4;
658 
        if (param_ch == '0' || param_ch == '1')
659 
          {
660 
            if (param_ch == '0')
661 
              tmp = 15 - tmp;
662 
            ret |= tmp << opc_pos;
663 
          }
664 
        enc += 3;
665 
      }
666 
    else
667 
      {
668 240 julius 
        if (*enc == '0' || *enc == '1' || *enc == '-' || isalpha ((int)*enc))
669 19 jeremybenn 
          {
670 
            opc_pos--;
671 
            if (param_ch == *enc)
672 
              ret |= 1 << opc_pos;
673 
          }
674 
        enc++;
675 
      }
676 
  return ret;
677 
}
678 
 
679 
#define MAX_AUTOMATA_SIZE (1200)
680 
#define MAX_OP_TABLE_SIZE (1200)
681 
#define MAX_LEN           (8)
682 
 
683 
#ifndef MIN
684 
# define MIN(x,y)          ((x) < (y) ? (x) : (y))
685 
#endif
686 
 
687 230 jeremybenn 
unsigned long *or1ksim_automata;
688 19 jeremybenn 
int nuncovered;
689 
int curpass = 0;
690 
 
691 
/* MM: Struct that holds runtime build information about instructions.  */
692 230 jeremybenn 
struct temp_insn_struct *or1ksim_ti;
693 19 jeremybenn 
 
694 230 jeremybenn 
static struct insn_op_struct *op_data;
695 19 jeremybenn 
 
696 230 jeremybenn 
struct insn_op_struct **or1ksim_op_start;
697 
 
698 19 jeremybenn 
static void
699 
or32_debug (int level, const char *format, ...)
700 
{
701 
#if DEBUG
702 
  char *p;
703 
  va_list ap;
704 
 
705 
  if ((p = malloc (1000)) == NULL)
706 
    return;
707 
  va_start (ap, format);
708 
  (void) vsnprintf (p, 1000, format, ap);
709 
  va_end (ap);
710 
  printf ("%s\n", p);
711 
  fflush (stdout);
712 
  free (p);
713 
#endif
714 
}
715 
 
716 
/* Recursive utility function used to find best match and to build automata.  */
717 
static unsigned long *
718 
cover_insn (unsigned long *cur, int pass, unsigned int mask)
719 
{
720 
  int best_first = 0, best_len = 0, i, last_match = -1, ninstr = 0;
721 
  unsigned long cur_mask = mask;
722 
  unsigned long *next;
723 
 
724 230 jeremybenn 
  for (i = 0; i < NUM_OPCODES; i++)
725 
    if (or1ksim_ti[i].in_pass == pass)
726 19 jeremybenn 
      {
727 230 jeremybenn 
        cur_mask &= or1ksim_ti[i].insn_mask;
728 19 jeremybenn 
        ninstr++;
729 
        last_match = i;
730 
      }
731 
 
732 
  or32_debug (8, "%08X %08lX\n", mask, cur_mask);
733 
  if (ninstr == 0)
734 
    return 0;
735 
  if (ninstr == 1)
736 
    {
737 
      /* Leaf holds instruction index. */
738 230 jeremybenn 
      or32_debug (8, "%i>I%i %s\n", cur - or1ksim_automata, last_match,
739 
             or1ksim_or32_opcodes[last_match].name);
740 19 jeremybenn 
      *cur = LEAF_FLAG | last_match;
741 
      cur++;
742 
      nuncovered--;
743 
    }
744 
  else
745 
    {
746 
      /* Find longest match.  */
747 
      for (i = 0; i < 32; i++)
748 
        {
749 
          int len;
750 
          for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
751 
            {
752 
              unsigned long m = (1UL << ((unsigned long) len)) - 1;
753 
              or32_debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)", len, m,
754 
                     cur_mask, i, (cur_mask >> (unsigned) i),
755 
                     (cur_mask >> (unsigned) i) & m);
756 
              if ((m & (cur_mask >> (unsigned) i)) == m)
757 
                {
758 
                  best_len = len;
759 
                  best_first = i;
760 
                  or32_debug (9, "!");
761 
                }
762 
              else
763 
                break;
764 
            }
765 
        }
766 
      or32_debug (9, "\n");
767 
      if (!best_len)
768 
        {
769 
          fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr,
770 
                   mask);
771 230 jeremybenn 
          for (i = 0; i < NUM_OPCODES; i++)
772 
            if (or1ksim_ti[i].in_pass == pass)
773 
              fprintf (stderr, "%s ", or1ksim_or32_opcodes[i].name);
774 19 jeremybenn 
 
775 
          fprintf (stderr, "\n");
776 
          exit (1);
777 
        }
778 230 jeremybenn 
      or32_debug (8, "%i> #### %i << %i (%i) ####\n", cur - or1ksim_automata, best_len,
779 19 jeremybenn 
             best_first, ninstr);
780 
      *cur = best_first;
781 
      cur++;
782 
      *cur = (1 << best_len) - 1;
783 
      cur++;
784 
      next = cur;
785 
      /* Allocate space for pointers.  */
786 
      cur += 1 << best_len;
787 
      cur_mask = (1 << (unsigned long) best_len) - 1;
788 
 
789 
      for (i = 0; i < (1 << (unsigned long) best_len); i++)
790 
        {
791 
          int j;
792 
          unsigned long *c;
793 
          curpass++;
794 230 jeremybenn 
          for (j = 0; j < NUM_OPCODES; j++)
795 
            if (or1ksim_ti[j].in_pass == pass
796 
                && ((or1ksim_ti[j].insn >> best_first) & cur_mask) ==
797 19 jeremybenn 
                (unsigned long) i
798 230 jeremybenn 
                && ((or1ksim_ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
799 
              or1ksim_ti[j].in_pass = curpass;
800 19 jeremybenn 
 
801 
          or32_debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first);
802 
          c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
803 
          if (c)
804 
            {
805 230 jeremybenn 
              or32_debug (8, "%i> #%X -> %u\n", next - or1ksim_automata, i,
806 
                     cur - or1ksim_automata);
807 
              *next = cur - or1ksim_automata;
808 19 jeremybenn 
              cur = c;
809 
            }
810 
          else
811 
            {
812 230 jeremybenn 
              or32_debug (8, "%i> N/A\n", next - or1ksim_automata);
813 19 jeremybenn 
              *next = 0;
814 
            }
815 
          next++;
816 
        }
817 
    }
818 
  return cur;
819 
}
820 
 
821 
/* Returns number of nonzero bits. */
822 
static int
823 
num_ones (unsigned long value)
824 
{
825 
  int c = 0;
826 
  while (value)
827 
    {
828 
      if (value & 1)
829 
        c++;
830 
      value >>= 1;
831 
    }
832 
  return c;
833 
}
834 
 
835 
/* Utility function, which converts parameters from or32_opcode format to more binary form.
836 230 jeremybenn 
   Parameters are stored in or1ksim_ti struct.  */
837 19 jeremybenn 
 
838 
static struct insn_op_struct *
839 
parse_params (CONST struct or32_opcode *opcode, struct insn_op_struct *cur)
840 
{
841 
  char *args = opcode->args;
842 
  int i, type;
843 
  int num_cur_op = 0;;
844 
 
845 
  i = 0;
846 
  type = 0;
847 
  /* In case we don't have any parameters, we add dummy read from r0.  */
848 
  if (!(*args))
849 
    {
850 
      cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
851 
      cur->data = 0;
852 
      or32_debug (9, "#%08lX %08lX\n", cur->type, cur->data);
853 
      cur++;
854 
      return cur;
855 
    }
856 
 
857 
  while (*args != '\0')
858 
    {
859 
      if (*args == 'r')
860 
        {
861 
          args++;
862 
          type |= OPTYPE_REG;
863 
          if (*args == 'D')
864 
            type |= OPTYPE_DST;
865 
        }
866 240 julius 
      else if (isalpha ((int)*args))
867 19 jeremybenn 
        {
868 
          unsigned long arg;
869 
          arg = insn_extract (*args, opcode->encoding);
870 
          or32_debug (9, "%s : %08lX ------\n", opcode->name, arg);
871 
          if (letter_signed (*args))
872 
            {
873 
              type |= OPTYPE_SIG;
874 
              type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
875 
            }
876 
 
877 
          num_cur_op = 0;
878 
          /* Split argument to sequences of consecutive ones.  */
879 
          while (arg)
880 
            {
881 
              int shr = 0;
882 
              unsigned long tmp = arg, mask = 0;
883 
              while ((tmp & 1) == 0)
884 
                {
885 
                  shr++;
886 
                  tmp >>= 1;
887 
                }
888 
              while (tmp & 1)
889 
                {
890 
                  mask++;
891 
                  tmp >>= 1;
892 
                }
893 
              cur->type = type | shr;
894 
              cur->data = mask;
895 
              arg &= ~(((1 << mask) - 1) << shr);
896 
              or32_debug (6, "|%08lX %08lX\n", cur->type, cur->data);
897 
              cur++;
898 
              num_cur_op++;
899 
            }
900 
          args++;
901 
        }
902 
      else if (*args == '(')
903 
        {
904 
          /* Next param is displacement.  Later we will treat them as one operand.  */
905 
          /* Set the OPTYPE_DIS flag on all insn_op_structs that belong to this
906 
           * operand */
907 
          while (num_cur_op > 0)
908 
            {
909 
              cur[-num_cur_op].type |= type | OPTYPE_DIS;
910 
              num_cur_op--;
911 
            }
912 
          cur[-1].type |= OPTYPE_OP;
913 
          or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
914 
          type = 0;
915 
          i++;
916 
          args++;
917 
        }
918 
      else if (*args == OPERAND_DELIM)
919 
        {
920 
          cur--;
921 
          cur->type = type | cur->type | OPTYPE_OP;
922 
          or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
923 
          cur++;
924 
          type = 0;
925 
          i++;
926 
          args++;
927 
        }
928 
      else if (*args == '0')
929 
        {
930 
          cur->type = type;
931 
          cur->data = 0;
932 
          or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
933 
          cur++;
934 
          type = 0;
935 
          i++;
936 
          args++;
937 
        }
938 
      else if (*args == ')')
939 
        args++;
940 
      else
941 
        {
942 
          fprintf (stderr, "%s : parse error in args.\n", opcode->name);
943 
          exit (1);
944 
        }
945 
    }
946 
  cur--;
947 
  cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
948 
  or32_debug (9, "#%08lX %08lX\n", cur->type, cur->data);
949 
  cur++;
950 
  return cur;
951 
}
952 
 
953 220 jeremybenn 
/* -------------------------------------------------------------------------- */
954 230 jeremybenn 
/*!Constructs new automata based on or1ksim_or32_opcodes array.
955 19 jeremybenn 
 
956 220 jeremybenn 
   @param[in] quiet  If non-zero (TRUE) do not print informational messages. */
957 
/* -------------------------------------------------------------------------- */
958 19 jeremybenn 
void
959 230 jeremybenn 
or1ksim_build_automata (int  quiet)
960 19 jeremybenn 
{
961 
  int i;
962 
  unsigned long *end;
963 
  struct insn_op_struct *cur;
964 
 
965 230 jeremybenn 
  or1ksim_automata =
966 19 jeremybenn 
    (unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
967 230 jeremybenn 
  or1ksim_ti =
968 19 jeremybenn 
    (struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) *
969 230 jeremybenn 
                                        NUM_OPCODES);
970 19 jeremybenn 
 
971 230 jeremybenn 
  nuncovered = NUM_OPCODES;
972 19 jeremybenn 
 
973 
#ifdef HAVE_EXECUTION
974 220 jeremybenn 
  if (!quiet)
975 
    {
976 
      printf ("Building automata... ");
977 
    }
978 19 jeremybenn 
#endif
979 
 
980 
  /* Build temporary information about instructions.  */
981 230 jeremybenn 
  for (i = 0; i < NUM_OPCODES; i++)
982 19 jeremybenn 
    {
983 
      unsigned long ones, zeros;
984 230 jeremybenn 
      char *encoding = or1ksim_or32_opcodes[i].encoding;
985 19 jeremybenn 
      ones = insn_extract ('1', encoding);
986 
      zeros = insn_extract ('0', encoding);
987 230 jeremybenn 
      or1ksim_ti[i].insn_mask = ones | zeros;
988 
      or1ksim_ti[i].insn = ones;
989 
      or1ksim_ti[i].in_pass = curpass = 0;
990 
      /*debug(9, "%s: %s %08X %08X\n", or1ksim_or32_opcodes[i].name,
991 
         or1ksim_or32_opcodes[i].encoding, or1ksim_ti[i].insn_mask, or1ksim_ti[i].insn); */
992 19 jeremybenn 
    }
993 
 
994 
  /* Until all are covered search for best criteria to separate them.  */
995 230 jeremybenn 
  end = cover_insn (or1ksim_automata, curpass, 0xFFFFFFFF);
996 
  if (end - or1ksim_automata > MAX_AUTOMATA_SIZE)
997 19 jeremybenn 
    {
998 
      fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
999 
      exit (1);
1000 
    }
1001 
#ifdef HAVE_EXECUTION
1002 220 jeremybenn 
  if (!quiet)
1003 
    {
1004 230 jeremybenn 
      printf ("done, num uncovered: %i/%i.\n", nuncovered, NUM_OPCODES);
1005 220 jeremybenn 
    }
1006 19 jeremybenn 
#endif
1007 
 
1008 
#ifdef HAVE_EXECUTION
1009 220 jeremybenn 
  if (!quiet)
1010 
    {
1011 
      printf ("Parsing operands data... ");
1012 
    }
1013 19 jeremybenn 
#endif
1014 
  op_data =
1015 
    (struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE *
1016 
                                      sizeof (struct insn_op_struct));
1017 230 jeremybenn 
  or1ksim_op_start =
1018 
    (struct insn_op_struct **) malloc (NUM_OPCODES *
1019 19 jeremybenn 
                                       sizeof (struct insn_op_struct *));
1020 
  cur = op_data;
1021 230 jeremybenn 
  for (i = 0; i < NUM_OPCODES; i++)
1022 19 jeremybenn 
    {
1023 230 jeremybenn 
      or1ksim_op_start[i] = cur;
1024 
      cur = parse_params (&or1ksim_or32_opcodes[i], cur);
1025 19 jeremybenn 
      if (cur - op_data > MAX_OP_TABLE_SIZE)
1026 
        {
1027 
          fprintf (stderr,
1028 
                   "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
1029 
          exit (1);
1030 
        }
1031 
    }
1032 
#ifdef HAVE_EXECUTION
1033 220 jeremybenn 
  if (!quiet)
1034 
    {
1035 
      printf ("done.\n");
1036 
    }
1037 19 jeremybenn 
#endif
1038 
}
1039 
 
1040 
void
1041 230 jeremybenn 
or1ksim_destruct_automata ()
1042 19 jeremybenn 
{
1043 230 jeremybenn 
  free (or1ksim_ti);
1044 
  free (or1ksim_automata);
1045 19 jeremybenn 
  free (op_data);
1046 230 jeremybenn 
  free (or1ksim_op_start);
1047 19 jeremybenn 
}
1048 
 
1049 
/* Decodes instruction and returns instruction index.  */
1050 
int
1051 230 jeremybenn 
or1ksim_insn_decode (unsigned int insn)
1052 19 jeremybenn 
{
1053 230 jeremybenn 
  unsigned long *a = or1ksim_automata;
1054 19 jeremybenn 
  int i;
1055 
  while (!(*a & LEAF_FLAG))
1056 
    {
1057 
      unsigned int first = *a;
1058 230 jeremybenn 
      //debug(9, "%i ", a - or1ksim_automata);
1059 19 jeremybenn 
      a++;
1060 
      i = (insn >> first) & *a;
1061 
      a++;
1062 
      if (!*(a + i))
1063 
        {                       /* Invalid instruction found?  */
1064 
          //debug(9, "XXX\n", i);
1065 
          return -1;
1066 
        }
1067 230 jeremybenn 
      a = or1ksim_automata + *(a + i);
1068 19 jeremybenn 
    }
1069 
  i = *a & ~LEAF_FLAG;
1070 
  //debug(9, "%i\n", i);
1071 
  /* Final check - do we have direct match?
1072 230 jeremybenn 
     (based on or1ksim_or32_opcodes this should be the only possibility,
1073 19 jeremybenn 
     but in case of invalid/missing instruction we must perform a check)  */
1074 230 jeremybenn 
  if ((or1ksim_ti[i].insn_mask & insn) == or1ksim_ti[i].insn)
1075 19 jeremybenn 
    return i;
1076 
  else
1077 
    return -1;
1078 
}
1079 
 
1080 
static char disassembled_str[50];
1081 230 jeremybenn 
char *or1ksim_disassembled = &disassembled_str[0];
1082 19 jeremybenn 
 
1083 420 jeremybenn 
/* trace data */
1084 
int           trace_dest_reg;
1085 
int           trace_store_addr_reg;
1086 
unsigned int  trace_store_imm;
1087 
int           trace_store_val_reg;
1088 
int           trace_store_width;
1089 458 julius 
int           trace_dest_spr;
1090 420 jeremybenn 
 
1091 19 jeremybenn 
/* Automagically does zero- or sign- extension and also finds correct
1092 
   sign bit position if sign extension is correct extension. Which extension
1093 
   is proper is figured out from letter description. */
1094 
 
1095 
unsigned long
1096 230 jeremybenn 
or1ksim_extend_imm (unsigned long imm, char l)
1097 19 jeremybenn 
{
1098 
  unsigned long mask;
1099 
  int letter_bits;
1100 
 
1101 
  /* First truncate all bits above valid range for this letter
1102 
     in case it is zero extend. */
1103 
  letter_bits = letter_range (l);
1104 
  mask = (1 << letter_bits) - 1;
1105 
  imm &= mask;
1106 
 
1107 
  /* Do sign extend if this is the right one. */
1108 
  if (letter_signed (l) && (imm >> (letter_bits - 1)))
1109 
    imm |= (~mask);
1110 
 
1111 
  return imm;
1112 
}
1113 
 
1114 
unsigned long
1115 230 jeremybenn 
or1ksim_or32_extract (param_ch, enc_initial, insn)
1116 19 jeremybenn 
     char param_ch;
1117 
     char *enc_initial;
1118 
     unsigned long insn;
1119 
{
1120 
  char *enc;
1121 
  unsigned long ret = 0;
1122 
  int opc_pos = 0;
1123 
  int param_pos = 0;
1124 
 
1125 
  for (enc = enc_initial; *enc != '\0'; enc++)
1126 
    if (*enc == param_ch)
1127 
      {
1128 
        if (enc - 2 >= enc_initial && (*(enc - 2) == '0')
1129 
            && (*(enc - 1) == 'x'))
1130 
          continue;
1131 
        else
1132 
          param_pos++;
1133 
      }
1134 
 
1135 
#if DEBUG
1136 230 jeremybenn 
  printf ("or1ksim_or32_extract: %x ", param_pos);
1137 19 jeremybenn 
#endif
1138 
  opc_pos = 32;
1139 
  for (enc = enc_initial; *enc != '\0';)
1140 
    if ((*enc == '0') && (*(enc + 1) == 'x'))
1141 
      {
1142 
        opc_pos -= 4;
1143 
        if ((param_ch == '0') || (param_ch == '1'))
1144 
          {
1145 
            unsigned long tmp = strtol (enc, NULL, 16);
1146 
#if DEBUG
1147 
            printf (" enc=%s, tmp=%x ", enc, tmp);
1148 
#endif
1149 
            if (param_ch == '0')
1150 
              tmp = 15 - tmp;
1151 
            ret |= tmp << opc_pos;
1152 
          }
1153 
        enc += 3;
1154 
      }
1155 
    else if ((*enc == '0') || (*enc == '1'))
1156 
      {
1157 
        opc_pos--;
1158 
        if (param_ch == *enc)
1159 
          ret |= 1 << opc_pos;
1160 
        enc++;
1161 
      }
1162 
    else if (*enc == param_ch)
1163 
      {
1164 
        opc_pos--;
1165 
        param_pos--;
1166 
#if DEBUG
1167 
        printf ("\n  ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos,
1168 
                param_pos);
1169 
#endif
1170 240 julius 
        if (islower ((int) param_ch))
1171 19 jeremybenn 
          ret -= ((insn >> opc_pos) & 0x1) << param_pos;
1172 
        else
1173 
          ret += ((insn >> opc_pos) & 0x1) << param_pos;
1174 
        enc++;
1175 
      }
1176 240 julius 
    else if (isalpha ((int)*enc))
1177 19 jeremybenn 
      {
1178 
        opc_pos--;
1179 
        enc++;
1180 
      }
1181 
    else if (*enc == '-')
1182 
      {
1183 
        opc_pos--;
1184 
        enc++;
1185 
      }
1186 
    else
1187 
      enc++;
1188 
 
1189 
#if DEBUG
1190 
  printf ("ret=%x\n", ret);
1191 
#endif
1192 
  return ret;
1193 
}
1194 
 
1195 
/* Print register. Used only by print_insn. */
1196 
 
1197 
static char *
1198 
or32_print_register (dest, param_ch, encoding, insn)
1199 
     char *dest;
1200 
     char param_ch;
1201 
     char *encoding;
1202 
     unsigned long insn;
1203 
{
1204 230 jeremybenn 
  int regnum = or1ksim_or32_extract (param_ch, encoding, insn);
1205 19 jeremybenn 
 
1206 
  sprintf (dest, "r%d", regnum);
1207 
  while (*dest)
1208 
    dest++;
1209 
  return dest;
1210 
}
1211 
 
1212 
/* Print immediate. Used only by print_insn. */
1213 
 
1214 
static char *
1215 
or32_print_immediate (dest, param_ch, encoding, insn)
1216 
     char *dest;
1217 
     char param_ch;
1218 
     char *encoding;
1219 
     unsigned long insn;
1220 
{
1221 230 jeremybenn 
  int imm = or1ksim_or32_extract (param_ch, encoding, insn);
1222 19 jeremybenn 
 
1223 230 jeremybenn 
  imm = or1ksim_extend_imm (imm, param_ch);
1224 19 jeremybenn 
 
1225 
  if (letter_signed (param_ch))
1226 
    {
1227 
      if (imm < 0)
1228 
        sprintf (dest, "%d", imm);
1229 
      else
1230 
        sprintf (dest, "0x%x", imm);
1231 
    }
1232 
  else
1233 
    sprintf (dest, "%#x", imm);
1234 
  while (*dest)
1235 
    dest++;
1236 
  return dest;
1237 
}
1238 
 
1239 
/* Disassemble one instruction from insn to disassemble.
1240 
   Return the size of the instruction.  */
1241 
 
1242 
int
1243 230 jeremybenn 
or1ksim_disassemble_insn (insn)
1244 19 jeremybenn 
     unsigned long insn;
1245 
{
1246 230 jeremybenn 
  return or1ksim_disassemble_index (insn, or1ksim_insn_decode (insn));
1247 19 jeremybenn 
}
1248 
 
1249 
/* Disassemble one instruction from insn index.
1250 
   Return the size of the instruction.  */
1251 
 
1252 
int
1253 230 jeremybenn 
or1ksim_disassemble_index (insn, index)
1254 19 jeremybenn 
     unsigned long insn;
1255 
     int index;
1256 
{
1257 230 jeremybenn 
  char *dest = or1ksim_disassembled;
1258 19 jeremybenn 
  if (index >= 0)
1259 
    {
1260 230 jeremybenn 
      struct or32_opcode const *opcode = &or1ksim_or32_opcodes[index];
1261 19 jeremybenn 
      char *s;
1262 
 
1263 
      strcpy (dest, opcode->name);
1264 
      while (*dest)
1265 
        dest++;
1266 
      *dest++ = ' ';
1267 
      *dest = 0;
1268 
 
1269 
      for (s = opcode->args; *s != '\0'; ++s)
1270 
        {
1271 
          switch (*s)
1272 
            {
1273 
            case '\0':
1274 230 jeremybenn 
              return or1ksim_insn_len (insn);
1275 19 jeremybenn 
 
1276 
            case 'r':
1277 
              dest = or32_print_register (dest, *++s, opcode->encoding, insn);
1278 
              break;
1279 
 
1280 
            default:
1281 
              if (strchr (opcode->encoding, *s))
1282 
                dest =
1283 
                  or32_print_immediate (dest, *s, opcode->encoding, insn);
1284 
              else
1285 
                {
1286 
                  *dest++ = *s;
1287 
                  *dest = 0;
1288 
                }
1289 
            }
1290 
        }
1291 
    }
1292 
  else
1293 
    {
1294 
      /* This used to be %8x for binutils.  */
1295 
      sprintf (dest, ".word 0x%08lx", insn);
1296 
      while (*dest)
1297 
        dest++;
1298 
    }
1299 230 jeremybenn 
  return or1ksim_insn_len (insn);
1300 19 jeremybenn 
}
1301 420 jeremybenn 
 
1302 
 
1303 
/* -------------------------------------------------------------------------- */
1304 
/*!Disassemble one instruction for tracing.
1305 
 
1306 
   A simplified form of  or1ksim_disassemble_index.
1307 
 
1308 
   @param[in] insn  The instruction to disassemble
1309 
   @param[in] index  Index into the opcode table.                             */
1310 
/* -------------------------------------------------------------------------- */
1311 
void
1312 
or1ksim_disassemble_trace_index (unsigned long int  insn,
1313 
                                 int                index)
1314 
{
1315 
  int                i;
1316 
  char              *dest        = or1ksim_disassembled;
1317 
 
1318 
  /* Set trace result defaults. */
1319 
  trace_dest_reg       = -1;
1320 458 julius 
  trace_dest_spr       = -1;
1321 420 jeremybenn 
  trace_store_addr_reg = -1;
1322 
  trace_store_imm      =  0;
1323 
  trace_store_val_reg  = -1;
1324 
  trace_store_width    =  0;     /* Non-zero if we have a store */
1325 
 
1326 
  if (index >= 0)
1327 
    {
1328 
      const int  OPC_WIDTH = 8;
1329 
 
1330 
      struct or32_opcode const *opcode = &or1ksim_or32_opcodes[index];
1331 
      char                     *s;
1332 
 
1333 
      /* Is it a store opcode? */
1334 
      if (0 == strcmp ("l.sb", opcode->name))
1335 
        {
1336 
          trace_store_width = 1;
1337 
        }
1338 
      else if (0 == strcmp ("l.sh", opcode->name))
1339 
        {
1340 
          trace_store_width = 2;
1341 
        }
1342 
      else if (0 == strcmp ("l.sw", opcode->name))
1343 
        {
1344 
          trace_store_width = 4;
1345 
        }
1346 
 
1347 458 julius 
      /* Is it a move to SPR opcode? */
1348 
      if (0 == strcmp ("l.mtspr", opcode->name))
1349 
        {
1350 
          trace_dest_spr = 1;
1351 
        }
1352 
 
1353 420 jeremybenn 
      /* Copy the opcode and pad */
1354 
      strcpy (dest, opcode->name);
1355 
 
1356 
      for (i = 0; i < OPC_WIDTH; i++)
1357 
        {
1358 
          if ('\0' == dest[0])
1359 
            {
1360 
              dest[0] = ' ';
1361 
              dest[1] = '\0';
1362 
            }
1363 
 
1364 
          dest++;
1365 
        }
1366 
 
1367 
      for (s = opcode->args; *s != '\0'; ++s)
1368 
        {
1369 
          switch (*s)
1370 
            {
1371 
            case '\0':
1372 
              break;
1373 
 
1374 
            case 'r':
1375 
              dest = or32_print_register (dest, *++s, opcode->encoding, insn);
1376 
 
1377 
              switch (*s)
1378 
                {
1379 
                case 'D':
1380 
                  trace_dest_reg =
1381 
                    or1ksim_or32_extract (*s, opcode->encoding, insn);
1382 
                  break;
1383 
 
1384 
                case 'A':
1385 
                  if (0 != trace_store_width)
1386 
                    {
1387 
                      trace_store_addr_reg =
1388 
                        or1ksim_or32_extract (*s, opcode->encoding, insn);
1389 
                    }
1390 
                  break;
1391 
 
1392 
                case 'B':
1393 
                  if (0 != trace_store_width)
1394 
                    {
1395 
                      trace_store_val_reg =
1396 
                        or1ksim_or32_extract (*s, opcode->encoding, insn);
1397 
                    }
1398 
                  break;
1399 
 
1400 
                }
1401 
 
1402 
              break;
1403 
 
1404 
            default:
1405 
              if (strchr (opcode->encoding, *s))
1406 
                {
1407 
                  dest = or32_print_immediate (dest, *s, opcode->encoding,
1408 
                                               insn);
1409 
 
1410 
                  /* If we have a store instruction, save the immediate. */
1411 
                  if (0 != trace_store_width)
1412 
                    {
1413 
                      trace_store_imm =
1414 
                        or1ksim_or32_extract (*s, opcode->encoding, insn);
1415 
                      trace_store_imm =
1416 
                        or1ksim_extend_imm (trace_store_imm, *s);
1417 
                    }
1418 458 julius 
 
1419 
                  if (1 == trace_dest_spr)
1420 
                  {
1421 
                          trace_dest_spr =
1422 
                                  or1ksim_or32_extract ('K', opcode->encoding,
1423 
                                                        insn);
1424 
                          trace_dest_reg =
1425 
                                  or1ksim_or32_extract ('A', opcode->encoding,
1426 
                                                        insn);
1427 
                  }
1428 
 
1429 420 jeremybenn 
                }
1430 
              else
1431 
                {
1432 
                  *dest++ = *s;
1433 
                  *dest = 0;
1434 
                }
1435 
            }
1436 
        }
1437 
    }
1438 
  else
1439 
    {
1440 
      /* This used to be %8x for binutils.  */
1441 
      sprintf (dest, ".word 0x%08lx", insn);
1442 
      while (*dest)
1443 
        dest++;
1444 
    }
1445 
}       /* or1ksim_disassemble_trace_index () */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.