OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cuc/] [insn.h] - Blame information for rev 784

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jeremybenn
/* insn.h -- OpenRISC Custom Unit Compiler, internal instruction definitions
2
 
3
   Copyright (C) 2002 Marko Mlinar, markom@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
 
27
#ifndef INSN__H
28
#define INSN__H
29
 
30
#include "cuc.h"
31
 
32
/* Instruction types */
33
#define II_ADD   0
34
#define II_SUB   1
35
#define II_AND   2
36
#define II_OR    3
37
#define II_XOR   4
38
#define II_MUL   5
39
#define II_SRL   6
40
#define II_SLL   7
41
#define II_SRA   8
42
#define II_LB    9
43
#define II_LH    10
44
#define II_LW    11
45
#define II_SB    12
46
#define II_SH    13
47
#define II_SW    14
48
#define II_SFEQ  15
49
#define II_SFNE  16
50
#define II_SFLE  17
51
#define II_SFLT  18
52
#define II_SFGE  19
53
#define II_SFGT  20
54
#define II_BF    21
55
#define II_LRBB  22
56
#define II_CMOV  23
57
#define II_REG   24
58
#define II_NOP   25
59
#define II_CALL  26
60
#define II_LAST  26
61
 
62
/* misc flags */
63
#define II_MASK   0x0fff
64
#define II_MEM    0x1000
65
#define II_SIGNED 0x2000
66
 
67
#define II_IS_LOAD(x) ((x) == II_LB || (x) == II_LH || (x) == II_LW)
68
#define II_IS_STORE(x) ((x) == II_SB || (x) == II_SH || (x) == II_SW)
69
#define II_MEM_WIDTH(x) (((x) == II_LB || (x) == II_SB) ? 1 :\
70
                         ((x) == II_LH || (x) == II_SH) ? 2 :\
71
                         ((x) == II_LW || (x) == II_SW) ? 4 : -1)
72
 
73
/* List of known instructions and their rtl representation */
74
typedef struct
75
{
76
  char *name;
77
  int comutative;
78
  char *rtl;
79
} cuc_known_insn;
80
 
81
extern const cuc_known_insn known[II_LAST + 1];
82
 
83
/* Timing table -- same indexes as known table */
84
typedef struct
85
{
86
  double delay;
87
  double size;
88
  double delayi;
89
  double sizei;
90
} cuc_timing_table;
91
 
92
/* Conversion links */
93
typedef struct
94
{
95
  const char *from;
96
  const int to;
97
} cuc_conv;
98
 
99
/* normal (not immediate) size of a function */
100
double ii_size (int index, int imm);
101
 
102
/* Returns instruction size */
103
double insn_time (cuc_insn * ii);
104
 
105
/* Returns instruction time */
106
double insn_size (cuc_insn * ii);
107
 
108
/* Find known instruction and attach them to insn */
109
void change_insn_type (cuc_insn * i, int index);
110
 
111
/* Returns instruction name */
112
const char *cuc_insn_name (cuc_insn * ii);
113
 
114
/* Loads in the specified timings table */
115
void load_timing_table (char *filename);
116
 
117
/* Displays shared instructions */
118
void print_shared (cuc_func * rf, cuc_shared_item * shared, int nshared);
119
 
120
#endif  /* INSN__H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.