URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cuc/] [load.c] - Blame information for rev 602

Go to most recent revision | Details | Compare with Previous | View Log


/* load.c -- OpenRISC Custom Unit Compiler, instruction loading and converting
 *    Copyright (C) 2002 Marko Mlinar, markom@opencores.org
 *
 *    This file is part of OpenRISC 1000 Architectural Simulator.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2 of the License, or
 *    (at your option) any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <assert.h>
 
#include "config.h"
 
#include "port.h"
#include "arch.h"
#include "abstract.h"
#include "sim-config.h"
#include "cuc.h"
#include "opcode/or32.h"
#include "insn.h"
 
static const cuc_conv conv[] = {
{"l.add", II_ADD}, {"l.addi", II_ADD},
{"l.movhi", II_OR},
{"l.sub", II_SUB}, {"l.subi", II_SUB},
{"l.and", II_AND}, {"l.andi", II_AND},
{"l.xor", II_XOR}, {"l.xori", II_XOR},
{"l.or",  II_OR }, {"l.ori",  II_OR},
{"l.mul", II_MUL}, {"l.muli", II_MUL},
 
{"l.sra", II_SRA}, {"l.srai", II_SRA},
{"l.srl", II_SRL}, {"l.srli", II_SRL},
{"l.sll", II_SLL}, {"l.slli", II_SLL},
 
{"l.lbz",II_LB | II_MEM}, {"l.lbs", II_LB | II_MEM | II_SIGNED},
{"l.lhz",II_LH | II_MEM}, {"l.lhs", II_LH | II_MEM | II_SIGNED},
{"l.lwz",II_LW | II_MEM}, {"l.lws", II_LW | II_MEM | II_SIGNED},
{"l.sb", II_SB | II_MEM}, {"l.sh",  II_SH | II_MEM}, {"l.sw", II_SW | II_MEM},
{"l.sfeq",  II_SFEQ }, {"l.sfeqi", II_SFEQ},
{"l.sfne",  II_SFNE }, {"l.sfnei", II_SFNE},
{"l.sflts", II_SFLT | II_SIGNED}, {"l.sfltis", II_SFLT | II_SIGNED},
{"l.sfltu", II_SFLT}, {"l.sfltiu", II_SFLT},
{"l.sfgts", II_SFGT | II_SIGNED}, {"l.sfgtis", II_SFGT | II_SIGNED},
{"l.sfgtu", II_SFGT}, {"l.sfgtiu", II_SFGT},
{"l.sfges", II_SFGE | II_SIGNED}, {"l.sfgeis", II_SFGE | II_SIGNED},
{"l.sfgeu", II_SFGE}, {"l.sfgeiu", II_SFGE},
{"l.sfles", II_SFLE | II_SIGNED}, {"l.sfleis", II_SFLE | II_SIGNED},
{"l.sfleu", II_SFLE}, {"l.sfleiu", II_SFLE},
{"l.j",     II_BF   },
{"l.bf",    II_BF   },
{"l.jal",   II_CALL },
{"l.nop",   II_NOP  }
};
 
/* Instructions from function */
cuc_insn insn[MAX_INSNS];
int num_insn;
int reloc[MAX_INSNS];
 
/* Prints out instructions */
void print_cuc_insns (char *s, int verbose)
{
  PRINTF ("****************** %s ******************\n", s);
  print_insns (0, insn, num_insn,verbose);
  PRINTF ("\n\n");
}
 
void xchg_insn (int i, int j)
{
  cuc_insn t;
  t = insn[i];
  insn[i] = insn[j];
  insn[j] = t;
}
 
/* Negates conditional instruction */
void negate_conditional (cuc_insn *ii)
{
  assert (ii->type & IT_COND);
 
  if (ii->index == II_SFEQ) change_insn_type (ii, II_SFNE);
  else if (ii->index == II_SFNE) change_insn_type (ii, II_SFEQ);
  else if (ii->index == II_SFLT) change_insn_type (ii, II_SFGE);
  else if (ii->index == II_SFGT) change_insn_type (ii, II_SFLE);
  else if (ii->index == II_SFLE) change_insn_type (ii, II_SFGT);
  else if (ii->index == II_SFGE) change_insn_type (ii, II_SFLT);
  else assert (0);
}
 
/* Remove delay slots */
void remove_dslots ()
{
  int i;
  int in_delay = 0;
  for (i = 0; i < num_insn; i++) {
    if (in_delay) insn[i].type |= IT_INDELAY;
    in_delay = 0;
    if (insn[i].type & IT_BRANCH) in_delay = 1;
    if (insn[i].type & IT_INDELAY) {
      cuc_insn *ii;
      cuc_insn *bi;
      assert (i >= 2);
      ii = &insn[i - 2];
      bi = &insn[i - 1];
      /* delay slot should not be a branch target! */
      assert ((insn[i].type & IT_BBSTART) == 0);
      assert ((bi->type & IT_INDELAY) == 0);
      insn[i].type &= ~IT_INDELAY; /* no more in delay slot */
 
      /* Get the value we need before the actual jump */
      if (bi->opt[1] & OPT_REGISTER && bi->op[1] >= 0) {
        int r = bi->op[1];
        assert (ii->index == II_NOP);
        change_insn_type (ii, II_ADD);
        ii->type = IT_COND;
        ii->dep = NULL;
        ii->op[0] = r; ii->opt[0] = OPT_REGISTER | OPT_DEST;
        ii->op[1] = r; ii->opt[1] = OPT_REGISTER;
        ii->op[2] = 0; ii->opt[2] = OPT_CONST;
        ii->opt[3] = OPT_NONE;
        bi->op[1] = i - 2; bi->opt[1] = OPT_REF;
      }
      xchg_insn (i, i - 1);
    }
  }
  assert (in_delay == 0);
}
 
/* Convert local variables (uses stack frame -- r1) to internal values */
void detect_locals ()
{
  int stack[CUC_MAX_STACK];
  int i, can_remove_stack = 1;
  int real_stack_size = 0;
 
  for (i = 0; i < CUC_MAX_STACK; i++) stack[i] = -1;
 
  for (i = 0; i < num_insn; i++) {
    /* sw off (r1),rx */
    if (insn[i].index == II_SW
      && (insn[i].opt[0] & OPT_CONST)
      && insn[i].op[1] == 1 && (insn[i].opt[1] & OPT_REGISTER)) {
 
      if (insn[i].op[0] < CUC_MAX_STACK/* && insn[i].op[1] >= 4*/) { /* Convert to normal move */
        stack[insn[i].op[0]] = i;
        insn[i].type &= IT_INDELAY | IT_BBSTART;
        change_insn_type (&insn[i], II_ADD);
        insn[i].op[0] = -1; insn[i].opt[0] = OPT_REGISTER | OPT_DEST;
        insn[i].op[1] = insn[i].op[2]; insn[i].opt[1] = insn[i].opt[2];
        insn[i].op[2] = 0; insn[i].opt[2] = OPT_CONST;
      } else can_remove_stack = 0;
    /* lw rx,off (r1) */
    } else if (insn[i].index == II_LW
      && (insn[i].opt[1] & OPT_CONST)
      && insn[i].op[2] == 1 && (insn[i].opt[2] & OPT_REGISTER)) {
 
      if (insn[i].op[1] < CUC_MAX_STACK && stack[insn[i].op[1]] >= 0) { /* Convert to normal move */
        insn[i].type &= IT_INDELAY | IT_BBSTART;
        change_insn_type (&insn[i], II_ADD);
        insn[i].op[1] = stack[insn[i].op[1]]; insn[i].opt[1] = OPT_REF;
        insn[i].op[2] = 0; insn[i].opt[2] = OPT_CONST;
      } else can_remove_stack = 0;
    /* Check for defined stack size */
    } else if (insn[i].index == II_ADD && !real_stack_size
            && (insn[i].opt[0] & OPT_REGISTER) && insn[i].op[0] == 1
            && (insn[i].opt[1] & OPT_REGISTER) && insn[i].op[1] == 1
            && (insn[i].opt[2] & OPT_CONST)) {
      real_stack_size = -insn[i].op[2];
    }
  }
  //assert (can_remove_stack); /* TODO */  
}
 
/* Disassemble one instruction from insn index and generate parameters */
const char *build_insn (unsigned long data, cuc_insn *insn)
{
  const char *name;
  char *s;
  int index = or1ksim_insn_decode (data);
  struct or32_opcode const *opcode;
  int i, argc = 0;
 
  insn->insn = data;
  insn->index = -1;
  insn->type = 0;
  name = or1ksim_insn_name (index);
  insn->index = index;
  or1ksim_disassemble_index (data, index);
  strcpy (insn->disasm, or1ksim_disassembled);
  insn->dep = NULL;
  for (i = 0; i < MAX_OPERANDS; i++) insn->opt[i] = OPT_NONE;
 
  if (index < 0) {
    fprintf (stderr, "Invalid opcode 0x%08lx!\n", data);
    exit (1);
  }
  opcode = &or1ksim_or32_opcodes[index];
 
  for (s = opcode->args; *s != '\0'; ++s) {
    switch (*s) {
    case '\0': return name;
    case 'r':
      insn->opt[argc] = OPT_REGISTER | (argc ? 0 : OPT_DEST);
      insn->op[argc++] = or1ksim_or32_extract(*++s, opcode->encoding, data);
      break;
 
    default:
      if (strchr (opcode->encoding, *s)) {
        unsigned long imm = or1ksim_or32_extract (*s, opcode->encoding, data);
        imm = or1ksim_extend_imm(imm, *s);
        insn->opt[argc] = OPT_CONST;
        insn->op[argc++] = imm;
      }
    }
  }
  return name;
}
 
/* inserts nop before branch */
void expand_branch ()
{
  int i, j, num_bra = 0, d;
  for (i = 0; i < num_insn; i++) if (insn[i].type & IT_BRANCH) num_bra++;
 
  d = num_insn + 2 * num_bra;
  assert (d < MAX_INSNS);
 
  /* Add nop before branch */
  for (i = num_insn - 1; i >= 0; i--) if (insn[i].type & IT_BRANCH) {
    insn[--d] = insn[i]; // for delay slot (later)
    if (insn[d].opt[1] & OPT_REGISTER) {
      assert (insn[d].op[1] == FLAG_REG);
      insn[d].op[1] = i; insn[d].opt[1] = OPT_REF;
    }
    insn[--d] = insn[i]; // for branch
    change_insn_type (&insn[d], II_NOP);
    insn[--d] = insn[i]; // save flag & negation of conditional, if required
    change_insn_type (&insn[d], II_CMOV);
    insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER | OPT_DEST;
    insn[d].op[1] = insn[d].type & IT_FLAG1 ? 0 : 1; insn[d].opt[1] = OPT_CONST;
    insn[d].op[2] = insn[d].type & IT_FLAG1 ? 1 : 0; insn[d].opt[2] = OPT_CONST;
    insn[d].op[3] = FLAG_REG; insn[d].opt[3] = OPT_REGISTER;
    insn[d].type = IT_COND;
    if (insn[d].type)
    reloc[i] = d;
  } else {
    insn[--d] = insn[i];
    reloc[i] = d;
  }
  num_insn += 2 * num_bra;
  for (i = 0; i < num_insn; i++)
    for (j = 0; j < MAX_OPERANDS; j++)
      if (insn[i].opt[j] & OPT_REF || insn[i].opt[j] & OPT_JUMP)
        insn[i].op[j] = reloc[insn[i].op[j]];
}
 
/* expands immediate memory instructions to two */
void expand_memory ()
{
  int i, j, num_mem = 0, d;
  for (i = 0; i < num_insn; i++) if (insn[i].type & IT_MEMORY) num_mem++;
 
  d = num_insn + num_mem;
  assert (d < MAX_INSNS);
 
  /* Split memory commands */
  for (i = num_insn - 1; i >= 0; i--) if (insn[i].type & IT_MEMORY) {
    insn[--d] = insn[i];
    insn[--d] = insn[i];
    reloc[i] = d;
    switch (insn[d].index) {
    case II_SW:
    case II_SH:
    case II_SB:
              insn[d + 1].op[1] = d; insn[d + 1].opt[1] = OPT_REF; /* sw rx,(t($-1)) */
              insn[d + 1].op[0] = insn[i].op[2]; insn[d + 1].opt[0] = insn[d + 1].opt[2];
              insn[d + 1].opt[2] = OPT_NONE;
              insn[d + 1].type &= ~IT_BBSTART;
              insn[d].op[2] = insn[d].op[0]; insn[d].opt[2] = insn[d].opt[0];
              insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER | OPT_DEST; /* add rd, ra, rb */
              insn[d].opt[3] = OPT_NONE;
              insn[d].type &= IT_INDELAY | IT_BBSTART;
              insn[d].type |= IT_MEMADD;
              change_insn_type (&insn[d], II_ADD);
              break;
    case II_LW:
    case II_LH:
    case II_LB:
              insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER | OPT_DEST; /* add rd, ra, rb */
              insn[d].type &= IT_INDELAY | IT_BBSTART;
              insn[d].type |= IT_MEMADD;
              change_insn_type (&insn[d], II_ADD);
              insn[d + 1].op[1] = d; insn[d + 1].opt[1] = OPT_REF; /* lw (t($-1)),rx */
              insn[d + 1].opt[2] = OPT_NONE;
              insn[d + 1].opt[3] = OPT_NONE;
              insn[d + 1].type &= ~IT_BBSTART;
              break;
    default:  fprintf (stderr, "%4i, %4i: %s\n", i, d, cuc_insn_name (&insn[d]));
              assert (0);
    }
  } else {
    insn[--d] = insn[i];
    reloc[i] = d;
  }
  num_insn += num_mem;
  for (i = 0; i < num_insn; i++) if (!(insn[i].type & IT_MEMORY))
    for (j = 0; j < MAX_OPERANDS; j++)
      if (insn[i].opt[j] & OPT_REF || insn[i].opt[j] & OPT_JUMP)
        insn[i].op[j] = reloc[insn[i].op[j]];
}
 
/* expands signed comparisons to three instructions */
void expand_signed ()
{
  int i, j, num_sig = 0, d;
  for (i = 0; i < num_insn; i++)
    if (insn[i].type & IT_SIGNED && !(insn[i].type & IT_MEMORY)) num_sig++;
 
  d = num_insn + num_sig * 2;
  assert (d < MAX_INSNS);
 
  /* Split signed instructions */
  for (i = num_insn - 1; i >= 0; i--)
    /* We will expand signed memory later */
    if (insn[i].type & IT_SIGNED && !(insn[i].type & IT_MEMORY)) {
      insn[--d] = insn[i];
      insn[d].op[1] = d - 2; insn[d].opt[1] = OPT_REF;
      insn[d].op[2] = d - 1; insn[d].opt[2] = OPT_REF;
 
      insn[--d] = insn[i];
      change_insn_type (&insn[d], II_ADD);
      insn[d].type = 0;
      insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER | OPT_DEST;
      insn[d].op[1] = insn[d].op[2]; insn[d].opt[1] = insn[d].opt[2];
      insn[d].op[2] = 0x80000000; insn[d].opt[2] = OPT_CONST;
      insn[d].opt[3] = OPT_NONE;
 
      insn[--d] = insn[i];
      change_insn_type (&insn[d], II_ADD);
      insn[d].type = 0;
      insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER | OPT_DEST;
      insn[d].op[1] = insn[d].op[1]; insn[d].opt[1] = insn[d].opt[1];
      insn[d].op[2] = 0x80000000; insn[d].opt[2] = OPT_CONST;
      insn[d].opt[3] = OPT_NONE;
 
      reloc[i] = d;
    } else {
      insn[--d] = insn[i];
      reloc[i] = d;
    }
  num_insn += num_sig * 2;
  for (i = 0; i < num_insn; i++) if (insn[i].type & IT_MEMORY || !(insn[i].type & IT_SIGNED)) {
    for (j = 0; j < MAX_OPERANDS; j++)
      if (insn[i].opt[j] & OPT_REF || insn[i].opt[j] & OPT_JUMP)
        insn[i].op[j] = reloc[insn[i].op[j]];
  } else insn[i].type &= ~IT_SIGNED;
}
 
/* expands calls to 7 instructions */
void expand_calls ()
{
  int i, j, num_call = 0, d;
  for (i = 0; i < num_insn; i++)
    if (insn[i].index == II_CALL) num_call++;
 
  d = num_insn + num_call * 6; /* 6 parameters */
  assert (d < MAX_INSNS);
 
  /* Split call instructions */
  for (i = num_insn - 1; i >= 0; i--)
    /* We will expand signed memory later */
    if (insn[i].index == II_CALL) {
      insn[--d] = insn[i];
      insn[d].op[0] = insn[d].op[1]; insn[d].opt[0] = OPT_CONST;
      insn[d].opt[1] = OPT_NONE;
      insn[d].type |= IT_VOLATILE;
 
      for (j = 0; j < 6; j++) {
        insn[--d] = insn[i];
        change_insn_type (&insn[d], II_ADD);
        insn[d].type = IT_VOLATILE;
        insn[d].op[0] = 3 + j; insn[d].opt[0] = OPT_REGISTER | OPT_DEST;
        insn[d].op[1] = 3 + j; insn[d].opt[1] = OPT_REGISTER;
        insn[d].op[2] = 0x80000000; insn[d].opt[2] = OPT_CONST;
        insn[d].opt[3] = OPT_NONE;
      }
 
      reloc[i] = d;
    } else {
      insn[--d] = insn[i];
      reloc[i] = d;
    }
  num_insn += num_call * 6;
  for (i = 0; i < num_insn; i++)
    for (j = 0; j < MAX_OPERANDS; j++)
      if (insn[i].opt[j] & OPT_REF || insn[i].opt[j] & OPT_JUMP)
        insn[i].op[j] = reloc[insn[i].op[j]];
}
 
/* Loads function from file into global array insn.
   Function returns nonzero if function cannot be converted. */
int cuc_load (char *in_fn)
{
  int i, j;
  FILE *fi;
  int func_return = 0;
  num_insn = 0;
 
  log ("Loading filename %s\n", in_fn);
  if ((fi = fopen (in_fn, "rt")) == NULL) {
    fprintf (stderr, "Cannot open '%s'\n", in_fn);
    exit (1);
  }
  /* Read in the function and decode the instructions */
  for (i = 0;; i++) {
    unsigned long data;
    const char *name;
 
    if (fscanf (fi, "%08lx\n", &data) != 1) break;
 
    /* build params */
    name = build_insn (data, &insn[i]);
    if (func_return) func_return++;
    //PRINTF ("%s\n", name);
 
    if (or1ksim_or32_opcodes[insn[i].index].flags & OR32_IF_DELAY) {
      int f;
      if (strcmp (name, "l.bnf") == 0) f = 1;
      else if (strcmp (name, "l.bf") == 0) f = 0;
      else if (strcmp (name, "l.j") == 0) {
        f = -1;
      } else if (strcmp (name, "l.jr") == 0 && func_return == 0) {
        func_return = 1;
        change_insn_type (&insn[i], II_NOP);
        continue;
      } else {
        cucdebug (1, "Instruction #%i: \"%s\" not supported.\n", i, name);
        log ("Instruction #%i: \"%s\" not supported.\n", i, name);
        return 1;
      }
      if (f < 0) { /* l.j */
        /* repair params */
        change_insn_type (&insn[i], II_BF);
        insn[i].op[0] = i + insn[i].op[0]; insn[i].opt[0] = OPT_JUMP;
        insn[i].op[1] = 1; insn[i].opt[1] = OPT_CONST;
        insn[i].type |= IT_BRANCH | IT_VOLATILE;
      } else {
        change_insn_type (&insn[i], II_BF);
        insn[i].op[0] = i + insn[i].op[0]; insn[i].opt[0] = OPT_JUMP;
        insn[i].op[1] = FLAG_REG; insn[i].opt[1] = OPT_REGISTER;
        insn[i].type |= IT_BRANCH | IT_VOLATILE;
        if (f) insn[i].type |= IT_FLAG1;
      }
    } else {
      insn[i].index = -1;
      for (j = 0; j < sizeof (conv) / sizeof (cuc_conv); j++)
        if (strcmp (conv[j].from, name) == 0) {
          if (conv[j].to & II_SIGNED) insn[i].type |= IT_SIGNED;
          if (conv[j].to & II_MEM) insn[i].type |= IT_MEMORY | IT_VOLATILE;
          change_insn_type (&insn[i], conv[j].to & II_MASK);
          break;
        }
      if (strcmp (name, "l.movhi") == 0) {
        insn[i].op[1] <<= 16;
        insn[i].op[2] = 0;
        insn[i].opt[2] = OPT_CONST;
      }
      if (insn[i].index == II_SFEQ || insn[i].index == II_SFNE
       || insn[i].index == II_SFLE || insn[i].index == II_SFGT
       || insn[i].index == II_SFGE || insn[i].index == II_SFLT) {
        /* repair params */
        insn[i].op[2] = insn[i].op[1]; insn[i].opt[2] = insn[i].opt[1] & ~OPT_DEST;
        insn[i].op[1] = insn[i].op[0]; insn[i].opt[1] = insn[i].opt[0] & ~OPT_DEST;
        insn[i].op[0] = FLAG_REG; insn[i].opt[0] = OPT_DEST | OPT_REGISTER;
        insn[i].opt[3] = OPT_NONE;
        insn[i].type |= IT_COND;
      }
      if ((insn[i].index < 0) ||
          ((insn[i].index == II_NOP) && (insn[i].op[0] != 0))) {
        cucdebug (1, "Instruction #%i: \"%s\" not supported (2).\n", i, name);
        log ("Instruction #%i: \"%s\" not supported (2).\n", i, name);
        return 1;
      }
    }
  }
  num_insn = i;
  fclose (fi);
  if (func_return != 2) {
    cucdebug (1, "Unsupported function structure.\n");
    log ("Unsupported function structure.\n");
    return 1;
  }
 
  log ("Number of instructions loaded = %i\n", num_insn);
  if (cuc_debug >= 3) print_cuc_insns ("INITIAL", 1);
 
  log ("Converting.\n");
  expand_branch ();
  if (cuc_debug >= 6) print_cuc_insns ("AFTER_EXP_BRANCH", 0);
 
  remove_dslots ();
  if (cuc_debug >= 6) print_cuc_insns ("NO_DELAY_SLOTS", 0);
 
  if (config.cuc.calling_convention) {
    detect_locals ();
    if (cuc_debug >= 7) print_cuc_insns ("AFTER_LOCALS", 0);
  }
  expand_memory ();
  if (cuc_debug >= 3) print_cuc_insns ("AFTER_EXP_MEM", 0);
 
  expand_signed ();
  if (cuc_debug >= 3) print_cuc_insns ("AFTER_EXP_SIG", 0);
 
  expand_calls ();
  if (cuc_debug >= 3) print_cuc_insns ("AFTER_EXP_CALLS", 0);
 
  return 0;
}

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cuc/] [load.c] - Blame information for rev 602

Line No.	Rev	Author	Line
1	19	jeremybenn	`/* load.c -- OpenRISC Custom Unit Compiler, instruction loading and converting`
2			`* Copyright (C) 2002 Marko Mlinar, markom@opencores.org`
3			`*`
4			`* This file is part of OpenRISC 1000 Architectural Simulator.`
5			`*`
6			`* This program is free software; you can redistribute it and/or modify`
7			`* it under the terms of the GNU General Public License as published by`
8			`* the Free Software Foundation; either version 2 of the License, or`
9			`* (at your option) any later version.`
10			`*`
11			`* This program is distributed in the hope that it will be useful,`
12			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`* GNU General Public License for more details.`
15			`*`
16			`* You should have received a copy of the GNU General Public License`
17			`* along with this program; if not, write to the Free Software`
18			`* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20			`#include <stdio.h>`
21			`#include <stdlib.h>`
22			`#include <stdarg.h>`
23			`#include <assert.h>`
24
25			`#include "config.h"`
26
27			`#include "port.h"`
28			`#include "arch.h"`
29			`#include "abstract.h"`
30			`#include "sim-config.h"`
31			`#include "cuc.h"`
32			`#include "opcode/or32.h"`
33			`#include "insn.h"`
34
35			`static const cuc_conv conv[] = {`
36			`{"l.add", II_ADD}, {"l.addi", II_ADD},`
37			`{"l.movhi", II_OR},`
38			`{"l.sub", II_SUB}, {"l.subi", II_SUB},`
39			`{"l.and", II_AND}, {"l.andi", II_AND},`
40			`{"l.xor", II_XOR}, {"l.xori", II_XOR},`
41			`{"l.or", II_OR }, {"l.ori", II_OR},`
42			`{"l.mul", II_MUL}, {"l.muli", II_MUL},`
43
44			`{"l.sra", II_SRA}, {"l.srai", II_SRA},`
45			`{"l.srl", II_SRL}, {"l.srli", II_SRL},`
46			`{"l.sll", II_SLL}, {"l.slli", II_SLL},`
47
48			`{"l.lbz",II_LB \| II_MEM}, {"l.lbs", II_LB \| II_MEM \| II_SIGNED},`
49			`{"l.lhz",II_LH \| II_MEM}, {"l.lhs", II_LH \| II_MEM \| II_SIGNED},`
50			`{"l.lwz",II_LW \| II_MEM}, {"l.lws", II_LW \| II_MEM \| II_SIGNED},`
51			`{"l.sb", II_SB \| II_MEM}, {"l.sh", II_SH \| II_MEM}, {"l.sw", II_SW \| II_MEM},`
52			`{"l.sfeq", II_SFEQ }, {"l.sfeqi", II_SFEQ},`
53			`{"l.sfne", II_SFNE }, {"l.sfnei", II_SFNE},`
54			`{"l.sflts", II_SFLT \| II_SIGNED}, {"l.sfltis", II_SFLT \| II_SIGNED},`
55			`{"l.sfltu", II_SFLT}, {"l.sfltiu", II_SFLT},`
56			`{"l.sfgts", II_SFGT \| II_SIGNED}, {"l.sfgtis", II_SFGT \| II_SIGNED},`
57			`{"l.sfgtu", II_SFGT}, {"l.sfgtiu", II_SFGT},`
58			`{"l.sfges", II_SFGE \| II_SIGNED}, {"l.sfgeis", II_SFGE \| II_SIGNED},`
59			`{"l.sfgeu", II_SFGE}, {"l.sfgeiu", II_SFGE},`
60			`{"l.sfles", II_SFLE \| II_SIGNED}, {"l.sfleis", II_SFLE \| II_SIGNED},`
61			`{"l.sfleu", II_SFLE}, {"l.sfleiu", II_SFLE},`
62			`{"l.j", II_BF },`
63			`{"l.bf", II_BF },`
64			`{"l.jal", II_CALL },`
65			`{"l.nop", II_NOP }`
66			`};`
67
68			`/* Instructions from function */`
69			`cuc_insn insn[MAX_INSNS];`
70			`int num_insn;`
71			`int reloc[MAX_INSNS];`
72
73			`/* Prints out instructions */`
74			`void print_cuc_insns (char *s, int verbose)`
75			`{`
76			`PRINTF ("**************** %s ****************\n", s);`
77			`print_insns (0, insn, num_insn,verbose);`
78			`PRINTF ("\n\n");`
79			`}`
80
81			`void xchg_insn (int i, int j)`
82			`{`
83			`cuc_insn t;`
84			`t = insn[i];`
85			`insn[i] = insn[j];`
86			`insn[j] = t;`
87			`}`
88
89			`/* Negates conditional instruction */`
90			`void negate_conditional (cuc_insn *ii)`
91			`{`
92			`assert (ii->type & IT_COND);`
93
94			`if (ii->index == II_SFEQ) change_insn_type (ii, II_SFNE);`
95			`else if (ii->index == II_SFNE) change_insn_type (ii, II_SFEQ);`
96			`else if (ii->index == II_SFLT) change_insn_type (ii, II_SFGE);`
97			`else if (ii->index == II_SFGT) change_insn_type (ii, II_SFLE);`
98			`else if (ii->index == II_SFLE) change_insn_type (ii, II_SFGT);`
99			`else if (ii->index == II_SFGE) change_insn_type (ii, II_SFLT);`
100			`else assert (0);`
101			`}`
102
103			`/* Remove delay slots */`
104			`void remove_dslots ()`
105			`{`
106			`int i;`
107			`int in_delay = 0;`
108			`for (i = 0; i < num_insn; i++) {`
109			`if (in_delay) insn[i].type \|= IT_INDELAY;`
110			`in_delay = 0;`
111			`if (insn[i].type & IT_BRANCH) in_delay = 1;`
112			`if (insn[i].type & IT_INDELAY) {`
113			`cuc_insn *ii;`
114			`cuc_insn *bi;`
115			`assert (i >= 2);`
116			`ii = &insn[i - 2];`
117			`bi = &insn[i - 1];`
118			`/* delay slot should not be a branch target! */`
119			`assert ((insn[i].type & IT_BBSTART) == 0);`
120			`assert ((bi->type & IT_INDELAY) == 0);`
121			`insn[i].type &= ~IT_INDELAY; /* no more in delay slot */`
122
123			`/* Get the value we need before the actual jump */`
124			`if (bi->opt[1] & OPT_REGISTER && bi->op[1] >= 0) {`
125			`int r = bi->op[1];`
126			`assert (ii->index == II_NOP);`
127			`change_insn_type (ii, II_ADD);`
128			`ii->type = IT_COND;`
129			`ii->dep = NULL;`
130			`ii->op[0] = r; ii->opt[0] = OPT_REGISTER \| OPT_DEST;`
131			`ii->op[1] = r; ii->opt[1] = OPT_REGISTER;`
132			`ii->op[2] = 0; ii->opt[2] = OPT_CONST;`
133			`ii->opt[3] = OPT_NONE;`
134			`bi->op[1] = i - 2; bi->opt[1] = OPT_REF;`
135			`}`
136			`xchg_insn (i, i - 1);`
137			`}`
138			`}`
139			`assert (in_delay == 0);`
140			`}`
141
142			`/* Convert local variables (uses stack frame -- r1) to internal values */`
143			`void detect_locals ()`
144			`{`
145			`int stack[CUC_MAX_STACK];`
146			`int i, can_remove_stack = 1;`
147			`int real_stack_size = 0;`
148
149			`for (i = 0; i < CUC_MAX_STACK; i++) stack[i] = -1;`
150
151			`for (i = 0; i < num_insn; i++) {`
152			`/* sw off (r1),rx */`
153			`if (insn[i].index == II_SW`
154			`&& (insn[i].opt[0] & OPT_CONST)`
155			`&& insn[i].op[1] == 1 && (insn[i].opt[1] & OPT_REGISTER)) {`
156
157			`if (insn[i].op[0] < CUC_MAX_STACK/* && insn[i].op[1] >= 4/) { / Convert to normal move */`
158			`stack[insn[i].op[0]] = i;`
159			`insn[i].type &= IT_INDELAY \| IT_BBSTART;`
160			`change_insn_type (&insn[i], II_ADD);`
161			`insn[i].op[0] = -1; insn[i].opt[0] = OPT_REGISTER \| OPT_DEST;`
162			`insn[i].op[1] = insn[i].op[2]; insn[i].opt[1] = insn[i].opt[2];`
163			`insn[i].op[2] = 0; insn[i].opt[2] = OPT_CONST;`
164			`} else can_remove_stack = 0;`
165			`/* lw rx,off (r1) */`
166			`} else if (insn[i].index == II_LW`
167			`&& (insn[i].opt[1] & OPT_CONST)`
168			`&& insn[i].op[2] == 1 && (insn[i].opt[2] & OPT_REGISTER)) {`
169
170			`if (insn[i].op[1] < CUC_MAX_STACK && stack[insn[i].op[1]] >= 0) { /* Convert to normal move */`
171			`insn[i].type &= IT_INDELAY \| IT_BBSTART;`
172			`change_insn_type (&insn[i], II_ADD);`
173			`insn[i].op[1] = stack[insn[i].op[1]]; insn[i].opt[1] = OPT_REF;`
174			`insn[i].op[2] = 0; insn[i].opt[2] = OPT_CONST;`
175			`} else can_remove_stack = 0;`
176			`/* Check for defined stack size */`
177			`} else if (insn[i].index == II_ADD && !real_stack_size`
178			`&& (insn[i].opt[0] & OPT_REGISTER) && insn[i].op[0] == 1`
179			`&& (insn[i].opt[1] & OPT_REGISTER) && insn[i].op[1] == 1`
180			`&& (insn[i].opt[2] & OPT_CONST)) {`
181			`real_stack_size = -insn[i].op[2];`
182			`}`
183			`}`
184			`//assert (can_remove_stack); /* TODO */`
185			`}`
186
187			`/* Disassemble one instruction from insn index and generate parameters */`
188			`const char build_insn (unsigned long data, cuc_insn insn)`
189			`{`
190			`const char *name;`
191			`char *s;`
192	230	jeremybenn	`int index = or1ksim_insn_decode (data);`
193	19	jeremybenn	`struct or32_opcode const *opcode;`
194			`int i, argc = 0;`
195
196			`insn->insn = data;`
197			`insn->index = -1;`
198			`insn->type = 0;`
199	230	jeremybenn	`name = or1ksim_insn_name (index);`
200	19	jeremybenn	`insn->index = index;`
201	230	jeremybenn	`or1ksim_disassemble_index (data, index);`
202			`strcpy (insn->disasm, or1ksim_disassembled);`
203	19	jeremybenn	`insn->dep = NULL;`
204			`for (i = 0; i < MAX_OPERANDS; i++) insn->opt[i] = OPT_NONE;`
205
206			`if (index < 0) {`
207			`fprintf (stderr, "Invalid opcode 0x%08lx!\n", data);`
208			`exit (1);`
209			`}`
210	230	jeremybenn	`opcode = &or1ksim_or32_opcodes[index];`
211	19	jeremybenn
212			`for (s = opcode->args; *s != '\0'; ++s) {`
213			`switch (*s) {`
214			`case '\0': return name;`
215			`case 'r':`
216			`insn->opt[argc] = OPT_REGISTER \| (argc ? 0 : OPT_DEST);`
217	230	jeremybenn	`insn->op[argc++] = or1ksim_or32_extract(*++s, opcode->encoding, data);`
218	19	jeremybenn	`break;`
219
220			`default:`
221			`if (strchr (opcode->encoding, *s)) {`
222	230	jeremybenn	`unsigned long imm = or1ksim_or32_extract (*s, opcode->encoding, data);`
223			`imm = or1ksim_extend_imm(imm, *s);`
224	19	jeremybenn	`insn->opt[argc] = OPT_CONST;`
225			`insn->op[argc++] = imm;`
226			`}`
227			`}`
228			`}`
229			`return name;`
230			`}`
231
232			`/* inserts nop before branch */`
233			`void expand_branch ()`
234			`{`
235			`int i, j, num_bra = 0, d;`
236			`for (i = 0; i < num_insn; i++) if (insn[i].type & IT_BRANCH) num_bra++;`
237
238			`d = num_insn + 2 * num_bra;`
239			`assert (d < MAX_INSNS);`
240
241			`/* Add nop before branch */`
242			`for (i = num_insn - 1; i >= 0; i--) if (insn[i].type & IT_BRANCH) {`
243			`insn[--d] = insn[i]; // for delay slot (later)`
244			`if (insn[d].opt[1] & OPT_REGISTER) {`
245			`assert (insn[d].op[1] == FLAG_REG);`
246			`insn[d].op[1] = i; insn[d].opt[1] = OPT_REF;`
247			`}`
248			`insn[--d] = insn[i]; // for branch`
249			`change_insn_type (&insn[d], II_NOP);`
250			`insn[--d] = insn[i]; // save flag & negation of conditional, if required`
251			`change_insn_type (&insn[d], II_CMOV);`
252			`insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER \| OPT_DEST;`
253			`insn[d].op[1] = insn[d].type & IT_FLAG1 ? 0 : 1; insn[d].opt[1] = OPT_CONST;`
254			`insn[d].op[2] = insn[d].type & IT_FLAG1 ? 1 : 0; insn[d].opt[2] = OPT_CONST;`
255			`insn[d].op[3] = FLAG_REG; insn[d].opt[3] = OPT_REGISTER;`
256			`insn[d].type = IT_COND;`
257			`if (insn[d].type)`
258			`reloc[i] = d;`
259			`} else {`
260			`insn[--d] = insn[i];`
261			`reloc[i] = d;`
262			`}`
263			`num_insn += 2 * num_bra;`
264			`for (i = 0; i < num_insn; i++)`
265			`for (j = 0; j < MAX_OPERANDS; j++)`
266			`if (insn[i].opt[j] & OPT_REF \|\| insn[i].opt[j] & OPT_JUMP)`
267			`insn[i].op[j] = reloc[insn[i].op[j]];`
268			`}`
269
270			`/* expands immediate memory instructions to two */`
271			`void expand_memory ()`
272			`{`
273			`int i, j, num_mem = 0, d;`
274			`for (i = 0; i < num_insn; i++) if (insn[i].type & IT_MEMORY) num_mem++;`
275
276			`d = num_insn + num_mem;`
277			`assert (d < MAX_INSNS);`
278
279			`/* Split memory commands */`
280			`for (i = num_insn - 1; i >= 0; i--) if (insn[i].type & IT_MEMORY) {`
281			`insn[--d] = insn[i];`
282			`insn[--d] = insn[i];`
283			`reloc[i] = d;`
284			`switch (insn[d].index) {`
285			`case II_SW:`
286			`case II_SH:`
287			`case II_SB:`
288			`insn[d + 1].op[1] = d; insn[d + 1].opt[1] = OPT_REF; /* sw rx,(t($-1)) */`
289			`insn[d + 1].op[0] = insn[i].op[2]; insn[d + 1].opt[0] = insn[d + 1].opt[2];`
290			`insn[d + 1].opt[2] = OPT_NONE;`
291			`insn[d + 1].type &= ~IT_BBSTART;`
292			`insn[d].op[2] = insn[d].op[0]; insn[d].opt[2] = insn[d].opt[0];`
293			`insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER \| OPT_DEST; /* add rd, ra, rb */`
294			`insn[d].opt[3] = OPT_NONE;`
295			`insn[d].type &= IT_INDELAY \| IT_BBSTART;`
296			`insn[d].type \|= IT_MEMADD;`
297			`change_insn_type (&insn[d], II_ADD);`
298			`break;`
299			`case II_LW:`
300			`case II_LH:`
301			`case II_LB:`
302			`insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER \| OPT_DEST; /* add rd, ra, rb */`
303			`insn[d].type &= IT_INDELAY \| IT_BBSTART;`
304			`insn[d].type \|= IT_MEMADD;`
305			`change_insn_type (&insn[d], II_ADD);`
306			`insn[d + 1].op[1] = d; insn[d + 1].opt[1] = OPT_REF; /* lw (t($-1)),rx */`
307			`insn[d + 1].opt[2] = OPT_NONE;`
308			`insn[d + 1].opt[3] = OPT_NONE;`
309			`insn[d + 1].type &= ~IT_BBSTART;`
310			`break;`
311			`default: fprintf (stderr, "%4i, %4i: %s\n", i, d, cuc_insn_name (&insn[d]));`
312			`assert (0);`
313			`}`
314			`} else {`
315			`insn[--d] = insn[i];`
316			`reloc[i] = d;`
317			`}`
318			`num_insn += num_mem;`
319			`for (i = 0; i < num_insn; i++) if (!(insn[i].type & IT_MEMORY))`
320			`for (j = 0; j < MAX_OPERANDS; j++)`
321			`if (insn[i].opt[j] & OPT_REF \|\| insn[i].opt[j] & OPT_JUMP)`
322			`insn[i].op[j] = reloc[insn[i].op[j]];`
323			`}`
324
325			`/* expands signed comparisons to three instructions */`
326			`void expand_signed ()`
327			`{`
328			`int i, j, num_sig = 0, d;`
329			`for (i = 0; i < num_insn; i++)`
330			`if (insn[i].type & IT_SIGNED && !(insn[i].type & IT_MEMORY)) num_sig++;`
331
332			`d = num_insn + num_sig * 2;`
333			`assert (d < MAX_INSNS);`
334
335			`/* Split signed instructions */`
336			`for (i = num_insn - 1; i >= 0; i--)`
337			`/* We will expand signed memory later */`
338			`if (insn[i].type & IT_SIGNED && !(insn[i].type & IT_MEMORY)) {`
339			`insn[--d] = insn[i];`
340			`insn[d].op[1] = d - 2; insn[d].opt[1] = OPT_REF;`
341			`insn[d].op[2] = d - 1; insn[d].opt[2] = OPT_REF;`
342
343			`insn[--d] = insn[i];`
344			`change_insn_type (&insn[d], II_ADD);`
345			`insn[d].type = 0;`
346			`insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER \| OPT_DEST;`
347			`insn[d].op[1] = insn[d].op[2]; insn[d].opt[1] = insn[d].opt[2];`
348			`insn[d].op[2] = 0x80000000; insn[d].opt[2] = OPT_CONST;`
349			`insn[d].opt[3] = OPT_NONE;`
350
351			`insn[--d] = insn[i];`
352			`change_insn_type (&insn[d], II_ADD);`
353			`insn[d].type = 0;`
354			`insn[d].op[0] = -1; insn[d].opt[0] = OPT_REGISTER \| OPT_DEST;`
355			`insn[d].op[1] = insn[d].op[1]; insn[d].opt[1] = insn[d].opt[1];`
356			`insn[d].op[2] = 0x80000000; insn[d].opt[2] = OPT_CONST;`
357			`insn[d].opt[3] = OPT_NONE;`
358
359			`reloc[i] = d;`
360			`} else {`
361			`insn[--d] = insn[i];`
362			`reloc[i] = d;`
363			`}`
364			`num_insn += num_sig * 2;`
365			`for (i = 0; i < num_insn; i++) if (insn[i].type & IT_MEMORY \|\| !(insn[i].type & IT_SIGNED)) {`
366			`for (j = 0; j < MAX_OPERANDS; j++)`
367			`if (insn[i].opt[j] & OPT_REF \|\| insn[i].opt[j] & OPT_JUMP)`
368			`insn[i].op[j] = reloc[insn[i].op[j]];`
369			`} else insn[i].type &= ~IT_SIGNED;`
370			`}`
371
372			`/* expands calls to 7 instructions */`
373			`void expand_calls ()`
374			`{`
375			`int i, j, num_call = 0, d;`
376			`for (i = 0; i < num_insn; i++)`
377			`if (insn[i].index == II_CALL) num_call++;`
378
379			`d = num_insn + num_call * 6; /* 6 parameters */`
380			`assert (d < MAX_INSNS);`
381
382			`/* Split call instructions */`
383			`for (i = num_insn - 1; i >= 0; i--)`
384			`/* We will expand signed memory later */`
385			`if (insn[i].index == II_CALL) {`
386			`insn[--d] = insn[i];`
387			`insn[d].op[0] = insn[d].op[1]; insn[d].opt[0] = OPT_CONST;`
388			`insn[d].opt[1] = OPT_NONE;`
389			`insn[d].type \|= IT_VOLATILE;`
390
391			`for (j = 0; j < 6; j++) {`
392			`insn[--d] = insn[i];`
393			`change_insn_type (&insn[d], II_ADD);`
394			`insn[d].type = IT_VOLATILE;`
395			`insn[d].op[0] = 3 + j; insn[d].opt[0] = OPT_REGISTER \| OPT_DEST;`
396			`insn[d].op[1] = 3 + j; insn[d].opt[1] = OPT_REGISTER;`
397			`insn[d].op[2] = 0x80000000; insn[d].opt[2] = OPT_CONST;`
398			`insn[d].opt[3] = OPT_NONE;`
399			`}`
400
401			`reloc[i] = d;`
402			`} else {`
403			`insn[--d] = insn[i];`
404			`reloc[i] = d;`
405			`}`
406			`num_insn += num_call * 6;`
407			`for (i = 0; i < num_insn; i++)`
408			`for (j = 0; j < MAX_OPERANDS; j++)`
409			`if (insn[i].opt[j] & OPT_REF \|\| insn[i].opt[j] & OPT_JUMP)`
410			`insn[i].op[j] = reloc[insn[i].op[j]];`
411			`}`
412
413			`/* Loads function from file into global array insn.`
414			`Function returns nonzero if function cannot be converted. */`
415			`int cuc_load (char *in_fn)`
416			`{`
417			`int i, j;`
418			`FILE *fi;`
419			`int func_return = 0;`
420			`num_insn = 0;`
421
422			`log ("Loading filename %s\n", in_fn);`
423			`if ((fi = fopen (in_fn, "rt")) == NULL) {`
424			`fprintf (stderr, "Cannot open '%s'\n", in_fn);`
425			`exit (1);`
426			`}`
427			`/* Read in the function and decode the instructions */`
428			`for (i = 0;; i++) {`
429			`unsigned long data;`
430			`const char *name;`
431
432			`if (fscanf (fi, "%08lx\n", &data) != 1) break;`
433
434			`/* build params */`
435			`name = build_insn (data, &insn[i]);`
436			`if (func_return) func_return++;`
437			`//PRINTF ("%s\n", name);`
438
439	230	jeremybenn	`if (or1ksim_or32_opcodes[insn[i].index].flags & OR32_IF_DELAY) {`
440	19	jeremybenn	`int f;`
441			`if (strcmp (name, "l.bnf") == 0) f = 1;`
442			`else if (strcmp (name, "l.bf") == 0) f = 0;`
443			`else if (strcmp (name, "l.j") == 0) {`
444			`f = -1;`
445			`} else if (strcmp (name, "l.jr") == 0 && func_return == 0) {`
446			`func_return = 1;`
447			`change_insn_type (&insn[i], II_NOP);`
448			`continue;`
449			`} else {`
450			`cucdebug (1, "Instruction #%i: \"%s\" not supported.\n", i, name);`
451			`log ("Instruction #%i: \"%s\" not supported.\n", i, name);`
452			`return 1;`
453			`}`
454			`if (f < 0) { /* l.j */`
455			`/* repair params */`
456			`change_insn_type (&insn[i], II_BF);`
457			`insn[i].op[0] = i + insn[i].op[0]; insn[i].opt[0] = OPT_JUMP;`
458			`insn[i].op[1] = 1; insn[i].opt[1] = OPT_CONST;`
459			`insn[i].type \|= IT_BRANCH \| IT_VOLATILE;`
460			`} else {`
461			`change_insn_type (&insn[i], II_BF);`
462			`insn[i].op[0] = i + insn[i].op[0]; insn[i].opt[0] = OPT_JUMP;`
463			`insn[i].op[1] = FLAG_REG; insn[i].opt[1] = OPT_REGISTER;`
464			`insn[i].type \|= IT_BRANCH \| IT_VOLATILE;`
465			`if (f) insn[i].type \|= IT_FLAG1;`
466			`}`
467			`} else {`
468			`insn[i].index = -1;`
469			`for (j = 0; j < sizeof (conv) / sizeof (cuc_conv); j++)`
470			`if (strcmp (conv[j].from, name) == 0) {`
471			`if (conv[j].to & II_SIGNED) insn[i].type \|= IT_SIGNED;`
472			`if (conv[j].to & II_MEM) insn[i].type \|= IT_MEMORY \| IT_VOLATILE;`
473			`change_insn_type (&insn[i], conv[j].to & II_MASK);`
474			`break;`
475			`}`
476			`if (strcmp (name, "l.movhi") == 0) {`
477			`insn[i].op[1] <<= 16;`
478			`insn[i].op[2] = 0;`
479			`insn[i].opt[2] = OPT_CONST;`
480			`}`
481			`if (insn[i].index == II_SFEQ \|\| insn[i].index == II_SFNE`
482			`\|\| insn[i].index == II_SFLE \|\| insn[i].index == II_SFGT`
483			`\|\| insn[i].index == II_SFGE \|\| insn[i].index == II_SFLT) {`
484			`/* repair params */`
485			`insn[i].op[2] = insn[i].op[1]; insn[i].opt[2] = insn[i].opt[1] & ~OPT_DEST;`
486			`insn[i].op[1] = insn[i].op[0]; insn[i].opt[1] = insn[i].opt[0] & ~OPT_DEST;`
487			`insn[i].op[0] = FLAG_REG; insn[i].opt[0] = OPT_DEST \| OPT_REGISTER;`
488			`insn[i].opt[3] = OPT_NONE;`
489			`insn[i].type \|= IT_COND;`
490			`}`
491			`if ((insn[i].index < 0) \|\|`
492			`((insn[i].index == II_NOP) && (insn[i].op[0] != 0))) {`
493			`cucdebug (1, "Instruction #%i: \"%s\" not supported (2).\n", i, name);`
494			`log ("Instruction #%i: \"%s\" not supported (2).\n", i, name);`
495			`return 1;`
496			`}`
497			`}`
498			`}`
499			`num_insn = i;`
500			`fclose (fi);`
501			`if (func_return != 2) {`
502			`cucdebug (1, "Unsupported function structure.\n");`
503			`log ("Unsupported function structure.\n");`
504			`return 1;`
505			`}`
506
507			`log ("Number of instructions loaded = %i\n", num_insn);`
508			`if (cuc_debug >= 3) print_cuc_insns ("INITIAL", 1);`
509
510			`log ("Converting.\n");`
511			`expand_branch ();`
512			`if (cuc_debug >= 6) print_cuc_insns ("AFTER_EXP_BRANCH", 0);`
513
514			`remove_dslots ();`
515			`if (cuc_debug >= 6) print_cuc_insns ("NO_DELAY_SLOTS", 0);`
516
517			`if (config.cuc.calling_convention) {`
518			`detect_locals ();`
519			`if (cuc_debug >= 7) print_cuc_insns ("AFTER_LOCALS", 0);`
520			`}`
521			`expand_memory ();`
522			`if (cuc_debug >= 3) print_cuc_insns ("AFTER_EXP_MEM", 0);`
523
524			`expand_signed ();`
525			`if (cuc_debug >= 3) print_cuc_insns ("AFTER_EXP_SIG", 0);`
526
527			`expand_calls ();`
528			`if (cuc_debug >= 3) print_cuc_insns ("AFTER_EXP_CALLS", 0);`
529
530			`return 0;`
531			`}`