OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cuc/] [verilog.c] - Blame information for rev 609

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jeremybenn
/* verilog.c -- OpenRISC Custom Unit Compiler, verilog generator
2
 
3
   Copyright (C) 2002 Marko Mlinar, markom@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
 
27
/* Autoconf and/or portability configuration */
28
#include "config.h"
29
#include "port.h"
30
 
31
/* System includes */
32
#include <stdio.h>
33
#include <stdlib.h>
34
#include <stdarg.h>
35
#include <assert.h>
36
 
37
/* Package includes */
38
#include "arch.h"
39
#include "abstract.h"
40
#include "cuc.h"
41
#include "insn.h"
42
#include "profiler.h"
43
#include "sim-config.h"
44
#include "misc.h"
45
 
46
/* Shortcut */
47
#define GEN(x...) fprintf (fo, x)
48
 
49
/* Find index of load/store/call */
50
static int
51
find_lsc_index (cuc_func * f, int ref)
52
{
53
  int c = 0;
54
  int i;
55
  int load;
56
 
57
  if (f->INSN (ref).index == II_CALL)
58
    {
59
      for (i = 0; i < f->nmsched; i++)
60
        {
61
          if (f->msched[i] == ref)
62
            break;
63
          if (f->mtype[i] & MT_CALL)
64
            c++;
65
        }
66
    }
67
  else
68
    {
69
      load = II_IS_LOAD (f->INSN (ref).index);
70
      for (i = 0; i < f->nmsched; i++)
71
        {
72
          if (f->msched[i] == ref)
73
            break;
74
          if ((load && (f->mtype[i] & MT_LOAD))
75
              || (!load && (f->mtype[i] & MT_STORE)))
76
            c++;
77
        }
78
    }
79
  return c;
80
}
81
 
82
/* Print out dependencies as verilog expression */
83
static void
84
print_deps (FILE * fo, cuc_func * f, int b, dep_list * t, int registered)
85
{
86
  if (t)
87
    {
88
      int first = 0;
89
      while (t)
90
        {
91
          if (f->INSN (t->ref).type & IT_MEMORY)
92
            {
93
              GEN ("%s%c_end[%i]", first ? " && " : "",
94
                   II_IS_LOAD (f->INSN (t->ref).index) ? 'l' : 's',
95
                   find_lsc_index (f, t->ref));
96
            }
97
          else if (f->INSN (t->ref).index == II_CALL)
98
            {
99
              GEN ("%sf_end[%i]", first ? " && " : "",
100
                   find_lsc_index (f, t->ref));
101
            }
102
          else
103
            {
104
              PRINTF ("print_deps: err %lx\n", t->ref);
105
              assert (0);
106
            }
107
          first = 1;
108
          t = t->next;
109
        }
110
    }
111
  else
112
    {
113
      if (registered)
114
        GEN ("bb_start_r[%i]", b);
115
      else
116
        GEN ("bb_start[%i]", b);
117
    }
118
}
119
 
120
static char *
121
print_op_v (cuc_func * f, char *s, int ref, int j)
122
{
123
  unsigned long op = f->INSN (ref).op[j];
124
  unsigned long opt = f->INSN (ref).opt[j];
125
  switch (opt & ~OPT_DEST)
126
    {
127
    case OPT_NONE:
128
      assert (0);
129
      break;
130
    case OPT_CONST:
131
      if (f->INSN (ref).type & IT_COND && (f->INSN (ref).index == II_CMOV
132
                                           || f->INSN (ref).index == II_ADD))
133
        {
134
          assert (op == 0 || op == 1);
135
          sprintf (s, "1'b%lx", op);
136
        }
137
      else
138
        sprintf (s, "32'h%lx", op);
139
      break;
140
    case OPT_REGISTER:
141
      if (opt & OPT_DEST)
142
        sprintf (s, "t%x_%x", REF_BB (ref), REF_I (ref));
143
      else
144
        sprintf (s, "r%li_%c", op, opt & OPT_DEST ? 'o' : 'i');
145
      break;
146
#if 0
147
    case OPT_FREG:
148
      assert (opt & OPT_DEST);
149
      sprintf (s, "fr%i_o", op);
150
      break;
151
#endif
152
    case OPT_REF:
153
      sprintf (s, "t%lx_%lx", REF_BB (op), REF_I (op));
154
      break;
155
    }
156
  return s;
157
}
158
 
159
/* Prints out specified instruction */
160
static void
161
print_insn_v (FILE * fo, cuc_func * f, int b, int i)
162
{
163
  cuc_insn *ii = &f->bb[b].insn[i];
164
  char *s = known[ii->index].rtl;
165
  char tmp[200] = "";
166
 
167
  assert (s);
168
  while (*s)
169
    {
170
      if (*s <= MAX_OPERANDS)
171
        {
172
          char t[30];
173
          sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF (b, i), *s - 1));
174
        }
175
      else if (*s == '\b')
176
        sprintf (tmp, "%s%i", tmp, b);
177
      else
178
        sprintf (tmp, "%s%c", tmp, *s);
179
      s++;
180
    }
181
  GEN ("%-40s /* %s */\n", tmp, ii->disasm);
182
  if (ii->type & IT_MEMORY)
183
    {
184
      int nls = find_lsc_index (f, REF (b, i));
185
      if (II_IS_LOAD (ii->index))
186
        {
187
          int nm;
188
          for (nm = 0; nm < f->nmsched; nm++)
189
            if (f->msched[nm] == REF (b, i))
190
              break;
191
          assert (nm < f->nmsched);
192
 
193
          GEN ("  if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
194
          switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED))
195
            {
196
            case 1:
197
              GEN ("l_dat_i & 32'hff;\n");
198
              break;
199
            case 2:
200
              GEN ("l_dat_i & 32'hffff;\n");
201
              break;
202
            case 4 | MT_SIGNED:
203
            case 4:
204
              GEN ("l_dat_i;\n");
205
              break;
206
            case 1 | MT_SIGNED:
207
              GEN ("{24{l_dat_i[7]}, l_dat_i[7:0]};\n");
208
              break;
209
            case 2 | MT_SIGNED:
210
              GEN ("{16{l_dat_i[15]}, l_dat_i[15:0]};\n");
211
              break;
212
            default:
213
              assert (0);
214
            }
215
        }
216
    }
217
  else if (ii->index == II_LRBB)
218
    {
219
      GEN ("  if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
220
      assert (f->bb[b].prev[0] >= 0);
221
      if (f->bb[b].prev[0] == BBID_START)
222
        GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp start_i;\n", b, b, i);
223
      else
224
        GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i,
225
             f->bb[b].prev[0]);
226
    }
227
  else if (ii->index == II_REG)
228
    {
229
      assert (ii->opt[1] == OPT_REF);
230
      GEN ("  if (");
231
      if (f->bb[b].mdep)
232
        print_deps (fo, f, b, f->bb[b].mdep, 0);
233
      else
234
        GEN ("bb_stb[%i]", b);
235
      GEN (") t%x_%x <= #Tp t%lx_%lx;\n", b, i,
236
           REF_BB (ii->op[1]), REF_I (ii->op[1]));
237
    }
238
}
239
 
240
/* Outputs binary number */
241
/*
242
static char *bin_str (unsigned long x, int len)
243
{
244
  static char bx[33];
245
  char *s = bx;
246
  while (len > 0) *s++ = '0' + ((x >> --len) & 1);
247
  *s = '\0';
248
  return bx;
249
}
250
*/
251
 
252
/* Returns index of branch instruction inside a block b */
253
static int
254
branch_index (cuc_bb * bb)
255
{
256
  int i;
257
  for (i = bb->ninsn - 1; i >= 0; i--)
258
    if (bb->insn[i].type & IT_BRANCH)
259
      return i;
260
  return -1;
261
}
262
 
263
static void
264
print_turn_off_dep (FILE * fo, cuc_func * f, dep_list * dep)
265
{
266
  while (dep)
267
    {
268
      assert (f->INSN (dep->ref).type & IT_MEMORY
269
              || f->INSN (dep->ref).index == II_CALL);
270
      GEN ("      %c_stb[%i] <= #Tp 1'b0;\n",
271
           f->INSN (dep->ref).index ==
272
           II_CALL ? 'f' : II_IS_LOAD (f->INSN (dep->ref).index) ? 'l' : 's',
273
           find_lsc_index (f, dep->ref));
274
      dep = dep->next;
275
    }
276
}
277
 
278
static int
279
func_index (cuc_func * f, int ref)
280
{
281
  int i;
282
  unsigned long addr;
283
  assert (f->INSN (ref).index == II_CALL && f->INSN (ref).opt[0] & OPT_CONST);
284
  addr = f->INSN (ref).op[0];
285
  for (i = 0; i < f->nfdeps; i++)
286
    if (f->fdeps[i]->start_addr == addr)
287
      return i;
288
 
289
  assert (0);
290
  return -1;
291
}
292
 
293
/* Generates verilog file out of insn dataflow */
294
void
295
output_verilog (cuc_func * f, char *filename, char *funcname)
296
{
297
  FILE *fo;
298
  int b, i, j;
299
  int ci = 0, co = 0;
300
  int nloads = 0, nstores = 0, ncalls = 0;
301
  char tmp[256];
302
  sprintf (tmp, "%s.v", filename);
303
 
304
  log ("Generating verilog file \"%s\"\n", tmp);
305
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
306
  if ((fo = fopen (tmp, "wt+")) == NULL)
307
    {
308
      fprintf (stderr, "Cannot open '%s'\n", tmp);
309
      exit (1);
310
    }
311
 
312
  /* output header */
313
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
314
  GEN ("   (C) 2002 Opencores\n");
315
  GEN ("   function   \"%s\"\n", funcname);
316
  GEN ("   at         %08lx - %08lx\n", f->start_addr, f->end_addr);
317
  GEN ("   num BBs    %i */\n\n", f->num_bb);
318
 
319
  GEN ("`include \"timescale.v\"\n\n");
320
  GEN ("module %s (clk, rst,\n", filename);
321
  GEN ("              l_adr_o, l_dat_i, l_req_o,\n");
322
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i,\n");
323
  GEN ("              s_adr_o, s_dat_o, s_req_o,\n");
324
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i,\n");
325
 
326
  GEN ("/* inputs */  ");
327
  for (i = 0; i < MAX_REGS; i++)
328
    if (f->used_regs[i])
329
      {
330
        GEN ("r%i_i, ", i);
331
        ci++;
332
      }
333
  if (!ci)
334
    GEN ("/* NONE */");
335
 
336
  GEN ("\n/* outputs */ ");
337
  for (i = 0; i < MAX_REGS; i++)
338
    if (f->lur[i] >= 0 && !f->saved_regs[i])
339
      {
340
        GEN ("r%i_o, ", i);
341
        co++;
342
      }
343
 
344
  if (!co)
345
    GEN ("/* NONE */");
346
  if (f->nfdeps)
347
    {
348
      GEN ("\n/* f. calls */, fstart_o, %sfend_i, fr11_i, ",
349
           log2_int (f->nfdeps) > 0 ? "fid_o, " : "");
350
      for (i = 0; i < 6; i++)
351
        GEN ("fr%i_o, ", i + 3);
352
    }
353
  GEN ("\n              start_i, end_o, busy_o);\n\n");
354
 
355
  GEN ("parameter Tp = 1;\n\n");
356
 
357
  GEN ("input         clk, rst;\n");
358
  GEN ("input         start_i;\t/* Module starts when set to 1 */ \n");
359
  GEN
360
    ("output        end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
361
  GEN
362
    ("output        busy_o;\t/* Set when module should not be interrupted */\n");
363
  GEN ("\n/* Bus signals */\n");
364
  GEN ("output        l_req_o, s_req_o;\n");
365
  GEN ("input         l_rdy_i, s_rdy_i;\n");
366
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
367
  GEN ("output [31:0] l_adr_o, s_adr_o;\n");
368
  GEN ("output        l_linbrst_o, s_linbrst_o;\n");
369
  GEN ("input  [31:0] l_dat_i;\n");
370
  GEN ("output [31:0] s_dat_o;\n\n");
371
 
372
  GEN ("reg           l_req_o, s_req_o;\n");
373
  GEN ("reg    [31:0] l_adr_o, s_adr_o;\n");
374
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
375
  GEN ("reg    [31:0] s_dat_o;\n");
376
  GEN ("reg           l_linbrst_o, s_linbrst_o;\n");
377
 
378
  if (ci || co)
379
    GEN ("\n/* module ports */\n");
380
  if (ci)
381
    {
382
      int first = 1;
383
      GEN ("input  [31:0]");
384
      for (i = 0; i < MAX_REGS; i++)
385
        if (f->used_regs[i])
386
          {
387
            GEN ("%sr%i_i", first ? " " : ", ", i);
388
            first = 0;
389
          }
390
      GEN (";\n");
391
    }
392
 
393
  if (co)
394
    {
395
      int first = 1;
396
      GEN ("output [31:0]");
397
      for (i = 0; i < MAX_REGS; i++)
398
        if (f->lur[i] >= 0 && !f->saved_regs[i])
399
          {
400
            GEN ("%sr%i_o", first ? " " : ", ", i);
401
            first = 0;
402
          }
403
      GEN (";\n");
404
    }
405
 
406
  if (f->nfdeps)
407
    {
408
      GEN ("\n/* Function calls */\n");
409
      GEN ("output [31:0] fr3_o");
410
      for (i = 1; i < 6; i++)
411
        GEN (", fr%i_o", i + 3);
412
      GEN (";\n");
413
      GEN ("input  [31:0] fr11_i;\n");
414
      if (log2_int (f->nfdeps) > 0)
415
        GEN ("output [%i:0] fid_o;\n", log2_int (f->nfdeps));
416
      GEN ("output        fstart_o;\n");
417
      GEN ("input         fend_i;\n");
418
    }
419
 
420
  /* Count loads & stores */
421
  for (i = 0; i < f->nmsched; i++)
422
    if (f->mtype[i] & MT_STORE)
423
      nstores++;
424
    else if (f->mtype[i] & MT_LOAD)
425
      nloads++;
426
    else if (f->mtype[i] & MT_CALL)
427
      ncalls++;
428
 
429
  /* Output internal registers for loads */
430
  if (nloads)
431
    {
432
      int first = 1;
433
      int num = 0;
434
      GEN ("\n/* internal registers for loads */\n");
435
      for (i = 0; i < f->nmsched; i++)
436
        if (f->mtype[i] & MT_LOAD)
437
          {
438
            GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ",
439
                 REF_BB (f->msched[i]), REF_I (f->msched[i]));
440
 
441
            if (num >= 8)
442
              {
443
                GEN (";\n");
444
                first = 1;
445
                num = 0;
446
              }
447
            else
448
              {
449
                first = 0;
450
                num++;
451
              }
452
          }
453
      if (!first)
454
        GEN (";\n");
455
    }
456
 
457
  /* Internal register for function return value */
458
  if (f->nfdeps)
459
    {
460
      GEN ("\n/* Internal register for function return value */\n");
461
      GEN ("reg     [31:0] fr11_r;\n");
462
    }
463
 
464
  GEN ("\n/* 'zero or one' hot state machines */\n");
465
  if (nloads)
466
    GEN ("reg     [%i:0] l_stb; /* loads */\n", nloads - 1);
467
  if (nstores)
468
    GEN ("reg     [%i:0] s_stb; /* stores */\n", nstores - 1);
469
  GEN ("reg     [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
470
 
471
  {
472
    int first = 2;
473
    int num = 0;
474
    for (b = 0; b < f->num_bb; b++)
475
      for (i = 0; i < f->bb[b].ninsn; i++)
476
        if (f->bb[b].insn[i].type & IT_COND
477
            && f->bb[b].insn[i].index != II_REG
478
            && f->bb[b].insn[i].index != II_LRBB)
479
          {
480
            if (first == 2)
481
              GEN ("\n/* basic block condition wires */\n");
482
            GEN ("%st%x_%x", first ? "wire          " : ", ", b, i);
483
            if (num >= 8)
484
              {
485
                GEN (";\n");
486
                first = 1;
487
                num = 0;
488
              }
489
            else
490
              {
491
                first = 0;
492
                num++;
493
              }
494
          }
495
    if (!first)
496
      GEN (";\n");
497
 
498
    GEN ("\n/* forward declaration of normal wires */\n");
499
    num = 0;
500
    first = 1;
501
    for (b = 0; b < f->num_bb; b++)
502
      for (i = 0; i < f->bb[b].ninsn; i++)
503
        if (!(f->bb[b].insn[i].type & (IT_COND | IT_BRANCH))
504
            && f->bb[b].insn[i].index != II_REG
505
            && f->bb[b].insn[i].index != II_LRBB)
506
          {
507
            /* Exclude loads */
508
            if (f->bb[b].insn[i].type & IT_MEMORY
509
                && II_IS_LOAD (f->bb[b].insn[i].index))
510
              continue;
511
            GEN ("%st%x_%x", first ? "wire   [31:0] " : ", ", b, i);
512
            if (num >= 8)
513
              {
514
                GEN (";\n");
515
                first = 1;
516
                num = 0;
517
              }
518
            else
519
              {
520
                first = 0;
521
                num++;
522
              }
523
          }
524
    if (!first)
525
      GEN (";\n");
526
 
527
    GEN ("\n/* forward declaration registers */\n");
528
    num = 0;
529
    first = 1;
530
    for (b = 0; b < f->num_bb; b++)
531
      for (i = 0; i < f->bb[b].ninsn; i++)
532
        if (f->bb[b].insn[i].index == II_REG
533
            && f->bb[b].insn[i].index != II_LRBB)
534
          {
535
            GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ", b, i);
536
            if (num >= 8)
537
              {
538
                GEN (";\n");
539
                first = 1;
540
                num = 0;
541
              }
542
            else
543
              {
544
                first = 0;
545
                num++;
546
              }
547
          }
548
    if (!first)
549
      GEN (";\n");
550
 
551
    num = 0;
552
    first = 1;
553
    for (b = 0; b < f->num_bb; b++)
554
      for (i = 0; i < f->bb[b].ninsn; i++)
555
        if (f->bb[b].insn[i].index != II_REG
556
            && f->bb[b].insn[i].index == II_LRBB)
557
          {
558
            GEN ("%st%x_%x", first ? "reg           " : ", ", b, i);
559
            if (num >= 8)
560
              {
561
                GEN (";\n");
562
                first = 1;
563
                num = 0;
564
              }
565
            else
566
              {
567
                first = 0;
568
                num++;
569
              }
570
          }
571
    if (!first)
572
      GEN (";\n");
573
  }
574
 
575
  if (nloads || nstores)
576
    GEN ("\n/* dependencies */\n");
577
  if (nloads)
578
    GEN ("wire    [%i:0] l_end = l_stb & {%i{l_rdy_i}};\n",
579
         nloads - 1, nloads);
580
  if (nstores)
581
    GEN ("wire    [%i:0] s_end = s_stb & {%i{s_rdy_i}};\n",
582
         nstores - 1, nstores);
583
  if (ncalls)
584
    GEN ("wire    [%i:0] f_end = f_stb & {%i{fend_i}};\n",
585
         ncalls - 1, ncalls);
586
 
587
  GEN ("\n/* last dependency */\n");
588
  GEN ("wire   end_o = ");
589
  for (b = 0; b < f->num_bb; b++)
590
    {
591
      for (i = 0; i < 2; i++)
592
        if (f->bb[b].next[i] == BBID_END)
593
          {
594
            GEN ("bb_stb[%i]", b);
595
            if (f->bb[b].mdep)
596
              {
597
                GEN (" && ");
598
                print_deps (fo, f, b, f->bb[b].mdep, 0);
599
              }
600
            /* Is branch to BBID_END conditional? */
601
            if (f->bb[b].next[1 - i] >= 0)
602
              {
603
                int bidx = branch_index (&f->bb[b]);
604
                char t[30];
605
                print_op_v (f, t, REF (b, bidx), 1);
606
                GEN (" && %s%s", i ? "" : "!", t);
607
              }
608
          }
609
    }
610
  GEN (";\n");
611
  GEN ("wire   busy_o = |bb_stb;\n");
612
 
613
 
614
  GEN ("\n/* Basic block triggers */\n");
615
  GEN ("wire   [%2i:0] bb_start = {\n", f->num_bb - 1);
616
  for (b = f->num_bb - 1; b >= 0; b--)
617
    {
618
      GEN ("    /* bb_start[%2i] */ ", b);
619
      for (i = 0; i < 2; i++)
620
        if (f->bb[b].prev[i] >= 0 && f->bb[b].prev[i] != BBID_START)
621
          {
622
            cuc_bb *prev = &f->bb[f->bb[b].prev[i]];
623
            int t;
624
            if (i)
625
              GEN ("\n                    || ");
626
            if (prev->mdep)
627
              {
628
                print_deps (fo, f, f->bb[b].prev[i], prev->mdep, 0);
629
                GEN (" && ");
630
              }
631
            GEN ("bb_stb[%i]", f->bb[b].prev[i]);
632
            if (prev->next[0] >= 0 && prev->next[0] != BBID_END
633
                && prev->next[1] >= 0 && prev->next[1] != BBID_END)
634
              {
635
                int bi =
636
                  REF (f->bb[b].prev[i],
637
                       branch_index (&f->bb[f->bb[b].prev[i]]));
638
                int ci;
639
                assert (bi >= 0);
640
                ci = f->INSN (bi).op[1];
641
                t = prev->next[0] == b;
642
                GEN (" && ");
643
                if (f->INSN (bi).opt[1] & OPT_REF)
644
                  {
645
                    GEN ("%st%x_%x", t ? "" : "!", REF_BB (ci), REF_I (ci));
646
                  }
647
                else
648
                  {
649
                    cucdebug (5, "%x!%x!%x\n", bi, ci, f->INSN (bi).opt[1]);
650
                    assert (f->INSN (bi).opt[1] & OPT_CONST);
651
                    GEN ("%s%i", t ? "" : "!", ci);
652
                  }
653
              }
654
          }
655
        else
656
          break;
657
      if (!i)
658
        GEN ("start_i");
659
      if (b == 0)
660
        GEN ("};\n");
661
      else
662
        GEN (",\n");
663
    }
664
 
665
  GEN ("\n/* Register the bb_start */\n");
666
  GEN ("reg   [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
667
  GEN ("always @(posedge rst or posedge clk)\n");
668
  GEN ("begin\n");
669
  GEN ("  if (rst) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
670
  GEN ("  else if (end_o) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
671
  GEN ("  else bb_start_r <= #Tp bb_start;\n");
672
  GEN ("end\n");
673
 
674
  GEN ("\n/* Logic */\n");
675
  /* output body */
676
  for (b = 0; b < f->num_bb; b++)
677
    {
678
      GEN ("\t\t/* BB%i */\n", b);
679
      for (i = 0; i < f->bb[b].ninsn; i++)
680
        print_insn_v (fo, f, b, i);
681
      GEN ("\n");
682
    }
683
 
684
  if (co)
685
    {
686
      GEN ("\n/* Outputs */\n");
687
      for (i = 0; i < MAX_REGS; i++)
688
        if (f->lur[i] >= 0 && !f->saved_regs[i])
689
          GEN ("assign r%i_o = t%x_%x;\n", i, REF_BB (f->lur[i]),
690
               REF_I (f->lur[i]));
691
    }
692
 
693
  if (nstores)
694
    {
695
      int cur_store;
696
      GEN ("\n/* Memory stores */\n");
697
      GEN ("always @(s_stb");
698
      for (i = 0; i < f->nmsched; i++)
699
        if (f->mtype[i] & MT_STORE)
700
          {
701
            char t[30];
702
            unsigned long opt = f->INSN (f->msched[i]).opt[0];
703
            if ((opt & ~OPT_DEST) != OPT_CONST)
704
              {
705
                GEN (" or %s", print_op_v (f, t, f->msched[i], 0));
706
              }
707
          }
708
 
709
      cur_store = 0;
710
      GEN (")\nbegin\n");
711
      for (i = 0; i < f->nmsched; i++)
712
        if (f->mtype[i] & MT_STORE)
713
          {
714
            char t[30];
715
            GEN ("  %sif (s_stb[%i]) s_dat_o = %s;\n",
716
                 cur_store == 0 ? "" : "else ", cur_store, print_op_v (f, t,
717
                                                                       f->
718
                                                                       msched
719
                                                                       [i],
720
                                                                       0));
721
            cur_store++;
722
            //PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
723
          }
724
      GEN ("  else s_dat_o = 32'hx;\n");
725
      GEN ("end\n");
726
    }
727
 
728
  /* Generate load and store state machine */
729
#if 0
730
  GEN ("\n/* Load&store state machine */\n");
731
  GEN ("always @(posedge clk or posedge rst)\n");
732
  GEN ("  if (rst) begin\n");
733
  if (nloads)
734
    GEN ("    l_stb <= #Tp %i'h0;\n", nloads);
735
  if (nstores)
736
    GEN ("    s_stb <= #Tp %i'h0;\n", nstores);
737
  GEN ("  end else begin\n");
738
  for (i = 0; i < f->nmsched; i++)
739
    if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE)
740
      {
741
        int cur = 0;
742
        dep_list *dep = f->INSN (f->msched[i]).dep;
743
        assert (f->INSN (f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
744
        GEN ("    if (");
745
        print_deps (fo, f, REF_BB (f->msched[i]), f->INSN (f->msched[i]).dep,
746
                    1);
747
        GEN (") begin\n");
748
        print_turn_off_dep (fo, f, dep);
749
        GEN ("      %c_stb[%i] <= #Tp 1'b1;\n",
750
             f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
751
        GEN ("    end\n");
752
      }
753
  GEN ("    if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
754
  GEN ("  end\n");
755
#endif
756
 
757
  /* Generate state generator machine */
758
  for (j = 0; j < 2; j++)
759
    {
760 96 jeremybenn
      char c = 0;                /* Mark Jarvin patch to initialize values. */
761
      char *s = NULL;
762 19 jeremybenn
 
763
      switch (j)
764
        {
765
        case 0:
766
          c = 'l';
767
          s = "Load";
768
          break;
769
        case 1:
770
          c = 's';
771
          s = "Store";
772
          break;
773
        case 2:
774
          c = 'c';
775
          s = "Calls";
776
          break;
777
        }
778
      if ((j == 0 && nloads) || (j == 1 && nstores) || (j == 2 && ncalls))
779
        {
780
          int cur = 0;
781
          char t[30];
782
 
783
          GEN ("\n/* %s state generator machine */\n", s);
784
          GEN ("always @(");
785
          for (i = 0; i < f->nmsched; i++)
786
            {
787
              print_op_v (f, t, f->msched[i], 1);
788
              GEN ("%s or ", t);
789
            }
790
          GEN ("bb_start_r");
791
          if (nloads)
792
            GEN (" or l_end");
793
          if (nstores)
794
            GEN (" or s_end");
795
          GEN (")\n");
796
          GEN ("begin\n  ");
797
          cucdebug (1, "%s\n", s);
798
          for (i = 0; i < f->nmsched; i++)
799
            if ((j == 0 && f->mtype[i] & MT_LOAD)
800
                || (j == 1 && f->mtype[i] & MT_STORE)
801
                || (j == 2 && f->mtype[i] & MT_CALL))
802
              {
803
                cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i],
804
                          f->mtype[i]);
805
                assert (f->INSN (f->msched[i]).
806
                        opt[1] & (OPT_REF | OPT_REGISTER));
807
                GEN ("if (");
808
                print_deps (fo, f, REF_BB (f->msched[i]),
809
                            f->INSN (f->msched[i]).dep, 1);
810
                GEN (") begin\n");
811
                GEN ("    %c_req_o = 1'b1;\n", c);
812
                GEN ("    %c_sel_o[3:0] = 4'b", c);
813
                switch (f->mtype[i] & MT_WIDTH)
814
                  {
815
                  case 1:
816
                    GEN ("0001 << (%s & 32'h3);\n",
817
                         print_op_v (f, t, f->msched[i], 1));
818
                    break;
819
                  case 2:
820
                    GEN ("0011 << ((%s & 32'h1) << 1);\n",
821
                         print_op_v (f, t, f->msched[i], 1));
822
                    break;
823
                  case 4:
824
                    GEN ("1111;\n");
825
                    break;
826
                  default:
827
                    assert (0);
828
                  }
829
                GEN ("    %c_linbrst_o = 1'b%i;\n", c,
830
                     (f->mtype[i] & MT_BURST)
831
                     && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
832
                GEN ("    %c_adr_o = t%lx_%lx & ~32'h3;\n", c,
833
                     REF_BB (f->INSN (f->msched[i]).op[1]),
834
                     REF_I (f->INSN (f->msched[i]).op[1]));
835
                GEN ("  end else ");
836
              }
837
          GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
838
          GEN ("    %c_req_o = 1'b0;\n", c);
839
          GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
840
          GEN ("    %c_linbrst_o = 1'b0;\n", c);
841
          GEN ("    %c_adr_o = 32'hx;\n", c);
842
          GEN ("  end else begin\n");
843
          GEN ("    %c_req_o = 1'b0;\n", c);
844
          GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
845
          GEN ("    %c_linbrst_o = 1'b0;\n", c);
846
          GEN ("    %c_adr_o = 32'hx;\n", c);
847
          GEN ("  end\n");
848
          GEN ("end\n");
849
        }
850
    }
851
 
852
  if (ncalls)
853
    {
854
      int cur_call = 0;
855
      GEN ("\n/* Function calls state machine */\n");
856
      GEN ("always @(posedge clk or posedge rst)\n");
857
      GEN ("begin\n");
858
      GEN ("  if (rst) begin\n");
859
      GEN ("    f_stb <= #Tp %i'h0;\n", nstores);
860
      for (i = 0; i < 6; i++)
861
        GEN ("    fr%i_o <= #Tp 32'h0;\n", i + 3);
862
      if (log2_int (ncalls))
863
        GEN ("    fid_o <= #Tp %i'h0;\n", log2_int (f->nfdeps));
864
      GEN ("    fstart_o <= #Tp 1'b0;\n");
865
      //GEN ("    f11_r <= #Tp 32'h0;\n");
866
      GEN ("  end else begin\n");
867
      cucdebug (1, "calls \n");
868
      for (i = 0; i < f->nmsched; i++)
869
        if (f->mtype[i] & MT_CALL)
870
          {
871
            dep_list *dep = f->INSN (f->msched[i]).dep;
872
            cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i],
873
                      f->mtype[i]);
874
            assert (f->INSN (f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
875
            GEN ("    if (");
876
            print_deps (fo, f, REF_BB (f->msched[i]),
877
                        f->INSN (f->msched[i]).dep, 1);
878
            GEN (") begin\n");
879
            print_turn_off_dep (fo, f, dep);
880
            GEN ("      f_stb[%i] <= #Tp 1'b1;\n", cur_call++);
881
            GEN ("      fstart_o <= #Tp 1'b1;\n");
882
            if (log2_int (f->nfdeps))
883
              GEN ("      fid_o <= #Tp %i'h%x;\n", log2_int (f->nfdeps),
884
                   func_index (f, f->msched[i]));
885
 
886
            for (j = 0; j < 6; j++)
887
              GEN ("      fr%i_o <= #Tp t%x_%x;\n", j + 3,
888
                   REF_BB (f->msched[i]), REF_I (f->msched[i]) - 6 + i);
889
            GEN ("    end\n");
890
          }
891
      GEN ("    if (f_end[%i]) begin\n", ncalls - 1);
892
      GEN ("      f_stb <= #Tp %i'h0;\n", ncalls);
893
      GEN ("      f_start_o <= #Tp 1'b0;\n");
894
      GEN ("    end\n");
895
      GEN ("  end\n");
896
      GEN ("end\n");
897
    }
898
 
899
  GEN ("\n/* Basic blocks state machine */\n");
900
  GEN ("always @(posedge clk or posedge rst)\n");
901
  GEN ("begin\n");
902
  GEN ("  if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
903
  GEN ("  else if (end_o) begin\n");
904
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
905
  for (i = 0; i < f->num_bb; i++)
906
    {
907
      GEN ("  end else if (bb_start[%i]) begin\n", i);
908
      GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
909
    }
910
  GEN ("  end else if (end_o) begin\n");
911
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
912
  GEN ("  end\n");
913
  GEN ("end\n");
914
 
915
  /* output footer */
916
  GEN ("\nendmodule\n");
917
 
918
  fclose (fo);
919
}
920
 
921
void
922
generate_main (int nfuncs, cuc_func ** f, char *filename)
923
{
924
  FILE *fo;
925
  int i, j, nrf, first;
926
  char tmp[256];
927
  int ncallees[MAX_FUNCS];
928
  int nl[MAX_FUNCS], ns[MAX_FUNCS];
929
  int maxncallees = 0;
930
  sprintf (tmp, "%s_top.v", filename);
931
 
932
  for (i = 0, nrf = 0; i < nfuncs; i++)
933
    {
934
      nl[i] = ns[i] = 0;
935
      ncallees[i] = 0;
936
      if (f[i])
937
        {
938
          f[i]->tmp = nrf++;
939
          for (j = 0; j < f[i]->nmsched; j++)
940
            if (f[i]->mtype[j] & MT_LOAD)
941
              nl[i]++;
942
            else if (f[i]->mtype[j] & MT_STORE)
943
              ns[i]++;
944
          for (j = 0; j < f[i]->nfdeps; j++)
945
            ncallees[f[i]->fdeps[j]->tmp]++;
946
        }
947
    }
948
  if (!nrf)
949
    return;
950
 
951
  for (i = 0; i < nrf; i++)
952
    if (maxncallees < ncallees[i])
953
      maxncallees = ncallees[i];
954
 
955
  log ("Generating verilog file \"%s\"\n", tmp);
956
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
957
  if ((fo = fopen (tmp, "wt+")) == NULL)
958
    {
959
      fprintf (stderr, "Cannot open '%s'\n", tmp);
960
      exit (1);
961
    }
962
 
963
  /* output header */
964
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
965
  GEN ("   (C) 2002 Opencores */\n\n");
966
  GEN ("/* Includes %i functions:", nrf);
967
  for (i = 0; i < nfuncs; i++)
968
    if (f[i])
969
      GEN ("\n%s", prof_func[i].name);
970
  GEN (" */\n\n");
971
 
972
  GEN ("`include \"timescale.v\"\n\n");
973
  GEN ("module %s (clk, rst,\n", filename);
974
  GEN ("              /* Load and store master Wishbone ports */\n");
975
  GEN ("              l_adr_o, l_dat_i, l_cyc_o, l_stb_o,\n");
976
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i, l_we_o,\n");
977
  GEN ("              s_adr_o, s_dat_o, s_cyc_o, s_stb_o,\n");
978
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i, s_we_o,\n\n");
979
  GEN ("              /* cuc interface */\n");
980
  GEN
981
    ("              cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_rdy_o);\n\n");
982
 
983
  GEN ("parameter Tp = 1;\n");
984
  GEN ("\n/* module ports */\n");
985
  GEN ("input         clk, rst, cuc_stb_i, cuc_we_i;\n");
986
  GEN ("input         l_rdy_i, s_rdy_i;\n");
987
  GEN ("output        l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
988
  GEN ("reg           l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
989
  GEN ("output        s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
990
  GEN ("reg           s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
991
  GEN ("output        cuc_rdy_o; /* Not registered ! */\n");
992
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
993
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
994
  GEN ("output [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
995
  GEN ("reg    [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
996
  GEN ("input  [15:0] cuc_adr_i;\n");
997
  GEN ("input  [31:0] l_dat_i, cuc_dat_i;\n\n");
998
 
999
  GEN ("wire   [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n",
1000
       nrf - 1);
1001
  GEN
1002
    ("wire   [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n",
1003
     nrf - 1);
1004
  GEN ("wire   [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
1005
  GEN ("wire   [%2i:0] i_l_req, i_s_req;\n", nrf - 1);
1006
  GEN ("reg    [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
1007
 
1008
  GEN ("assign i_selected = {\n");
1009
  for (i = 0; i < nrf; i++)
1010
    GEN ("    cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
1011
 
1012
  GEN ("assign i_first_reg = {\n");
1013
  for (i = 0; i < nfuncs; i++)
1014
    if (f[i])
1015
      {
1016
        for (j = 0; j <= MAX_REGS; j++)
1017
          if (f[i]->used_regs[j])
1018
            break;
1019
        GEN ("    cuc_adr_i[5:0] == %i%s\n", j,
1020
             f[i]->tmp < nrf - 1 ? "," : "};");
1021
      }
1022
 
1023
  GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
1024
  GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
1025
 
1026
  GEN ("assign i_start = i_go_bsy & {%i{cuc_rdy_o}};\n", nrf);
1027
  GEN ("assign i_start_bidok = {\n");
1028
  for (i = 0; i < nrf; i++)
1029
    GEN ("    i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
1030
  GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
1031
  GEN ("assign main_end = {%i{i_end}} & i_selected;\n",
1032
       nrf - 1);        /* JPB guess at missing args */
1033
 
1034
  GEN ("\nalways @(posedge clk or posedge rst)\n");
1035
  GEN ("begin\n");
1036
  GEN ("  if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
1037
  GEN ("  else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
1038
  GEN ("end\n");
1039
 
1040
 
1041
  /* Function specific data */
1042
  for (i = 0; i < nfuncs; i++)
1043
    if (f[i])
1044
      {
1045
        int ci = 0, co = 0;
1046
        int fn = f[i]->tmp;
1047
        GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
1048
        for (j = 0, first = 1; j < MAX_REGS; j++)
1049
          if (f[i]->used_regs[j])
1050
            {
1051
              GEN ("%s i%i_r%ii", first ? "/* inputs */\nreg    [31:0]" : ",",
1052
                   fn, j);
1053
              first = 0;
1054
              ci++;
1055
            }
1056
        if (ci)
1057
          GEN (";\n");
1058
 
1059
        for (j = 0, first = 1; j < MAX_REGS; j++)
1060
          if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
1061
            {
1062
              GEN ("%s i%i_r%io",
1063
                   first ? "/* outputs */\nwire   [31:0]" : ",", fn, j);
1064
              first = 0;
1065
              co++;
1066
            }
1067
        if (co)
1068
          GEN (";\n");
1069
        GEN ("wire [31:0] i%i_l_adr, i%i_s_adr;\n", fn, fn);
1070
 
1071
        GEN ("always @(posedge clk or posedge rst)\n");
1072
        GEN ("  if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
1073
        GEN
1074
          ("  else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
1075
 
1076
        if (ci)
1077
          {
1078
            GEN ("\n/* write register access */\n");
1079
            GEN ("always @(posedge clk or posedge rst)\n");
1080
            GEN ("begin\n");
1081
            GEN ("  if (rst) begin\n");
1082
            for (j = 0; j < MAX_REGS; j++)
1083
              if (f[i]->used_regs[j])
1084
                GEN ("    i%i_r%ii <= #Tp 32'h0;\n", fn, j);
1085
            GEN ("  end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
1086
            GEN ("    case (cuc_adr_i[5:0])\n");
1087
            for (j = 0; j < MAX_REGS; j++)
1088
              if (f[i]->used_regs[j])
1089
                GEN ("      %-2i: i%i_r%ii <= #Tp cuc_dat_i;\n", j, fn, j);
1090
            GEN ("    endcase\n");
1091
            GEN ("end\n");
1092
          }
1093
 
1094
        GEN ("\n");
1095
      }
1096
 
1097
  /* Generate machine for reading all function registers. Register read can be
1098
     delayed till function completion */
1099
  {
1100
    int co;
1101
    GEN ("/* read register access - data */\n");
1102
    GEN ("always @(posedge clk or posedge rst)\n");
1103
    GEN ("  if (rst) cuc_dat_o <= #Tp 32'h0;\n");
1104
    GEN ("  else if (cuc_stb_i && cuc_we_i) begin\n");
1105
    GEN ("    ");
1106
 
1107
    for (i = 0; i < nfuncs; i++)
1108
      if (f[i])
1109
        {
1110
          co = 0;
1111
          for (j = 0; j < MAX_REGS; j++)
1112
            if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
1113
              co++;
1114
 
1115
          GEN ("if (cuc_adr_i[15:6] == %i)", f[i]->tmp);
1116
          if (co)
1117
            {
1118
              first = 1;
1119
              GEN ("\n      case (cuc_adr_i[5:0])\n");
1120
              for (j = 0; j < MAX_REGS; j++)
1121
                if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
1122
                  GEN ("        %-2i: cuc_dat_o <= #Tp i%i_r%io;\n", j,
1123
                       f[i]->tmp, j);
1124
              GEN ("      endcase\n");
1125
            }
1126
          else
1127
            {
1128
              GEN ("      cuc_dat_o <= #Tp 32'hx;\n");
1129
            }
1130
          GEN ("    else ");
1131
        }
1132
    GEN ("cuc_dat_o <= #Tp 32'hx;\n");
1133
    GEN ("  end else cuc_dat_o <= #Tp 32'hx;\n");
1134
 
1135
    GEN ("\n/* read register access - acknowledge */\n");
1136
    GEN
1137
      ("assign cuc_rdy_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
1138
  }
1139
 
1140
  /* Store/load Wishbone bridge */
1141
  for (j = 0; j < 2; j++)
1142
    {
1143
      char t = j ? 's' : 'l';
1144
      GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
1145
      GEN ("reg [%i:0] %cm_sel;\n", log2_int (nrf), t);
1146
      GEN ("reg [%i:0] %cm_bid;\n", log2_int (nrf), t);
1147
      GEN ("reg       %ccyc_ip;\n\n", t);
1148
      GEN ("always @(posedge clk)\n");
1149
      GEN ("begin\n");
1150
      GEN ("  %c_we_o <= #Tp 1'b%i;\n", t, j);
1151
      GEN ("  %c_cyc_o <= #Tp |i_%c_req;\n", t, t);
1152
      GEN ("  %c_stb_o <= #Tp |i_%c_req;\n", t, t);
1153
      GEN ("end\n");
1154
 
1155
      GEN ("\n/* highest bid */\n");
1156
      GEN ("always @(");
1157
      for (i = 0; i < nrf; i++)
1158
        GEN ("%si_%c_req", i > 0 ? " or " : "", t);
1159
      GEN (")\n");
1160
      for (i = 0; i < nrf; i++)
1161
        GEN ("  %sif (i_%c_req) %cm_bid = %i'h%x;\n",
1162
             i ? "else " : "", t, t, log2_int (nrf) + 1, i);
1163
 
1164
      GEN ("\n/* selected transfer */\n");
1165
      GEN ("always @(posedge clk or posedge rst)\n");
1166
      GEN ("  if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2_int (nrf) + 1);
1167
      GEN ("  else if (%c_rdy_i) %cm_sel <= #Tp %i'h0;\n", t, t,
1168
           log2_int (nrf) + 1);
1169
      GEN ("  else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
1170
 
1171
      GEN ("\n/* Cycle */\n");
1172
      GEN ("\nalways @(posedge clk or posedge rst)\n");
1173
      GEN ("  if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
1174
      GEN ("  else if (%c_rdy_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
1175
      GEN ("  else %ccyc_ip <= #Tp %c_cyc_o;\n", t, t);
1176
    }
1177
 
1178
  GEN ("\n/* Acknowledge */\n");
1179
  for (i = 0; i < nrf; i++)
1180
    {
1181
      GEN
1182
        ("wire i%i_s_rdy = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & s_rdy_i;\n",
1183
         i, i, i);
1184
      GEN
1185
        ("wire i%i_l_rdy = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & l_rdy_i;\n",
1186
         i, i, i);
1187
    }
1188
 
1189
  GEN ("\n/* data, address selects and burst enables */\n");
1190
  for (i = 0; i < nrf; i++)
1191
    GEN ("wire [31:0] i%i_s_dat;\n", i);
1192
  for (i = 0; i < nrf; i++)
1193
    GEN ("wire i%i_s_linbrst, i%i_l_linbrst;\n", i, i);
1194
  for (i = 0; i < nrf; i++)
1195
    GEN ("wire [3:0]  i%i_s_sel, i%i_l_sel;\n", i, i);
1196
  for (i = 0; i < nrf; i++)
1197
    GEN ("wire [31:0] i%i_l_dat = l_dat_i;\n", i);
1198
  GEN ("\nalways @(posedge clk)\n");
1199
  GEN ("begin\n");
1200
  GEN ("  s_dat_o <= #Tp ");
1201
  for (i = 0; i < nrf - 1; i++)
1202
    GEN ("\n    sm_bid == %i ? i%i_s_dat : ", i, i);
1203
  GEN ("i%i_s_dat;\n", nrf - 1);
1204
  GEN ("  s_adr_o <= #Tp ");
1205
  for (i = 0; i < nrf - 1; i++)
1206
    GEN ("\n    sm_bid == %i ? i%i_s_adr : ", i, i);
1207
  GEN ("i%i_s_adr;\n", nrf - 1);
1208
  GEN ("  s_sel_o <= #Tp ");
1209
  for (i = 0; i < nrf - 1; i++)
1210
    GEN ("\n    sm_bid == %i ? i%i_s_sel : ", i, i);
1211
  GEN ("i%i_s_sel;\n", nrf - 1);
1212
  GEN ("  s_linbrst_o <= #Tp ");
1213
  for (i = 0; i < nrf - 1; i++)
1214
    GEN ("\n    sm_bid == %i ? i%i_s_linbrst : ", i, i);
1215
  GEN ("i%i_s_linbrst;\n", nrf - 1);
1216
  GEN ("end\n\n");
1217
 
1218
  GEN ("always @(posedge clk)\n");
1219
  GEN ("begin\n");
1220
  GEN ("  l_adr_o <= #Tp ");
1221
  for (i = 0; i < nrf - 1; i++)
1222
    GEN ("\n    lm_bid == %i ? i%i_l_adr : ", i, i);
1223
  GEN ("i%i_l_adr;\n", nrf - 1);
1224
  GEN ("  l_sel_o <= #Tp ");
1225
  for (i = 0; i < nrf - 1; i++)
1226
    GEN ("\n    lm_bid == %i ? i%i_l_sel : ", i, i);
1227
  GEN ("i%i_l_sel;\n", nrf - 1);
1228
  GEN ("  l_linbrst_o <= #Tp ");
1229
  for (i = 0; i < nrf - 1; i++)
1230
    GEN ("\n    lm_bid == %i ? i%i_l_linbrst : ", i, i);
1231
  GEN ("i%i_l_linbrst;\n", nrf - 1);
1232
  GEN ("end\n\n");
1233
 
1234
  /* start/end signals */
1235
  GEN ("\n\n/* start/end signals */\n");
1236
  for (i = 0; i < nrf; i++)
1237
    {
1238
      if (log2_int (maxncallees + 1))
1239
        GEN
1240
          ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
1241
           log2_int (maxncallees + 1), i, i, i, i);
1242
      else
1243
        GEN ("wire i%i_current = 0;\n", i);
1244
    }
1245
  GEN ("\n");
1246
 
1247
  for (i = 0, j = 0; i < nfuncs; i++)
1248
    if (f[i])
1249
      {
1250
        if (log2_int (ncallees[i]))
1251
          {
1252
            GEN ("reg [%i:0] i%i_start_bid;\n", log2_int (ncallees[i]), j);
1253
            GEN ("always @(start%i", f[i]->tmp);
1254
            for (j = 0, first = 1; j < f[i]->nfdeps; j++)
1255
              if (f[i]->fdeps[j])
1256
                GEN (", ");
1257
            GEN (")\n");
1258
            GEN ("begin !!!\n");        //TODO
1259
            GEN ("  \n");
1260
            GEN ("end\n");
1261
          }
1262
        GEN ("wire i%i_start = main_start[%i];\n", j, j);
1263
        j++;
1264
      }
1265
  GEN ("\n");
1266
 
1267
  for (i = 0; i < nfuncs; i++)
1268
    if (f[i])
1269
      {
1270
        int nf = f[i]->tmp;
1271
        GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename,
1272
             prof_func[i].name, nf);
1273
        GEN
1274
          ("  .l_adr_o(i%i_l_adr), .l_dat_i(i%i_l_dat), .l_req_o(i_l_req[%i]),\n",
1275
           nf, nf, nf);
1276
        GEN
1277
          ("  .l_sel_o(i%i_l_sel), .l_linbrst_o(i%i_l_linbrst), .l_rdy_i(i%i_l_rdy),\n",
1278
           nf, nf, nf);
1279
        GEN
1280
          ("  .s_adr_o(i%i_s_adr), .s_dat_o(i%i_s_dat), .s_req_o(i_s_req[%i]),\n",
1281
           nf, nf, nf);
1282
        GEN
1283
          ("  .s_sel_o(i%i_s_sel), .s_linbrst_o(i%i_s_linbrst), .s_rdy_i(i%i_s_rdy),\n",
1284
           nf, nf, nf);
1285
        GEN ("  ");
1286
        for (j = 0, first = 1; j < MAX_REGS; j++)
1287
          if (f[i]->used_regs[j])
1288
            GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
1289
 
1290
        if (first)
1291
          GEN ("\n  ");
1292
        for (j = 0, first = 1; j < MAX_REGS; j++)
1293
          if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
1294
            GEN (".r%i_o(i%i_r%io), ", j, nf, j), first = 0;
1295
        if (first)
1296
          GEN ("\n  ");
1297
        if (f[i]->nfdeps)
1298
          {
1299
            GEN
1300
              (".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n",
1301
               i, i, i),
1302
              GEN
1303
              ("  .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n",
1304
               i, i, i, i);     /* JPB guess at missing args */
1305
            GEN
1306
              ("  .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n  ",
1307
               i, i, i);        /* JPB guess at missing args */
1308
          }
1309
        GEN
1310
          (".start_i(i_start[%i]), .end_o(i_end[%i]), .busy_o(i_busy[%i]));\n",
1311
           nf, nf, nf);
1312
      }
1313
 
1314
  /* output footer */
1315
  GEN ("\nendmodule\n");
1316
 
1317
  fclose (fo);
1318
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.