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[/] [openrisc/] [trunk/] [or1ksim/] [debug/] [debug-unit.c] - Blame information for rev 496

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1 19 jeremybenn
/* debug_unit.c -- Simulation of Or1k debug unit
2
 
3
   Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
22
 
23
/* This program is commented throughout in a fashion suitable for processing
24
   with Doxygen. */
25
 
26
/* This is an architectural level simulation of the Or1k debug unit as
27
   described in OpenRISC 1000 System Architecture Manual, v. 0.1 on 22 April,
28
   2001. This unit is described in Section 13.
29
 
30
   Every attempt has been made to be as accurate as possible with respect to
31
   the registers and the behavior. There are no known limitations at this
32
   time.
33
 
34
   Note in particular that there is an alternative (smaller) debug unit on the
35
   OpenCores website, designed by Igor Mohor. At present this interface is NOT
36
   supported here. */
37
 
38
/* Autoconf and/or portability configuration */
39
#include "config.h"
40
#include "port.h"
41
 
42
/* System includes */
43
#include <stdlib.h>
44
#include <stdio.h>
45
#include <assert.h>
46
 
47
/* Package includes */
48
#include "arch.h"
49
#include "debug-unit.h"
50
#include "sim-config.h"
51
#include "except.h"
52
#include "abstract.h"
53
#include "parse.h"
54
#include "gdb.h"
55
#include "except.h"
56
#include "opcode/or32.h"
57
#include "spr-defs.h"
58
#include "execute.h"
59
#include "sprs.h"
60
#include "toplevel-support.h"
61
#include "rsp-server.h"
62
 
63
 
64
/*! The fields for the RISCOP register in the development interface scan chain
65
    (JTAG_CHAIN_DEVELOPMENT). */
66
#define RISCOP_STALL  0x00000001        /*!< Stall processor */
67
#define RISCOP_RESET  0x00000002        /*!< Reset processor (clears stall) */
68
 
69
/*! The various addresses in the development interface scan chain
70
    (JTAG_CHAIN_DEVELOPMENT). Only documents the ones we actually have*/
71
enum development_interface_address_space
72
{
73
  DEVELOPINT_RISCOP  =  4,
74
  DEVELOPINT_MAX     = 27,
75
};
76
 
77
/*! Data structure holding debug registers and their bits */
78
unsigned long  development[DEVELOPINT_MAX + 1];
79
 
80
/*! The current scan chain being accessed */
81
static enum debug_scan_chain_ids current_scan_chain = JTAG_CHAIN_GLOBAL;
82
 
83
/*! External STALL signal to debug interface */
84
static int in_reset = 0;
85
 
86
/*! Forward declaration of static functions */
87
static int calculate_watchpoints (enum debug_unit_action action,
88
                                  unsigned long          udata);
89
static int get_devint_reg (unsigned int   addr,
90
                           unsigned long *data);
91
static int set_devint_reg (unsigned int   addr,
92
                           unsigned long  data);
93
static int debug_set_mem (oraddr_t address, uorreg_t data);
94
static int debug_get_mem (oraddr_t address, uorreg_t * data);
95
 
96
 
97
 
98
/*---------------------------------------------------------------------------*/
99
/*!Reset the debug unit
100
 
101
   Clear all development inteface registers                                  */
102
/*---------------------------------------------------------------------------*/
103
void
104
du_reset ()
105
{
106
  int  i;
107
 
108
  for (i = 0; i <= DEVELOPINT_MAX; i++)
109
    {
110
      development[i] = 0;
111
    }
112
 
113
  set_stall_state (0);
114
 
115
}       /* du_reset () */
116
 
117
 
118
/*---------------------------------------------------------------------------*/
119
/*!Set the stall state of the processor
120
 
121
   @param[in] state  If non-zero stall the processor.                        */
122
/*---------------------------------------------------------------------------*/
123
void
124
set_stall_state (int state)
125
{
126
#if DYNAMIC_EXECUTION
127
  if (state)
128
    {
129
      PRINTF("FIXME: Emulating a stalled cpu not implemented "
130
             "(in the dynamic execution model)\n");
131
    }
132
#endif
133
 
134
  development[DEVELOPINT_RISCOP] &= ~RISCOP_STALL;
135
  development[DEVELOPINT_RISCOP] |= state ? RISCOP_STALL : 0;
136
 
137
  runtime.cpu.stalled             = state;
138
 
139
  /* If we unstall, any changed NPC becomes valid again */
140
 
141
  if (!runtime.cpu.stalled)
142
    {
143
      cpu_state.npc_not_valid = 0;
144
    }
145
}       /* set_stall_state () */
146
 
147
 
148
/*---------------------------------------------------------------------------*/
149
/*!Check for a breakpoint on this action
150
 
151
   @note This does not include single-stepping - that will be picked up in the
152
   main loop AFTER the instruction has executed.
153
 
154
   @param[in] action  The action to be checked
155
   @param[in] udata   The data to compare against (for some actions)
156
 
157
   @return  Non-zero if there was a breakpoint, 0 otherwise.                 */
158
/*---------------------------------------------------------------------------*/
159
int
160
check_debug_unit (enum debug_unit_action  action,
161
                  unsigned long           udata)
162
{
163
  /* Do not stop if we have debug module disabled or during reset */
164
  if (!config.debug.enabled || in_reset)
165
    {
166
      return 0;
167
    }
168
 
169
  /* is any watchpoint enabled to generate a break or count? If not, ignore */
170
  if (cpu_state.sprs[SPR_DMR2] & (SPR_DMR2_WGB | SPR_DMR2_AWTC))
171
    {
172
      return  calculate_watchpoints (action, udata);
173
    }
174
 
175
  return 0;                      /* No breakpoint */
176
 
177
}       /* check_debug_unit () */
178
 
179
 
180
/*---------------------------------------------------------------------------*/
181
/*!Check whether we should stall the RISC or cause an exception.
182
 
183
   Rewritten by JPB for current architecture.
184
 
185
   @param[in] action  The action to be checked
186
   @param[in] udata   The data to compare against (for some actions)
187
 
188
   @return  Non-zero if this should generate a breakpoint                    */
189
/*---------------------------------------------------------------------------*/
190
static int
191
calculate_watchpoints (enum debug_unit_action  action,
192
                       unsigned long           udata)
193
{
194
  int  i;
195
  int  match_found      = 0;             /* Flag if we found any matchpoint */
196
  int  breakpoint_found;                /* Flag if we found any breakpoint */
197
 
198
  /* Debug registers */
199
  unsigned long  dmr1;
200
  unsigned long  dmr2;
201
 
202
  /* Debug bit fields */
203
  unsigned char  counter0_enabled;
204
  unsigned char  counter1_enabled;
205
  unsigned char  counter0_matched;
206
  unsigned char  counter1_matched;
207
 
208
  unsigned char  mp[MAX_MATCHPOINTS];   /* Which matchpoints matched */
209
  unsigned char  wp[MAX_WATCHPOINTS];   /* Which watchpoints matched */
210
 
211 82 jeremybenn
  memset (mp, 0, sizeof (mp));
212
  memset (wp, 0, sizeof (wp));
213 19 jeremybenn
 
214
  /* First find the matchpoints */
215
 
216
  for (i = 0; i < MAX_MATCHPOINTS; i++)
217
    {
218
      unsigned long  dcr    = cpu_state.sprs[SPR_DCR (i)];
219
      unsigned char  dcr_dp = dcr & SPR_DCR_DP;
220
      unsigned char  dcr_cc;
221
      unsigned char  dcr_sc;
222
      unsigned char  dcr_ct;
223
      int            match_so_far;
224
 
225
      if (SPR_DCR_DP != dcr_dp)
226
        {
227
          continue;
228
        }
229
 
230
      dcr_ct       = dcr & SPR_DCR_CT;
231
      match_so_far = 0;
232
 
233
      switch (dcr_ct)
234
        {
235
        case SPR_DCR_CT_IFEA:
236
          match_so_far = (DebugInstructionFetch == action);
237
          break;
238
 
239
        case SPR_DCR_CT_LEA:
240
          match_so_far = (DebugLoadAddress == action);
241
          break;
242
 
243
        case SPR_DCR_CT_SEA:
244
          match_so_far = (DebugStoreAddress == action);
245
          break;
246
 
247
        case SPR_DCR_CT_LD:
248
          match_so_far = (DebugLoadData == action);
249
          break;
250
 
251
        case SPR_DCR_CT_SD:
252
          match_so_far = (DebugStoreData == action);
253
          break;
254
 
255
        case SPR_DCR_CT_LSEA:
256
          match_so_far = (DebugLoadAddress == action) ||
257
            (DebugStoreAddress == action);
258
          break;
259
 
260
        case SPR_DCR_CT_LSD:
261
          match_so_far = (DebugLoadData == action) ||
262
            (DebugStoreData == action);
263
          break;
264
 
265
        default:
266
          break;
267
        }
268
 
269
      if (!match_so_far)
270
        {
271
          continue;                     /* Skip to the end of the loop */
272
        }
273
 
274
      dcr_sc = dcr & SPR_DCR_SC;
275
      dcr_cc = dcr & SPR_DCR_CC;
276
 
277
      /* Perform signed comparison?  */
278
      if (SPR_DCR_SC == dcr_sc)
279
        {
280
          long int sop1 = udata;
281
          long int sop2 = cpu_state.sprs[SPR_DVR (i)];
282
 
283
          switch (dcr & SPR_DCR_CC)
284
            {
285
            case SPR_DCR_CC_MASKED:
286
              mp[i] = sop1 & sop2;
287
              break;
288
 
289
            case SPR_DCR_CC_EQUAL:
290
              mp[i] = sop1 == sop2;
291
              break;
292
 
293
            case SPR_DCR_CC_NEQUAL:
294
              mp[i] = sop1 != sop2;
295
              break;
296
 
297
            case SPR_DCR_CC_LESS:
298
              mp[i] = sop1 < sop2;
299
              break;
300
 
301
            case SPR_DCR_CC_LESSE:
302
              mp[i] = sop1 <= sop2;
303
              break;
304
 
305
            case SPR_DCR_CC_GREAT:
306
              mp[i] = sop1 > sop2;
307
              break;
308
 
309
            case SPR_DCR_CC_GREATE:
310
              mp[i] = sop1 >= sop2;
311
              break;
312
 
313
            default:
314
              break;
315
            }
316
        }
317
      else
318
        {
319
          unsigned long int op1 = udata;
320
          unsigned long int op2 = cpu_state.sprs[SPR_DVR (i)];
321
 
322
          switch (dcr & SPR_DCR_CC)
323
            {
324
            case SPR_DCR_CC_MASKED:
325
              mp[i] = op1 & op2;
326
              break;
327
 
328
            case SPR_DCR_CC_EQUAL:
329
              mp[i] = op1 == op2;
330
              break;
331
 
332
            case SPR_DCR_CC_NEQUAL:
333
              mp[i] = op1 != op2;
334
              break;
335
 
336
            case SPR_DCR_CC_LESS:
337
              mp[i] = op1 < op2;
338
              break;
339
 
340
            case SPR_DCR_CC_LESSE:
341
              mp[i] = op1 <= op2;
342
              break;
343
 
344
            case SPR_DCR_CC_GREAT:
345
              mp[i] = op1 > op2;
346
              break;
347
 
348
            case SPR_DCR_CC_GREATE:
349
              mp[i] = op1 >= op2;
350
              break;
351
 
352
            default:
353
              break;
354
            }
355
        }
356
 
357
      if (mp[i])
358
        {
359
          match_found = 1;      /* A match was found */
360
        }
361
    }
362
 
363
  /* If no match was found, give up here, since none of the watchpoints will
364
     change. */
365
 
366
  if (!match_found)
367
    {
368
      return 0;
369
    }
370
 
371
  /* Compute the non-counting watchpoints. Done by slog, since each one is
372
     different. The counting watchpoints will be done AFTER the counts have
373
     been incremented. Done in order, so the chaining works correctly. This
374
     code expects the number of matchpoints to be 8. As a precaution, that is
375
     asserted here.
376
 
377
     IMPORTANT.....
378
 
379
     The architecture manual appears to be wrong, in suggesting that
380
     watchpoint 4 chains with external watchpoint in the same way as
381
     watchpoint 0. The Verilog source code suggests it chains with watchpoint
382
     3. */
383
 
384
  assert (MAX_MATCHPOINTS == 8);
385
 
386
  dmr1 = cpu_state.sprs[SPR_DMR1];
387
 
388
  switch (dmr1 & SPR_DMR1_CW0)
389
    {
390
    case 0:
391
      wp[0] = mp[0];
392
      break;
393
 
394
    case SPR_DMR1_CW0_AND:
395
      printf ("External watchpoint not supported\n");
396
      break;
397
 
398
    case SPR_DMR1_CW0_OR:
399
      printf ("External watchpoint not supported\n");
400
      break;
401
 
402
    case SPR_DMR1_CW0:
403
      printf ("SPR DMR1_CW0=11 reserved\n");
404
      break;
405
    }
406
 
407
  switch (dmr1 & SPR_DMR1_CW1)
408
    {
409
    case 0:
410
      wp[1] = mp[1];
411
      break;
412
 
413
    case SPR_DMR1_CW1_AND:
414
      wp[1] = mp[1] && wp[0];
415
      break;
416
 
417
    case SPR_DMR1_CW1_OR:
418
      wp[1] = mp[1] || wp[0];
419
      break;
420
 
421
    case SPR_DMR1_CW1:
422
      printf ("SPR DMR1_CW1=11 reserved\n");
423
      break;
424
    }
425
 
426
  switch (dmr1 & SPR_DMR1_CW2)
427
    {
428
    case 0:
429
      wp[2] = mp[2];
430
      break;
431
 
432
    case SPR_DMR1_CW2_AND:
433
      wp[2] = mp[2] && wp[1];
434
      break;
435
 
436
    case SPR_DMR1_CW2_OR:
437
      wp[2] = mp[2] || wp[1];
438
      break;
439
 
440
    case SPR_DMR1_CW2:
441
      printf ("SPR DMR1_CW2=11 reserved\n");
442
      break;
443
    }
444
 
445
  switch (dmr1 & SPR_DMR1_CW3)
446
    {
447
    case 0:
448
      wp[3] = mp[3];
449
      break;
450
 
451
    case SPR_DMR1_CW3_AND:
452
      wp[3] = mp[3] && wp[2];
453
      break;
454
 
455
    case SPR_DMR1_CW3_OR:
456
      wp[3] = mp[3] || wp[2];
457
      break;
458
 
459
    case SPR_DMR1_CW3:
460
      printf ("SPR DMR1_CW3=11 reserved\n");
461
      break;
462
    }
463
 
464
  switch (dmr1 & SPR_DMR1_CW4)
465
    {
466
    case 0:
467
      wp[4] = mp[4];
468
      break;
469
 
470
    case SPR_DMR1_CW4_AND:
471
      wp[4] = mp[4] && wp[3];
472
      break;
473
 
474
    case SPR_DMR1_CW4_OR:
475
      wp[4] = mp[4] || wp[3];
476
      break;
477
 
478
    case SPR_DMR1_CW4:
479
      printf ("SPR DMR1_CW4=11 reserved\n");
480
      break;
481
    }
482
 
483
  switch (dmr1 & SPR_DMR1_CW5)
484
    {
485
    case 0:
486
      wp[5] = mp[5];
487
      break;
488
 
489
    case SPR_DMR1_CW5_AND:
490
      wp[5] = mp[5] && wp[4];
491
      break;
492
 
493
    case SPR_DMR1_CW5_OR:
494
      wp[5] = mp[5] || wp[4];
495
      break;
496
 
497
    case SPR_DMR1_CW5:
498
      printf ("SPR DMR1_CW5=11 reserved\n");
499
      break;
500
    }
501
 
502
  switch (dmr1 & SPR_DMR1_CW6)
503
    {
504
    case 0:
505
      wp[6] = mp[6];
506
      break;
507
 
508
    case SPR_DMR1_CW6_AND:
509
      wp[6] = mp[6] && wp[5];
510
      break;
511
 
512
    case SPR_DMR1_CW6_OR:
513
      wp[6] = mp[6] || wp[5];
514
      break;
515
 
516
    case SPR_DMR1_CW6:
517
      printf ("SPR DMR1_CW6=11 reserved\n");
518
      break;
519
    }
520
 
521
  switch (dmr1 & SPR_DMR1_CW7)
522
    {
523
    case 0:
524
      wp[7] = mp[7];
525
      break;
526
 
527
    case SPR_DMR1_CW7_AND:
528
      wp[7] = mp[7] && wp[6];
529
      break;
530
 
531
    case SPR_DMR1_CW7_OR:
532
      wp[7] = mp[7] || wp[6];
533
      break;
534
 
535
    case SPR_DMR1_CW7:
536
      printf ("SPR DMR1_CW7=11 reserved\n");
537
      break;
538
    }
539
 
540
  /* Increment counters. Note the potential ambiguity, if the last two
541
     watchpoints, which depend on the counters, also increment the
542
     counters. Since they cannot yet be set, they are not tested here. */
543
 
544
  dmr2             = cpu_state.sprs[SPR_DMR2];
545
 
546
  counter0_enabled = SPR_DMR2_WCE0 == (dmr2 & SPR_DMR2_WCE0);
547
  counter1_enabled = SPR_DMR2_WCE1 == (dmr2 & SPR_DMR2_WCE1);
548
 
549
  if (counter0_enabled || counter1_enabled)
550
    {
551
      short int  counter0 = cpu_state.sprs[SPR_DWCR0] & SPR_DWCR_COUNT;
552
      short int  counter1 = cpu_state.sprs[SPR_DWCR1] & SPR_DWCR_COUNT;
553
 
554
      for (i = 0; i < MAX_WATCHPOINTS - 2; i++)
555
        {
556
          int  use_counter_0 = (dmr2 >> (SPR_DMR2_AWTC_OFF + i) & 1) != 1;
557
 
558
          if (use_counter_0)
559
            {
560
              if (counter0_enabled && wp[i])
561
                {
562
                  counter0++;
563
                }
564
            }
565
          else
566
            {
567
              if (counter1_enabled && wp[i])
568
                {
569
                  counter1++;
570
                }
571
            }
572
        }
573
 
574
      cpu_state.sprs[SPR_DWCR0] &= ~SPR_DWCR_COUNT;
575
      cpu_state.sprs[SPR_DWCR0] |= counter0;
576
      cpu_state.sprs[SPR_DWCR1] &= ~SPR_DWCR_COUNT;
577
      cpu_state.sprs[SPR_DWCR1] |= counter1;
578
    }
579
 
580
  /* Sort out the last two matchpoints, which depend on counters
581
 
582
     IMPORTANT.....
583
 
584
     The architecture manual appears to be wrong, in suggesting that
585
     watchpoint 8 chains with watchpoint 3 and watchpoint 9 chains with
586
     watchpoint 7. The Verilog source code suggests watchpoint 8 chains with
587
     watchpoint 7 and watchpoint 9 chains with watchpoint 8. */
588
 
589
  counter0_matched =
590
    ((cpu_state.sprs[SPR_DWCR0] & SPR_DWCR_COUNT) ==
591
     ((cpu_state.sprs[SPR_DWCR0] & SPR_DWCR_MATCH) >> SPR_DWCR_MATCH_OFF));
592
  counter1_matched =
593
    ((cpu_state.sprs[SPR_DWCR1] & SPR_DWCR_COUNT) ==
594
     ((cpu_state.sprs[SPR_DWCR1] & SPR_DWCR_MATCH) >> SPR_DWCR_MATCH_OFF));
595
 
596
  switch (dmr1 & SPR_DMR1_CW8)
597
    {
598
    case 0:
599
      wp[8] = counter0_matched;
600
      break;
601
 
602
    case SPR_DMR1_CW8_AND:
603
      wp[8] = counter0_matched && wp[7];
604
      break;
605
 
606
    case SPR_DMR1_CW8_OR:
607
      wp[8] = counter0_matched || wp[7];
608
      break;
609
 
610
    case SPR_DMR1_CW8:
611
      printf ("SPR DMR1_CW8=11 reserved\n");
612
      break;
613
    }
614
 
615
  switch (dmr1 & SPR_DMR1_CW9)
616
    {
617
    case 0:
618
      wp[9] = counter1_matched;
619
      break;
620
 
621
    case SPR_DMR1_CW9_AND:
622
      wp[9] = counter1_matched && wp[8];
623
      break;
624
 
625
    case SPR_DMR1_CW9_OR:
626
      wp[9] = counter1_matched || wp[8];
627
      break;
628
 
629
    case SPR_DMR1_CW9:
630
      printf ("SPR DMR1_CW9=11 reserved\n");
631
      break;
632
    }
633
 
634
  /* Now work out which watchpoints (if any) have caused a breakpoint and
635
     update the breakpoint status bits */
636
 
637
  breakpoint_found = 0;
638
 
639
  for (i = 0; i < MAX_WATCHPOINTS; i++)
640
    {
641
      if (1 == (dmr2 >> (SPR_DMR2_WGB_OFF + i) & 1))
642
        {
643
          if (wp[i])
644
            {
645
              dmr2             |= 1 << (SPR_DMR2_WBS_OFF + i);
646
              breakpoint_found  = 1;
647
            }
648
        }
649
    }
650
 
651
  cpu_state.sprs[SPR_DMR2] = dmr2;
652
 
653
  return breakpoint_found;
654
 
655
}       /* calculate_watchpoints () */
656
 
657
 
658
/*---------------------------------------------------------------------------*/
659
/*!Get a JTAG register
660
 
661
   Action depends on which scan chain is currently active.
662
 
663
   @param[in]  address  Address on the scan chain
664
   @param[out] data     Where to put the result of the read
665
 
666
   @return  An error code (including ERR_NONE) if there is no error          */
667
/*---------------------------------------------------------------------------*/
668
int
669
debug_get_register (oraddr_t  address,
670
                    uorreg_t *data)
671
{
672
  int  err = ERR_NONE;
673
 
674
  switch (current_scan_chain)
675
    {
676
    case JTAG_CHAIN_DEBUG_UNIT:
677
      *data = mfspr (address);
678
      break;
679
 
680
    case JTAG_CHAIN_TRACE:
681
      err = JTAG_PROXY_INVALID_CHAIN;   /* Not yet implemented */
682
      break;
683
 
684
    case JTAG_CHAIN_DEVELOPMENT:
685
      err = get_devint_reg (address, (unsigned long *)data);
686
      break;
687
 
688
    case JTAG_CHAIN_WISHBONE:
689
      err = debug_get_mem (address, data);
690
      break;
691
 
692
    default:
693
      err = JTAG_PROXY_INVALID_CHAIN;
694
    }
695
 
696
  return  err;
697
 
698
}       /* debug_get_register () */
699
 
700
 
701
/*---------------------------------------------------------------------------*/
702
/*!Set a JTAG register
703
 
704
   Action depends on which scan chain is currently active.
705
 
706
   @param[in]  address  Address on the scan chain
707
   @param[out] data     Data to set
708
 
709
   @return  An error code (including ERR_NONE) if there is no error          */
710
/*---------------------------------------------------------------------------*/
711
int
712
debug_set_register (oraddr_t  address,
713
                    uorreg_t  data)
714
{
715
  int  err = ERR_NONE;
716
 
717
  switch (current_scan_chain)
718
    {
719
    case JTAG_CHAIN_DEBUG_UNIT:
720
      mtspr (address, data);
721
      break;
722
 
723
    case JTAG_CHAIN_TRACE:
724
      err = JTAG_PROXY_ACCESS_EXCEPTION;        /* Not yet implemented */
725
      break;
726
 
727
    case JTAG_CHAIN_DEVELOPMENT:
728
      err = set_devint_reg (address, data);
729
      break;
730
 
731
    case JTAG_CHAIN_WISHBONE:
732
      err = debug_set_mem (address, data);
733
      break;
734
 
735
    default:
736
      err = JTAG_PROXY_INVALID_CHAIN;
737
    }
738
 
739
  return err;
740
 
741
}       /* debug_set_register () */
742
 
743
 
744
/*---------------------------------------------------------------------------*/
745
/*!Set the JTAG chain
746
 
747
   Only permit chains we support. Currently TRACE is not implemented.
748
 
749
   @param[in] chain  Chain to be set as current
750
 
751
   @return  An error code (including ERR_NONE) if there is no error          */
752
/*---------------------------------------------------------------------------*/
753
int
754
debug_set_chain (enum debug_scan_chain_ids  chain)
755
{
756
  switch (chain)
757
    {
758
    case JTAG_CHAIN_DEBUG_UNIT:
759
    case JTAG_CHAIN_DEVELOPMENT:
760
    case JTAG_CHAIN_WISHBONE:
761
      current_scan_chain = chain;
762
      break;
763
 
764
    case JTAG_CHAIN_TRACE:
765
      return  JTAG_PROXY_INVALID_CHAIN; /* Not yet implemented */
766
 
767
    default:
768
      return  JTAG_PROXY_INVALID_CHAIN; /* All other chains not implemented */
769
    }
770
 
771
  return  ERR_NONE;
772
 
773
}       /* debug_set_chain() */
774
 
775
 
776
/*---------------------------------------------------------------------------*/
777
/*!Get a development interface register
778
 
779
   No side effects on get - just return the register
780
 
781
   @param[in]  address  The register to get
782
   @param[out] data     Where to put the result
783
 
784
   @return  An error code (including ERR_NONE) if there is no error          */
785
/*---------------------------------------------------------------------------*/
786
static int
787
get_devint_reg (enum development_interface_address_space  address,
788
                unsigned long                            *data)
789
{
790
  int  err = ERR_NONE;
791
 
792
  if (address <= DEVELOPINT_MAX)
793
    {
794
      *data = development[address];
795
    }
796
  else
797
    {
798
      err = JTAG_PROXY_INVALID_ADDRESS;
799
    }
800
 
801
  return  err;
802
 
803
}       /* get_devint_reg () */
804
 
805
 
806
/*---------------------------------------------------------------------------*/
807
/*!Set a development interface register
808
 
809
   Sets the value of the corresponding register. Only RISC_OP has any
810
   side-effects. The others just store the value, so it can be read back.
811
 
812
   @param[in] address  The register to set
813
   @param[in] data     The data to set
814
 
815
   @return  An error code (including ERR_NONE) if there is no error          */
816
/*---------------------------------------------------------------------------*/
817
static int
818
set_devint_reg (enum development_interface_address_space  address,
819
                unsigned long                             data)
820
{
821
  int err =  ERR_NONE;
822
 
823
  if (DEVELOPINT_RISCOP == address)
824
    {
825
      int old_value = (development[DEVELOPINT_RISCOP] & RISCOP_RESET) != 0;
826
 
827
      development[DEVELOPINT_RISCOP] = data;
828
      in_reset                       = ((data & RISCOP_RESET) != 0);
829
 
830
      /* Reset the cpu on the negative edge of RESET */
831
      if (old_value && !in_reset)
832
        {
833
          sim_reset ();         /* Reset all units */
834
        }
835
 
836
      set_stall_state ((development[DEVELOPINT_RISCOP] & RISCOP_STALL) != 0);
837
    }
838
  else if (address <= DEVELOPINT_MAX)
839
    {
840
      development[address] = data;
841
    }
842
  else
843
    {
844
      err = JTAG_PROXY_INVALID_ADDRESS;
845
    }
846
 
847
  return  err;
848
 
849
}       /* set_devint_reg() */
850
 
851
 
852
/*---------------------------------------------------------------------------*/
853
/*!Read from main bus
854
 
855
   @param[in]  address  Address to read from
856
   @param[out] data     Where to put the result
857
 
858
   @return  An error code (including ERR_NONE) if there is no error          */
859
/*---------------------------------------------------------------------------*/
860
static int
861
debug_get_mem (oraddr_t  address,
862
               uorreg_t *data)
863
{
864
  int  err = ERR_NONE;
865
 
866
  if (!verify_memoryarea (address))
867
    {
868
    err = JTAG_PROXY_INVALID_ADDRESS;
869
    }
870
  else
871
    {
872
      *data = eval_direct32 (address, 0, 0);
873
    }
874
 
875
  return  err;
876
 
877
}       /* debug_get_mem () */
878
 
879
 
880
/*---------------------------------------------------------------------------*/
881
/*!Write to main bus
882
 
883
   @param[in]  address  Address to write to
884
   @param[out] data     Data to write
885
 
886
   @return  An error code (including ERR_NONE) if there is no error          */
887
/*---------------------------------------------------------------------------*/
888
static int
889
debug_set_mem (oraddr_t  address,
890
               uint32_t  data)
891
{
892
  int  err = ERR_NONE;
893
 
894
  if (!verify_memoryarea (address))
895
    {
896
      err = JTAG_PROXY_INVALID_ADDRESS;
897
    }
898
  else
899
    {
900
      // circumvent the read-only check usually done for mem accesses
901
      // data is in host order, because that's what set_direct32 needs
902
      set_program32 (address, data);
903
    }
904
 
905
  return  err;
906
 
907
}       /* debug_set_mem () */
908
 
909
 
910
/*---------------------------------------------------------------------------*/
911
/*!See if an exception should be ignored
912
 
913
   @param[in] except  The exception to consider
914
 
915
   @return  Non-zero if the exception should be ignored                      */
916
/*---------------------------------------------------------------------------*/
917
int
918
debug_ignore_exception (unsigned long  except)
919
{
920
  int           result = 0;
921
  unsigned long dsr    = cpu_state.sprs[SPR_DSR];
922
 
923
  switch (except)
924
    {
925
    case EXCEPT_RESET:    result = (dsr & SPR_DSR_RSTE);  break;
926
    case EXCEPT_BUSERR:   result = (dsr & SPR_DSR_BUSEE); break;
927
    case EXCEPT_DPF:      result = (dsr & SPR_DSR_DPFE);  break;
928
    case EXCEPT_IPF:      result = (dsr & SPR_DSR_IPFE);  break;
929
    case EXCEPT_TICK:     result = (dsr & SPR_DSR_TTE);   break;
930
    case EXCEPT_ALIGN:    result = (dsr & SPR_DSR_AE);    break;
931
    case EXCEPT_ILLEGAL:  result = (dsr & SPR_DSR_IIE);   break;
932
    case EXCEPT_INT:      result = (dsr & SPR_DSR_IE);    break;
933
    case EXCEPT_DTLBMISS: result = (dsr & SPR_DSR_DME);   break;
934
    case EXCEPT_ITLBMISS: result = (dsr & SPR_DSR_IME);   break;
935
    case EXCEPT_RANGE:    result = (dsr & SPR_DSR_RE);    break;
936
    case EXCEPT_SYSCALL:  result = (dsr & SPR_DSR_SCE);   break;
937
    case EXCEPT_TRAP:     result = (dsr & SPR_DSR_TE);    break;
938
 
939
    default:                                              break;
940
    }
941
 
942
  cpu_state.sprs[SPR_DRR] |= result;
943
  set_stall_state (result != 0);
944
 
945
  /* Notify RSP if enabled. TODO: Should we actually notify ALL exceptions,
946
     not just those maked in the DSR? */
947
 
948
  if (config.debug.rsp_enabled && (0 != result))
949
    {
950
      rsp_exception (except);
951
    }
952
 
953
  return  (result != 0);
954
 
955
}       /* debug_ignore_exception () */
956
 
957
 
958
/*---------------------------------------------------------------------------*/
959
/*!Enable or disable the debug unit
960
 
961
   Set the corresponding field in the UPR
962
 
963
   @param[in] val  The value to use
964
   @param[in] dat  The config data structure (not used here)                 */
965
/*---------------------------------------------------------------------------*/
966
static void
967
debug_enabled (union param_val val, void *dat)
968
{
969
  if (val.int_val)
970
    {
971
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_DUP;
972
    }
973
  else
974
    {
975
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DUP;
976
    }
977
 
978
  config.debug.enabled = val.int_val;
979
 
980
}       /* debug_enabled() */
981
 
982
 
983
/*---------------------------------------------------------------------------*/
984
/*!Enable or disable Remote Serial Protocol GDB interface to the debug unit
985
 
986 235 jeremybenn
   This is the now the only interface.
987 19 jeremybenn
 
988
   @param[in] val  The value to use
989
   @param[in] dat  The config data structure (not used here)                 */
990
/*---------------------------------------------------------------------------*/
991
static void
992
debug_rsp_enabled (union param_val val, void *dat)
993
{
994
  config.debug.rsp_enabled = val.int_val;
995
 
996
}       /* debug_rsp_enabled () */
997
 
998
 
999
/*---------------------------------------------------------------------------*/
1000
/*!Set the Remote Serial Protocol GDB server port
1001
 
1002
   This is for use with the RSP, which is now the preferred interface.  Ensure
1003
   the value chosen is valid. Note that 0 is permitted, meaning the connection
1004
   should be to the "or1ksim-rsp" service, rather than a port.
1005
 
1006
   @param[in] val  The value to use
1007
   @param[in] dat  The config data structure (not used here)                 */
1008
/*---------------------------------------------------------------------------*/
1009
static void
1010
debug_rsp_port (union param_val val, void *dat)
1011
{
1012
  if ((val.int_val < 0) || (val.int_val > 65535))
1013
    {
1014
      fprintf (stderr, "Warning: invalid RSP GDB port specified: ignored\n");
1015
    }
1016
  else
1017
    {
1018
      config.debug.rsp_port = val.int_val;
1019
    }
1020
}       /* debug_rsp_port() */
1021
 
1022
 
1023
/*---------------------------------------------------------------------------*/
1024
/*!Set the VAPI ID for the debug unit
1025
 
1026
   @param[in] val  The value to use
1027
   @param[in] dat  The config data structure (not used here)                 */
1028
/*---------------------------------------------------------------------------*/
1029
static void
1030
debug_vapi_id (union param_val val, void *dat)
1031
{
1032
  config.debug.vapi_id = val.int_val;
1033
 
1034
}       /* debug_vapi_id () */
1035
 
1036
 
1037
/*---------------------------------------------------------------------------*/
1038
/*!Register the configuration functions for the debug unit                   */
1039
/*---------------------------------------------------------------------------*/
1040
void
1041
reg_debug_sec ()
1042
{
1043
  struct config_section *sec = reg_config_sec ("debug", NULL, NULL);
1044
 
1045 224 jeremybenn
  reg_config_param (sec, "enabled",     PARAMT_INT, debug_enabled);
1046
  reg_config_param (sec, "rsp_enabled", PARAMT_INT, debug_rsp_enabled);
1047
  reg_config_param (sec, "rsp_port",    PARAMT_INT, debug_rsp_port);
1048
  reg_config_param (sec, "vapi_id",     PARAMT_INT, debug_vapi_id);
1049 19 jeremybenn
 
1050
}       /* reg_debug_sec () */
1051
 

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