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1 82 jeremybenn
/* jtag.c -- JTAG modeling
2
 
3
   Copyright (C) 2008 Embecosm Limited
4
 
5
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
6
 
7
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
8
 
9
   This program is free software; you can redistribute it and/or modify it
10
   under the terms of the GNU General Public License as published by the Free
11
   Software Foundation; either version 3 of the License, or (at your option)
12
   any later version.
13
 
14
   This program is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17
   more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
21
 
22
/* This program is commented throughout in a fashion suitable for processing
23
   with Doxygen. */
24
 
25
 
26
/* Autoconf and/or portability configuration */
27
#include "config.h"
28
#include "port.h"
29
 
30
/* System includes */
31
#include <stdlib.h>
32
#include <unistd.h>
33
#include <stddef.h>
34
#include <stdint.h>
35
#include <string.h>
36
 
37
/* Package includes */
38
#include "sim-config.h"
39
#include "sprs.h"
40
#include "debug-unit.h"
41
#include "spr-defs.h"
42
#include "jtag.h"
43
#include "abstract.h"
44
#include "toplevel-support.h"
45
 
46
 
47
/*---------------------------------------------------------------------------*/
48
/*!Calculate an ongoing 32-bit CRC for a value
49
 
50
   Utility function. This is for a CRC, where the value is presented in normal
51
   order (i.e its most significant bit is at the most significant positions,
52
   it has not been reversed for incorporating ina JTAG register).
53
 
54
   The function can be used for values with more than 64 bits, but will treat
55
   the supplied value as the most-significant 64 bits, with all other bits
56
   zero. In practice this is only of use when shifting in a large number of
57
   zeros.
58
 
59
   The CRC used is the IEEE 802.3 32-bit CRC using the polynomial:
60
 
61
   x^32 + x^26 + x^23 +x^22 +x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 +
62
   x^4 + x^2 + x^1 + 1
63
 
64
   In this implementation, the CRC is initialized to all ones (outside this
65
   function), to catch leading zeros.
66
 
67
   The function is designed to be used in a continuing calculation if
68
   desired. It takes a partially computed CRC and shifts in the appropriate
69
   new bits for the value supplied. For a new calculation, this value should
70
   be 0xffffffff.
71
 
72
  @param[in] value     The number whose CRC is wanted (MSB first)
73
  @param[in] num_bits  The number of bits to use from value
74
  @param[in] crc_in    The value of the CRC computed so far
75
 
76
  @return  The updated CRC value                                             */
77
/*---------------------------------------------------------------------------*/
78
static uint32_t
79
crc32 (uint64_t  value,
80
       int       num_bits,
81
       uint32_t  crc_in)
82
{
83
  static const uint32_t  CRC32_POLY = 0x04c11db7;
84
 
85
  /* Incorporate the bits, MS bit first. */
86
  int  i;
87
 
88
  for (i = num_bits - 1; i >= 0; i--)
89
    {
90
      uint32_t  d = (1 == ((value >> i) & 1))   ? 0xfffffff : 0x0000000;
91
      uint32_t  t = (1 == ((crc_in >> 31) & 1)) ? 0xfffffff : 0x0000000;
92
 
93
      crc_in <<= 1;
94
      crc_in  ^= (d ^ t) & CRC32_POLY;
95
    }
96
 
97
  return  crc_in;
98
 
99
}       /* crc32 () */
100
 
101
 
102
/*---------------------------------------------------------------------------*/
103
/*!Reverse up to 64 bits in a word
104
 
105
   Utility function. Uses the "reverse" algorithm from the University of
106
   Kentucky Aggregate Magic Algorithms.
107
 
108
   @param[in] val      The long word to reverse
109
   @param[in] numBits  Number of bits to reverse
110
 
111
   @return  The reversed word.                                               */
112
/*---------------------------------------------------------------------------*/
113
static uint64_t
114
reverse_bits (uint64_t  val,
115
              int       numBits)
116
{
117
  val = (((val & 0xaaaaaaaaaaaaaaaaULL) >>  1) |
118
         ((val & 0x5555555555555555ULL) <<  1));
119
  val = (((val & 0xccccccccccccccccULL) >>  2) |
120
         ((val & 0x3333333333333333ULL) <<  2));
121
  val = (((val & 0xf0f0f0f0f0f0f0f0ULL) >>  4) |
122
         ((val & 0x0f0f0f0f0f0f0f0fULL) <<  4));
123
  val = (((val & 0xff00ff00ff00ff00ULL) >>  8) |
124
         ((val & 0x00ff00ff00ff00ffULL) <<  8));
125
  val = (((val & 0xffff0000ffff0000ULL) >> 16) |
126 98 jeremybenn
         ((val & 0x0000ffff0000ffffULL) << 16));
127 82 jeremybenn
  val = ((val >> 32) | (val << 32));
128
 
129
  return  val >> (64 - numBits);        /* Only the bits we want */
130
 
131
}       /* reverse_bits () */
132
 
133
 
134
/*---------------------------------------------------------------------------*/
135
/*!Reverse a byte
136
 
137
   Utility function. Uses the "reverse" algorithm from the University of
138
   Kentucky Aggregate Magic Algorithms.
139
 
140
   @param[in] byte  The byte to reverse
141
 
142
   @return  The reversed byte.                                               */
143
/*---------------------------------------------------------------------------*/
144
static uint8_t
145
reverse_byte (uint8_t  byte)
146
{
147
  byte = (((byte & 0xaa) >> 1) | ((byte & 0x55) << 1));
148
  byte = (((byte & 0xcc) >> 2) | ((byte & 0x33) << 2));
149
 
150
  return ((byte >> 4) | (byte << 4));
151
 
152
}       /* reverse_byte () */
153
 
154
 
155
/*---------------------------------------------------------------------------*/
156
/*!Construct a response register to shift out.
157
 
158
   The generic format is:
159
 
160
          +-------+--------+---------+---------+
161
          |       |        |         |         |
162
   TDI -> |  CRC  | Status |  XX..XX |  00..00 | -> TDO
163
          |       |        |         |         |
164
          +-------+--------+---------+---------+
165
              32       4    "ignored"   "zero"
166
             bits    bits      bits      bits
167
 
168
 
169
   Fields are always shifted in MS bit first, so must be reversed. The CRC is
170
   on the 4 status bits. Only the "zero" bits are zeroed. This allows for
171
   other fields to be specified in the "ignored" bits region, which are
172
   guaranteed to be left untouched.
173
 
174
   @param[out] jreg       The buffer for the constructed register
175
   @param[in]  status     The status bits
176
   @param[in]  crc_in     CRC computed so far (set to 0xffffffff if none)
177
   @param[in]  ign_bits   The number of bits to ignore
178 98 jeremybenn
   @param[in]  zero_bits  The number of bits to zero                         */
179 82 jeremybenn
/*---------------------------------------------------------------------------*/
180 98 jeremybenn
static void
181 82 jeremybenn
construct_response (unsigned char *jreg,
182
                    uint8_t        status,
183
                    uint32_t       crc_in,
184
                    unsigned int   ign_bits,
185
                    unsigned int   zero_bits)
186
{
187
  /* Construct the outgoing CRC */
188
  uint32_t  crc_out = crc32 (status, 4, crc_in);
189
 
190
  /* Reversed versions of fields ready for insertion */
191
  uint8_t   status_r  = reverse_bits (status, 4);
192
  uint32_t  crc_out_r = reverse_bits (crc_out, 32);
193
 
194
  /* Construct the response register */
195
  unsigned int  zero_bytes = zero_bits / 8;
196
  unsigned int  zero_off   = zero_bits % 8;
197
 
198
  /* Clear the zero bits */
199
  if (zero_bytes > 0)
200
    {
201
      memset (jreg, 0, zero_bytes);
202
    }
203
 
204
  jreg[zero_bytes] >>= zero_off;
205
  jreg[zero_bytes] <<= zero_off;
206
 
207
  /* Determine how much to skip in total */
208 97 jeremybenn
  unsigned int  skip_bytes = (ign_bits + zero_bits) / 8;
209
  unsigned int  bit_off    = (ign_bits + zero_bits) % 8;
210 82 jeremybenn
 
211
  /* Simplify by dealing separately with two cases:
212
     - the bit offset is less than or equal to 4, so the status goes in the
213
       first free byte, with some CRC.
214
     - the bit offset is greater than 4 but less than 8, so the status goes in
215
       the first and second free bytes.
216
 
217
     For completeness we deal with what should be the impossible case of
218
     bit_off > 7. */
219
  if (bit_off <= 4)
220
    {
221
      /* Note that this works even if bit_off == 4, since there will be no CRC
222
         remaining to OR into the first byte. */
223
      jreg[skip_bytes]     |=  ((status_r & 0xf) << bit_off) |
224
                              ((crc_out_r << (4 + bit_off)) & 0xff);
225
      jreg[skip_bytes + 1]  =  (crc_out_r >> ( 4 - bit_off)) & 0xff;
226
      jreg[skip_bytes + 2]  =  (crc_out_r >> (12 - bit_off)) & 0xff;
227
      jreg[skip_bytes + 3]  =  (crc_out_r >> (20 - bit_off)) & 0xff;
228
      jreg[skip_bytes + 4]  =  (crc_out_r >> (28 - bit_off)) & 0xff;
229
    }
230
  else if (bit_off < 8)
231
    {
232
      jreg[skip_bytes]     |=   status_r << bit_off;
233
      jreg[skip_bytes + 1]  =  (status_r >> (8 - bit_off)) |
234
                              ((crc_out_r << (bit_off - 4)) & 0xff);
235
      jreg[skip_bytes + 2]  =  (crc_out_r >> (12 - bit_off)) & 0xff;
236
      jreg[skip_bytes + 3]  =  (crc_out_r >> (20 - bit_off)) & 0xff;
237
      jreg[skip_bytes + 4]  =  (crc_out_r >> (28 - bit_off)) & 0xff;
238
      jreg[skip_bytes + 5]  =  (crc_out_r >> (36 - bit_off)) & 0xff;
239
    }
240
  else
241
    {
242
      fprintf (stderr, "*** ABORT ***: construct_response: impossible bit "
243 98 jeremybenn
               "offset: %u.\n", bit_off);
244 82 jeremybenn
      abort ();
245
    }
246
}       /* construct_response () */
247
 
248
 
249
/*---------------------------------------------------------------------------*/
250
/*!Select a module for debug
251
 
252
   Process a module selection register. The format is:
253
 
254
          +---------+-------+--------+---+
255
          |         |       |        |   |
256
   TDI -> | Ignored |  CRC  | Module | 1 | -> TDO
257
          |         |       |   ID   |   |
258
          +---------+-------+--------+---+
259
              36        32       4
260
             bits      bits    bits
261
 
262
   The returned register has the format:
263
 
264
          +-------+--------+---------+
265
          |       |        |         |
266
   TDI -> |  CRC  | Status |  00..00 | -> TDO
267
          |       |        |         |
268
          +-------+--------+---------+
269
              32       4        37
270
             bits    bits      bits
271
 
272
 
273
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
274
   is computed on the first 5 bits, the CRC out on the 4 status bits.
275
 
276 98 jeremybenn
   This is a register of a fixed size, which we verify initially.
277 82 jeremybenn
 
278 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
279
                            back out.
280
   @param[in]     num_bits  The number of bits supplied.
281
 
282 82 jeremybenn
   @return  The number of cycles the shift took, which in turn is the number
283
            of bits in the register                                          */
284
/*---------------------------------------------------------------------------*/
285 98 jeremybenn
static void
286
select_module (unsigned char *jreg,
287
               int            num_bits)
288 82 jeremybenn
{
289 98 jeremybenn
  /* Validate register size, which is fixed */
290
  const int  REG_BITS = 36 + 32 + 4 + 1;
291
 
292
  if (REG_BITS != num_bits)
293
    {
294
      fprintf (stderr,
295
               "ERROR: JTAG module select %d bits, when %d bits expected.\n",
296
              num_bits, REG_BITS);
297
      return;
298
    }
299
 
300 82 jeremybenn
  /* Break out the fields */
301
  uint8_t   mod_id = reverse_bits ((jreg[0] >> 1) & 0xf, 4);
302 97 jeremybenn
  uint32_t  crc_in = reverse_bits (((uint32_t ) (jreg[0] & 0xe0) >>  5) |
303 82 jeremybenn
                                   ((uint32_t )  jreg[1]         <<  3) |
304
                                   ((uint32_t )  jreg[2]         << 11) |
305
                                   ((uint32_t )  jreg[3]         << 19) |
306
                                   ((uint32_t ) (jreg[4] & 0x1f) << 27), 32);
307
 
308
  /* Compute the expected CRC */
309
  uint32_t  crc_computed;
310
 
311
  crc_computed = crc32 (1,      1, 0xffffffff);
312
  crc_computed = crc32 (mod_id, 4, crc_computed);
313
 
314
  /* Status flags */
315
  enum jtag_status  status = JS_OK;
316
 
317
  /* Validate the CRC */
318 98 jeremybenn
  if (crc_computed == crc_in)
319 82 jeremybenn
    {
320
      /* Is it a valid module? */
321
      switch (mod_id)
322
        {
323
        case JM_WISHBONE:
324
        case JM_CPU0:
325
        case JM_CPU1:
326
          /* All valid. Record the module */
327
          runtime.debug.mod_id = mod_id;
328
 
329
          break;
330
 
331
        default:
332 98 jeremybenn
          /* Bad module: record the error. Set the module to JM_UNDEFINED,
333
             which will trigger more errors in the future, rather than
334
             leaving the module unchanged, which might allow such errors to
335
             slip by undetected. */
336 82 jeremybenn
          status |= JS_MODULE_MISSING;
337 98 jeremybenn
          runtime.debug.mod_id = JM_UNDEFINED;
338 82 jeremybenn
          break;
339
        }
340
    }
341 98 jeremybenn
  else
342
    {
343
      /* CRC Mismatch: record the error */
344
      status |= JS_CRC_IN_ERROR;
345
    }
346 82 jeremybenn
 
347
  /* Construct the outgoing register and return the JTAG cycles taken (the
348
     register length) */
349
  return  construct_response (jreg, status, 0xffffffff, 0, 37);
350
 
351 98 jeremybenn
}       /* select_module */
352 82 jeremybenn
 
353
 
354
/*---------------------------------------------------------------------------*/
355
/*!Read WishBone data
356
 
357
   Read memory from WishBone. The WRITE_COMMAND address is updated to reflect
358
   the completed read if successful.
359
 
360 98 jeremybenn
   The data follows an initial 37 bits corresponding to the incoming command
361
   and CRC. We use the smaller of the data size in the original WRITE_COMMAND
362
   and the size of the data in the GO_COMMAND_WRITE packet, so we can handle
363
   over/under-run.
364
 
365 82 jeremybenn
   The result is the CRC of the data read. The status flag is supplied as a
366
   pointer, since this can also be updated if there is a problem reading the
367
   data.
368
 
369
   @note The size of the data is one greater than the length specified in the
370
         original WRITE_COMMAND.
371
 
372
   @todo For now we always read a byte a time. In the future, we ought to use
373
         16 and 32-bit accesses for greater efficiency.
374
 
375
   @todo  The algorithm for ensuring we only set the bits of interest in the
376
          register is inefficient. We should instead clear the whole area
377
          before starting.
378
 
379
   @param[out] jreg        The JTAG register buffer where data is to be
380
                           stored.
381 98 jeremybenn
   @param[in]  jreg_bytes   The number of bytes expected in the JTAG register
382
                           (may be different to that in the prior READ/WRITE
383
                           if we have over- or under-run).
384 82 jeremybenn
   @param[in]  status_ptr  Pointer to the status register.
385
 
386
   @return  The CRC of the data read                                         */
387
/*---------------------------------------------------------------------------*/
388
static uint32_t
389 98 jeremybenn
wishbone_read (unsigned char     *jreg,
390
               unsigned long int  jreg_bytes,
391
               enum jtag_status  *status_ptr)
392 82 jeremybenn
{
393 98 jeremybenn
  const unsigned int  BIT_OFF  = 37 % 8;        /* Skip initial fields */
394
  const unsigned int  BYTE_OFF = 37 / 8;
395 82 jeremybenn
 
396 98 jeremybenn
  /* Transfer each byte in turn, computing the CRC as we go. We must supply
397
     jreg_bytes. If there is overrun, we use zero for the remaining bytes. */
398
  uint32_t           crc_out  = 0xffffffff;
399
  unsigned long int  i;
400
 
401
  for (i = 0; i < jreg_bytes; i++)
402 82 jeremybenn
    {
403 98 jeremybenn
      unsigned char  byte = 0;
404 82 jeremybenn
 
405 98 jeremybenn
      /* Get a byte if available */
406
      if (i < runtime.debug.size)
407 82 jeremybenn
        {
408 98 jeremybenn
          /* Error if we can't access this byte */
409
          if (NULL == verify_memoryarea (runtime.debug.addr + i))
410
            {
411
              *status_ptr |= JS_WISHBONE_ERROR;
412
            }
413
          else
414
            {
415
              /* Get the data with no cache or VM translation */
416
              byte = eval_direct8 (runtime.debug.addr + i, 0, 0);
417
            }
418 82 jeremybenn
        }
419
 
420 98 jeremybenn
      /* Update the CRC, reverse, then store the byte in the register, without
421
         trampling adjacent bits. Simplified version when the bit offset is
422
         zero. */
423 82 jeremybenn
      crc_out = crc32 (byte, 8, crc_out);
424 98 jeremybenn
      byte    = reverse_byte (byte);
425 82 jeremybenn
 
426 98 jeremybenn
      /* Clear the bits (only) we are setting */
427
      jreg[BYTE_OFF + i]     <<= 8 - BIT_OFF;
428
      jreg[BYTE_OFF + i]     >>= 8 - BIT_OFF;
429
      jreg[BYTE_OFF + i + 1] >>= BIT_OFF;
430
      jreg[BYTE_OFF + i + 1] <<= BIT_OFF;
431 97 jeremybenn
 
432 98 jeremybenn
      /* OR in the bits */
433
      jreg[BYTE_OFF + i]     |= (byte <<      BIT_OFF)  & 0xff;
434
      jreg[BYTE_OFF + i + 1] |= (byte >> (8 - BIT_OFF)) & 0xff;
435
    }
436 82 jeremybenn
 
437 98 jeremybenn
  /* Only advance if there we no errors (including over/under-run. */
438
  if (JS_OK == *status_ptr)
439
    {
440
      runtime.debug.addr += runtime.debug.size;
441 82 jeremybenn
    }
442
 
443
  return  crc_out;
444
 
445
}       /* wishbone_read () */
446
 
447
 
448
/*---------------------------------------------------------------------------*/
449 98 jeremybenn
/*!Read SPR data
450 82 jeremybenn
 
451 98 jeremybenn
   Read memory from a SPR. The WRITE_COMMAND address is updated to reflect the
452
   completed read if successful.
453 82 jeremybenn
 
454 98 jeremybenn
   The data follows an initial 37 bits corresponding to the incoming command
455
   and CRC. We use the smaller of the data size in the original WRITE_COMMAND
456
   and the size of the data in the GO_COMMAND_WRITE packet, so we can handle
457
   over/under-run.
458 82 jeremybenn
 
459
   The result is the CRC of the data read.
460
 
461
   Unlike with Wishbone, there is no concept of any errors possible when
462
   reading an SPR.
463
 
464
   @todo The algorithm for ensuring we only set the bits of interest in the
465
         register is inefficient. We should instead clear the whole area
466
         before starting.
467
 
468
   @note The address is treated as a word address of the SPR.
469
 
470
   @note The debug unit is documented as being explicitly Big Endian. However
471
         that seems to be a poor basis for modeling, and more to do with the
472
         debug unit only ever being used with big-endian architectures. We
473
         transfer the bytes in the endianness of the OR1K.
474
 
475
   @param[out] jreg       The JTAG register buffer where data is to be stored.
476 98 jeremybenn
   @param[in]  jreg_bytes   The number of bytes expected in the JTAG register
477
                           (may be different to that in the prior READ/WRITE
478
                           if we have over- or under-run).
479
   @param[in]  status_ptr  Pointer to the status register.
480 82 jeremybenn
 
481
   @return  The CRC of the data read                                         */
482
/*---------------------------------------------------------------------------*/
483
static uint32_t
484 98 jeremybenn
spr_read (unsigned char     *jreg,
485
          unsigned long int  jreg_bytes,
486
          enum jtag_status  *status_ptr)
487 82 jeremybenn
{
488 98 jeremybenn
  const unsigned int  BIT_OFF  = 37 % 8;        /* Skip initial fields */
489
  const unsigned int  BYTE_OFF = 37 / 8;
490 82 jeremybenn
 
491 98 jeremybenn
  /* Store the SPR in the register, without trampling adjacent bits, computing
492
     the CRC as we go. We have to fill all the JTAG register bytes. If there
493
     is overrun, we pack in zeros. */
494
  uint32_t           spr      = mfspr (runtime.debug.addr);
495
  uint32_t           crc_out  = 0xffffffff;
496
  unsigned long int  i;
497 82 jeremybenn
 
498 98 jeremybenn
  for (i = 0; i < jreg_bytes; i++)
499 97 jeremybenn
    {
500 98 jeremybenn
      unsigned char  byte = 0;
501 97 jeremybenn
 
502 98 jeremybenn
      /* Get the byte from the SPR if available, otherwise use zero */
503
      if (i < 4)
504 82 jeremybenn
        {
505
#ifdef OR32_BIG_ENDIAN
506 98 jeremybenn
          byte = (spr >> 8 * i) & 0xff;
507 82 jeremybenn
#else /* !OR32_BIG_ENDIAN */
508 98 jeremybenn
          byte = (spr >> (24 - (8 * i))) & 0xff;
509 82 jeremybenn
#endif /* OR32_BIG_ENDIAN */
510
        }
511
 
512 98 jeremybenn
      /* Update the CRC */
513
      crc_out = crc32 (byte, 8, crc_out);
514
 
515
      /* Reverse, then store the byte in the register, without trampling
516
         adjacent bits. */
517
      byte = reverse_byte (byte);
518
 
519
      /* Clear the bits (only) we are setting */
520
      jreg[BYTE_OFF + i]     <<= 8 - BIT_OFF;
521
      jreg[BYTE_OFF + i]     >>= 8 - BIT_OFF;
522
      jreg[BYTE_OFF + i + 1] >>= BIT_OFF;
523
      jreg[BYTE_OFF + i + 1] <<= BIT_OFF;
524 82 jeremybenn
 
525 98 jeremybenn
      /* OR in the bits */
526
      jreg[BYTE_OFF + i]     |= (byte <<      BIT_OFF)  & 0xff;
527
      jreg[BYTE_OFF + i + 1] |= (byte >> (8 - BIT_OFF)) & 0xff;
528
    }
529 82 jeremybenn
 
530 98 jeremybenn
  /* Only advance if there we no errors (including over/under-run). */
531
  if (JS_OK == *status_ptr)
532
    {
533
      runtime.debug.addr++;
534 82 jeremybenn
    }
535
 
536
  return  crc_out;
537
 
538
}       /* spr_read () */
539
 
540
 
541
/*---------------------------------------------------------------------------*/
542 98 jeremybenn
/*!Set up null data.
543
 
544
   When there is an error in GO_COMMAND_READ, the data fields must be
545
   populated and the CRC set up, to ensure a correct return.
546
 
547
   The data follows an initial 37 bits corresponding to the incoming command
548
   and CRC. We use the smaller of the data size in the original WRITE_COMMAND
549
   and the size of the data in the GO_COMMAND_WRITE packet, so we can handle
550
   over/under-run.
551
 
552
   @param[out] jreg       The JTAG register buffer where data is to be stored.
553
   @param[in]  jreg_bytes   The number of bytes expected in the JTAG register
554
                           (may be different to that in the prior READ/WRITE
555
                           if we have over- or under-run).
556
 
557
   @return  The CRC of the data read                                         */
558
/*---------------------------------------------------------------------------*/
559
static uint32_t
560
null_read (unsigned char     *jreg,
561
           unsigned long int  jreg_bytes)
562
{
563
  const unsigned int  BIT_OFF  = 37 % 8;        /* Skip initial fields */
564
  const unsigned int  BYTE_OFF = 37 / 8;
565
 
566
  /* Store each null byte in turn, computing the CRC as we go */
567
  uint32_t           crc_out  = 0xffffffff;
568
  unsigned long int  i;
569
 
570
  for (i = 0; i < jreg_bytes; i++)
571
    {
572
      crc_out = crc32 (0, 8, crc_out);   /* Compute the CRC for null byte */
573
 
574
      /* Store null byte in the register, without trampling adjacent
575
         bits. */
576
      jreg[BYTE_OFF + i]     <<= 8 - BIT_OFF;
577
      jreg[BYTE_OFF + i]     >>= 8 - BIT_OFF;
578
      jreg[BYTE_OFF + i + 1] >>= BIT_OFF;
579
      jreg[BYTE_OFF + i + 1] <<= BIT_OFF;
580
    }
581
 
582
  return  crc_out;
583
 
584
}       /* null_read () */
585
 
586
 
587
/*---------------------------------------------------------------------------*/
588 82 jeremybenn
/*!Carry out a read from WishBone or SPR
589
 
590
   Process a GO_COMMAND register for read. The format is:
591
 
592
          +-------------+-------+---------+---+
593
          |             |       |    GO   |   |
594
   TDI -> |   Ignored   |  CRC  | COMMAND | 0 | -> TDO
595
          |             |       |  (0x0)  |   |
596
          +-------------+-------+---------+---+
597
           36 + 8 * size    32       4
598
               bits        bits    bits
599
 
600
   The returned register has the format:
601
 
602
          +-------+--------+------------+---------+
603
          |       |        |            |         |
604
   TDI -> |  CRC  | Status |    Data    |  00..00 | -> TDO
605
          |       |        |            |         |
606
          +-------+--------+------------+---------+
607
              32       4      8 * size       37
608
             bits    bits       bits        bits
609
 
610
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
611
   is computed on the first 5 bits, the CRC out on the 4 + 8 * size status and
612
   data bits.
613
 
614
   @note The size of the data is one greater than the length specified in the
615
         original WRITE_COMMAND.
616
 
617 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
618
                            back out.
619
   @param[in]     num_bits  The number of bits supplied.                     */
620 82 jeremybenn
/*---------------------------------------------------------------------------*/
621 98 jeremybenn
static void
622
go_command_read (unsigned char *jreg,
623
                 int            num_bits)
624 82 jeremybenn
{
625 98 jeremybenn
  /* Check the length is consistent with the prior WRITE_COMMAND. If not we
626
     have overrun or underrun and flag accordingly. */
627
  const int          REG_BITS = 36 + 8 * runtime.debug.size + 32 + 4 + 1;
628
  unsigned long int  jreg_bytes;
629
  enum jtag_status   status;
630
 
631
  if (REG_BITS == num_bits)
632
    {
633
      jreg_bytes = runtime.debug.size;
634
      status    = JS_OK;
635
    }
636
  else
637
    {
638
      /* Size will round down for safety */
639
      jreg_bytes = (runtime.debug.size * 8 + num_bits - REG_BITS) / 8;
640
      status    = JS_OVER_UNDERRUN;
641
    }
642
 
643 82 jeremybenn
  /* Break out the fields */
644
  uint32_t  crc_in   = reverse_bits (((uint32_t) (jreg[0] & 0xe0) >>  5) |
645
                                     ((uint32_t)  jreg[1]         <<  3) |
646
                                     ((uint32_t)  jreg[2]         << 11) |
647
                                     ((uint32_t)  jreg[3]         << 19) |
648
                                     ((uint32_t) (jreg[4] & 0x1f) << 27), 32);
649
 
650
  /* Compute the expected CRC */
651
  uint32_t  crc_computed;
652
 
653
  crc_computed = crc32 (0,                1, 0xffffffff);
654
  crc_computed = crc32 (JCMD_GO_COMMAND,  4, crc_computed);
655
 
656
  /* CRC to go out */
657 96 jeremybenn
  uint32_t  crc_out = 0;
658 82 jeremybenn
 
659
  /* Validate the CRC */
660
  if (crc_computed == crc_in)
661
    {
662 98 jeremybenn
      /* Read the data. Module errors will have been detected earlier, so we
663
         do nothing more here. */
664 82 jeremybenn
      switch (runtime.debug.mod_id)
665
        {
666
        case JM_WISHBONE:
667 98 jeremybenn
          crc_out = wishbone_read (jreg, jreg_bytes, &status);
668 82 jeremybenn
          break;
669
 
670
        case JM_CPU0:
671 98 jeremybenn
          crc_out = spr_read (jreg, jreg_bytes, &status);
672 82 jeremybenn
          break;
673
 
674
        default:
675 98 jeremybenn
          crc_out = null_read (jreg, jreg_bytes);
676 97 jeremybenn
          break;
677 82 jeremybenn
        }
678
    }
679
  else
680
    {
681
      /* Mismatch: record the error */
682
      status |= JS_CRC_IN_ERROR;
683
    }
684
 
685
  /* Construct the outgoing register, skipping the data read and returning the
686
     number of JTAG cycles taken (the register length). */
687 98 jeremybenn
  construct_response (jreg, status, crc_out, 8UL * jreg_bytes, 37);
688 82 jeremybenn
 
689
}       /* go_command_read () */
690
 
691
 
692
/*---------------------------------------------------------------------------*/
693
/*!Write WishBone data
694
 
695
   Write memory to WishBone. The WRITE_COMMAND address is updated to reflect
696
   the completed write if successful.
697
 
698 98 jeremybenn
   The data follows an initial 5 bits specifying the command. We use the
699
   smaller of the data size in the original WRITE_COMMAND and the size of the
700
   data in the GO_COMMAND_WRITE packet, so we can handle over/under-run.
701
 
702 82 jeremybenn
   @note The size of the data is one greater than the length specified in the
703
         original WRITE_COMMAND.
704
 
705
   @todo For now we always write a byte a time. In the future, we ought to use
706 98 jeremybenn
         16 and 32-bit accesses for greater efficiency and to correctly model
707
         the use of different access types.
708 82 jeremybenn
 
709 98 jeremybenn
   @param[in]  jreg        The JTAG register buffer where data is found.
710
   @param[in]  jreg_bytes   The number of bytes expected in the JTAG register
711
                           (may be different to that in the prior READ/WRITE
712
                           if we have over- or under-run).
713
   @param[out] status_ptr  Pointer to the status register.                   */
714 82 jeremybenn
/*---------------------------------------------------------------------------*/
715
static void
716 98 jeremybenn
wishbone_write (unsigned char     *jreg,
717
                unsigned long int  jreg_bytes,
718
                enum jtag_status  *status_ptr)
719 82 jeremybenn
{
720 98 jeremybenn
  const unsigned int  BIT_OFF  = 5;     /* Skip initial command */
721 82 jeremybenn
 
722 98 jeremybenn
  /* Transfer each byte in turn, computing the CRC as we go. We must supply
723
     jreg_bytes. If there is overrun, we ignore the remaining bytes. */
724
  unsigned long int  i;
725 82 jeremybenn
 
726 98 jeremybenn
  for (i = 0; i < jreg_bytes; i++)
727 82 jeremybenn
    {
728 98 jeremybenn
      /* Set a byte if available */
729
      if (i < runtime.debug.size)
730 82 jeremybenn
        {
731 98 jeremybenn
          /* Error if we can't access this byte */
732
          if (NULL == verify_memoryarea (runtime.debug.addr + i))
733
            {
734
              *status_ptr |= JS_WISHBONE_ERROR;
735
            }
736
          else
737
            {
738
              /* Extract the byte from the register, reverse it and write it,
739
                 circumventing the usual checks by pretending this is program
740
                 memory. */
741
              unsigned char  byte;
742 82 jeremybenn
 
743 98 jeremybenn
              byte = (jreg[i] >> BIT_OFF) | (jreg[i + 1] << (8 - BIT_OFF));
744
              byte = reverse_byte (byte);
745
 
746
              set_program8 (runtime.debug.addr + i, byte);
747
            }
748 82 jeremybenn
        }
749 98 jeremybenn
    }
750 82 jeremybenn
 
751 98 jeremybenn
  if (JS_OK == *status_ptr)
752
    {
753
      runtime.debug.addr += runtime.debug.size;
754 82 jeremybenn
    }
755
}       /* wishbone_write () */
756
 
757
 
758
/*---------------------------------------------------------------------------*/
759
/*!Write SPR data
760
 
761
   Write memory to WishBone. The WRITE_COMMAND address is updated to reflect
762
   the completed write if successful.
763
 
764 98 jeremybenn
   The data follows an initial 5 bits specifying the command. We use the
765
   smaller of the data size in the original WRITE_COMMAND and the size of the
766
   data in the GO_COMMAND_WRITE packet, so we can handle over/under-run.
767
 
768 82 jeremybenn
   Unlike with Wishbone, there is no concept of any errors possible when
769 98 jeremybenn
   writing an SPR.
770 82 jeremybenn
 
771
   @todo The algorithm for ensuring we only set the bits of interest in the
772
         register is inefficient. We should instead clear the whole area
773
         before starting.
774
 
775
   @note The address is treated as a word address of the SPR.
776
 
777
   @note The debug unit is documented as being explicitly Big Endian. However
778
         that seems to be a poor basis for modeling, and more to do with the
779
         debug unit only ever being used with big-endian architectures. We
780
         transfer the bytes in the endianness of the OR1K.
781
 
782
   @param[out] jreg       The JTAG register buffer where data is to be stored.
783 98 jeremybenn
   @param[in]  jreg_bytes   The number of bytes expected in the JTAG register
784
                           (may be different to that in the prior READ/WRITE
785
                           if we have over- or under-run).
786
   @param[out] status_ptr  Pointer to the status register.                   */
787 82 jeremybenn
/*---------------------------------------------------------------------------*/
788
static void
789 98 jeremybenn
spr_write (unsigned char     *jreg,
790
           unsigned long int  jreg_bytes,
791
           enum jtag_status  *status_ptr)
792 82 jeremybenn
{
793 98 jeremybenn
  const unsigned int  BIT_OFF  = 5;     /* Skip initial command */
794 82 jeremybenn
 
795 98 jeremybenn
  /* Construct the SPR value one byte at a time. If there is overrun, ignore
796
     the excess bytes. */
797
  uint32_t           spr = 0;
798
  unsigned long int  i;
799 82 jeremybenn
 
800 98 jeremybenn
  for (i = 0; i < jreg_bytes; i++)
801 82 jeremybenn
    {
802 98 jeremybenn
      if (i < 4)
803 82 jeremybenn
        {
804 98 jeremybenn
          uint8_t byte;
805 82 jeremybenn
 
806 98 jeremybenn
          byte = (jreg[i] >> BIT_OFF) | (jreg[i + 1] << (8 - BIT_OFF));
807
          byte = reverse_byte (byte);
808
 
809 82 jeremybenn
#ifdef OR32_BIG_ENDIAN
810 98 jeremybenn
          spr |= ((uint32_t) (byte)) << (8 * i);
811 82 jeremybenn
#else /* !OR32_BIG_ENDIAN */
812 98 jeremybenn
          spr |= ((uint32_t) (byte)) << (24 - (8 * i));
813 82 jeremybenn
#endif /* OR32_BIG_ENDIAN */
814 98 jeremybenn
        }
815 82 jeremybenn
    }
816
 
817
  /* Transfer the SPR */
818
  mtspr (runtime.debug.addr, spr);
819
 
820 98 jeremybenn
  /* Only advance if there we no errors (including over/under-run). */
821
  if (JS_OK == *status_ptr)
822
    {
823
      runtime.debug.addr++;
824
    }
825 82 jeremybenn
}       /* spr_write () */
826
 
827
 
828
/*---------------------------------------------------------------------------*/
829
/*!Carry out a write to WishBone or SPR
830
 
831
   Process a GO_COMMAND register for write. The format is:
832
 
833
          +-------------+-------+------------+---------+---+
834
          |             |       |            |    GO   |   |
835
   TDI -> |   Ignored   |  CRC  |    Data    | COMMAND | 0 | -> TDO
836
          |             |       |            |  (0x0)  |   |
837
          +-------------+-------+------------+---------+---+
838
                36          32     8 * size       4
839
               bits        bits      bits       bits
840
 
841
   The returned register has the format:
842
 
843
          +-------+--------+-------------+
844
          |       |        |             |
845
   TDI -> |  CRC  | Status |  00......00 | -> TDO
846
          |       |        |             |
847
          +-------+--------+-------------+
848
              32       4    8 * size + 37
849
             bits    bits        bits
850
 
851
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
852
   is computed on the first 5 + 8 * size bits, the CRC out on the 4 status
853
   bits.
854
 
855
   @note The size of the data is one greater than the length specified in the
856
         original WRITE_COMMAND.
857
 
858
   @todo The rules say we look for errors in the WRITE_COMMAND spec
859
         here. However it would be better to do that at WRITE_COMMAND time and
860
         save the result for here, to avoid using duff data.
861
 
862 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
863
                            back out.
864
   @param[in]     num_bits  The number of bits supplied.                     */
865 82 jeremybenn
/*---------------------------------------------------------------------------*/
866 98 jeremybenn
static void
867
go_command_write (unsigned char *jreg,
868
                  int            num_bits)
869 82 jeremybenn
{
870 98 jeremybenn
  /* Check the length is consistent with the prior WRITE_COMMAND. If not we
871
     have overrun or underrun and flag accordingly. */
872
  const int          REG_BITS = 36 + 32 + 8 * runtime.debug.size + 4 + 1;
873
  unsigned long int  real_size;
874
  enum jtag_status   status;
875
 
876
  if (REG_BITS == num_bits)
877
    {
878
      real_size = runtime.debug.size;
879
      status    = JS_OK;
880
    }
881
  else
882
    {
883
      /* Size will round down for safety */
884
      real_size = (runtime.debug.size * 8UL + num_bits - REG_BITS) / 8UL;
885
      status    = JS_OVER_UNDERRUN;
886
    }
887
 
888 82 jeremybenn
  /* Break out the fields */
889
  uint32_t  crc_in =
890 98 jeremybenn
    reverse_bits (((uint32_t) (jreg[real_size + 0] & 0xe0) >>  5) |
891
                  ((uint32_t)  jreg[real_size + 1]         <<  3) |
892
                  ((uint32_t)  jreg[real_size + 2]         << 11) |
893
                  ((uint32_t)  jreg[real_size + 3]         << 19) |
894
                  ((uint32_t) (jreg[real_size + 4] & 0x1f) << 27),
895 82 jeremybenn
                  32);
896
 
897
  /* Compute the expected CRC */
898
  uint32_t  crc_computed;
899
 
900
  crc_computed = crc32 (0,                1, 0xffffffff);
901
  crc_computed = crc32 (JCMD_GO_COMMAND,  4, crc_computed);
902
 
903 98 jeremybenn
  unsigned long int  i;
904 82 jeremybenn
 
905 98 jeremybenn
  for (i = 0; i < real_size; i++)
906 82 jeremybenn
    {
907 97 jeremybenn
      uint8_t  byte = reverse_bits (((jreg[i] & 0xe0) >> 5) |
908
                      ((jreg[i + 1] & 0x1f) << 3), 8);
909 82 jeremybenn
      crc_computed = crc32 (byte, 8, crc_computed);
910
    }
911
 
912
  /* Validate the CRC */
913
  if (crc_computed == crc_in)
914
    {
915 98 jeremybenn
      /* Write the data. Module errors will have been detected earlier, so we
916
         do nothing more here. */
917 82 jeremybenn
      switch (runtime.debug.mod_id)
918
        {
919
        case JM_WISHBONE:
920 98 jeremybenn
          wishbone_write (jreg, real_size, &status);
921 82 jeremybenn
          break;
922
 
923
        case JM_CPU0:
924 98 jeremybenn
          spr_write (jreg, real_size, &status);
925 82 jeremybenn
          break;
926 98 jeremybenn
 
927 82 jeremybenn
        default:
928 97 jeremybenn
          break;
929 82 jeremybenn
        }
930
    }
931
  else
932
    {
933
      /* Mismatch: record the error */
934
      status |= JS_CRC_IN_ERROR;
935
    }
936
 
937
  /* Construct the outgoing register, skipping the data read and returning the
938
     number of JTAG cycles taken (the register length). */
939 98 jeremybenn
  construct_response (jreg, status, 0xffffffff, 0, 37UL + 8UL * real_size);
940 82 jeremybenn
 
941
}       /* go_command_write () */
942
 
943
 
944
/*---------------------------------------------------------------------------*/
945
/*!Invoke the action specified by a prior WRITE_COMMAND register
946
 
947
   Process a GO_COMMAND register.
948
 
949
   How this is handled depends on whether a previous WRITE_COMMAND has
950
   selected a read access type or a write access type has been selected.
951
 
952
   This function breaks this out.
953
 
954 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
955
                            back out.
956
   @param[in]     num_bits  The number of bits supplied.                     */
957 82 jeremybenn
/*---------------------------------------------------------------------------*/
958 98 jeremybenn
static void
959
go_command (unsigned char *jreg,
960
            int            num_bits)
961 82 jeremybenn
{
962
  /* Have we even had a WRITE_COMMAND? */
963
  if (!runtime.debug.write_defined_p)
964
    {
965 98 jeremybenn
      memset (jreg, 0, (num_bits + 7) / 8);
966
      fprintf (stderr, "ERROR: JTAG GO_COMMAND with no prior WRITE_COMMAND.\n");
967
      return;
968 82 jeremybenn
    }
969
 
970 98 jeremybenn
  /* Whether to read or write depends on the access type. We don't put an
971
     error message if it's invalid here - we rely on the prior WRITE_COMMAND
972
     to do that. We just silently ignore. */
973 82 jeremybenn
  switch (runtime.debug.acc_type)
974
    {
975
    case JAT_WRITE8:
976
    case JAT_WRITE16:
977
    case JAT_WRITE32:
978 98 jeremybenn
      go_command_write (jreg, num_bits);
979
      break;
980 82 jeremybenn
 
981
    case JAT_READ8:
982
    case JAT_READ16:
983
    case JAT_READ32:
984 98 jeremybenn
      go_command_read (jreg, num_bits);
985
      break;
986 82 jeremybenn
 
987
    default:
988 98 jeremybenn
      break;
989 82 jeremybenn
    }
990
}       /* go_command () */
991
 
992
 
993
/*---------------------------------------------------------------------------*/
994
/*!Read a previouse WRITE_COMMAND register
995
 
996
   Process a READ_COMMAND register. The format is:
997
 
998
          +---------+-------+---------+---+
999
          |         |       |   READ  |   |
1000
   TDI -> | Ignored |  CRC  | COMMAND | 0 | -> TDO
1001
          |         |       |  (0x1)  |   |
1002
          +---------+-------+---------+---+
1003
              88        32       4
1004
             bits      bits    bits
1005
 
1006
   The returned register has the format:
1007
 
1008
          +-------+--------+--------+---------+--------+---------+
1009
          |       |        |        |         |        |         |
1010
   TDI -> |  CRC  | Status | Length | Address | Access |  00..00 | -> TDO
1011
          |       |        |        |         |  Type  |         |
1012
          +-------+--------+--------+---------+--------+---------+
1013
              32       4       16        32        4        37
1014
             bits    bits     bits      bits     bits      bits
1015
 
1016
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
1017
   is computed on the first 5 bits, the CRC out on the 56 status, length,
1018
   address and access type bits.
1019
 
1020 98 jeremybenn
   This is a register of a fixed size, which we verify initially.
1021 82 jeremybenn
 
1022 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
1023
                            back out.
1024
   @param[in]     num_bits  The number of bits supplied.                     */
1025 82 jeremybenn
/*---------------------------------------------------------------------------*/
1026 98 jeremybenn
static void
1027
read_command (unsigned char *jreg,
1028
              int            num_bits)
1029 82 jeremybenn
{
1030 98 jeremybenn
  /* Validate register size, which is fixed */
1031
  const int  REG_BITS = 88 + 32 + 4 + 1;
1032
 
1033
  if (REG_BITS != num_bits)
1034
    {
1035
      fprintf (stderr,
1036
               "ERROR: JTAG READ_COMMAND %d bits, when %d bits expected.\n",
1037
               num_bits, REG_BITS);
1038
      return;
1039
    }
1040
 
1041 82 jeremybenn
  /* Break out the fields */
1042
  uint32_t  crc_in   = reverse_bits (((uint32_t) (jreg[0] & 0xe0) >>  5) |
1043
                                     ((uint32_t)  jreg[1]         <<  3) |
1044
                                     ((uint32_t)  jreg[2]         << 11) |
1045
                                     ((uint32_t)  jreg[3]         << 19) |
1046
                                     ((uint32_t) (jreg[4] & 0x1f) << 27), 32);
1047
 
1048
  /* Compute the expected CRC */
1049
  uint32_t  crc_computed;
1050
 
1051
  crc_computed = crc32 (0,                   1, 0xffffffff);
1052
  crc_computed = crc32 (JCMD_READ_COMMAND,  4, crc_computed);
1053
 
1054
  /* CRC to go out */
1055
  uint32_t  crc_out = 0xffffffff;
1056
 
1057
  /* Status flags */
1058
  enum jtag_status  status = JS_OK;
1059
 
1060 98 jeremybenn
  /* Only do anything with this if the CRC's match */
1061
  if (crc_computed == crc_in)
1062 82 jeremybenn
    {
1063 98 jeremybenn
      /* If we haven't had a previous WRITE_COMMAND, then we return empty
1064
         data. There is no valid status flag we can use, but we print a rude
1065
         message. */
1066
      uint8_t   acc_type;
1067
      uint32_t  addr;
1068
      uint16_t  len;
1069
 
1070
      if (runtime.debug.write_defined_p)
1071
        {
1072
          acc_type = runtime.debug.acc_type;
1073
          addr     = runtime.debug.addr;
1074
          len      = runtime.debug.size - 1;
1075
        }
1076
      else
1077
        {
1078
          fprintf (stderr, "ERROR: JTAG READ_COMMAND finds no data.\n");
1079
 
1080
          acc_type = 0;
1081
          addr     = 0;
1082
          len      = 0;
1083
        }
1084
 
1085
      /* Compute the CRC */
1086
      crc_out = crc32 (acc_type,  4, crc_out);
1087
      crc_out = crc32 (addr,     32, crc_out);
1088
      crc_out = crc32 (len,      16, crc_out);
1089
 
1090
      /* Reverse the bit fields */
1091
      acc_type = reverse_bits (acc_type,  4);
1092
      addr     = reverse_bits (addr,     32);
1093
      len      = reverse_bits (len,      16);
1094
 
1095
      /* Construct the outgoing register. */
1096
      jreg[ 4] |= (acc_type <<  5) & 0xe0;
1097
      jreg[ 5] |= (acc_type >>  3) & 0x01;
1098
      jreg[ 5] |= (addr     <<  1) & 0xfe;
1099
      jreg[ 6] |= (addr     >>  7) & 0xff;
1100
      jreg[ 7] |= (addr     >> 15) & 0xff;
1101
      jreg[ 8] |= (addr     >> 23) & 0xff;
1102
      jreg[ 9] |= (addr     >> 31) & 0x01;
1103
      jreg[ 9] |= (len      <<  1) & 0xfe;
1104
      jreg[10] |= (len      >>  7) & 0xff;
1105
      jreg[11] |= (len      >> 15) & 0x01;
1106
    }
1107
  else
1108
    {
1109
      /* CRC Mismatch: record the error */
1110 82 jeremybenn
      status |= JS_CRC_IN_ERROR;
1111
    }
1112 97 jeremybenn
 
1113 98 jeremybenn
  /* Construct the final response with the status, skipping the fields we've
1114
     just written. */
1115
  return  construct_response (jreg, status, crc_out, 52, 37);
1116 97 jeremybenn
 
1117 98 jeremybenn
}       /* read_command () */
1118
 
1119
 
1120
/*---------------------------------------------------------------------------*/
1121
/*!Validate WRITE_COMMAND fields for WishBone
1122
 
1123
   Check that a WRITE_COMMAND's fields are valid for WishBone access.
1124
 
1125
   - 16 and 32-bit access must be correctly aligned.
1126
 
1127
   - size must be a multiple of 2 for 16-bit access, and a multiple of 4 for
1128
     32-bit access.
1129
 
1130
   Error messages are printed to explain any validation problems.
1131
 
1132
   @todo Should multiple SPR accesses be allowed in a single access?
1133
 
1134
   @note The size of the data is one greater than the length specified in the
1135
         original WRITE_COMMAND.
1136
 
1137
   @param[in] acc_type  The access type field
1138
   @param[in] addr      The address field
1139
   @param[in] size      The number of bytes to transfer (field is 1 less than
1140
                        this).
1141
 
1142
   @return  1 (TRUE) if validation is OK, 0 (FALSE) if validation fails.     */
1143
/*---------------------------------------------------------------------------*/
1144
static int
1145
validate_wb_fields (unsigned char      acc_type,
1146
                    unsigned long int  addr,
1147
                    unsigned long int  size)
1148
{
1149
  int  res_p = 1;                       /* Result */
1150
 
1151
  /* Determine the size of the access */
1152
  uint32_t  access_bytes = 1;
1153
 
1154
  switch (acc_type)
1155 82 jeremybenn
    {
1156 98 jeremybenn
    case JAT_WRITE8:
1157
    case JAT_READ8:
1158
      access_bytes = 1;
1159
      break;
1160 82 jeremybenn
 
1161 98 jeremybenn
    case JAT_WRITE16:
1162
    case JAT_READ16:
1163
      access_bytes = 2;
1164
      break;
1165
 
1166
    case JAT_WRITE32:
1167
    case JAT_READ32:
1168
      access_bytes = 4;
1169
      break;
1170
 
1171
    default:
1172
      fprintf (stderr, "ERROR: JTAG WRITE_COMMAND unknown access type %u.\n",
1173
               acc_type);
1174
      res_p = 0;
1175
      break;
1176 82 jeremybenn
    }
1177 98 jeremybenn
 
1178
  /* Check for alignment. This works for 8-bit and undefined access type,
1179
     although the tests will always pass. */
1180
 
1181
  if (0 != (addr % access_bytes))
1182 82 jeremybenn
    {
1183 98 jeremybenn
      fprintf (stderr, "ERROR: JTAG WishBone %d-bit access must be %d-byte "
1184
               "aligned.\n", access_bytes * 8, access_bytes);
1185
      res_p = 0;
1186
    }
1187 97 jeremybenn
 
1188 98 jeremybenn
  /* Check byte length is multiple of access width */
1189
  if (0 != (size % access_bytes))
1190
    {
1191
      fprintf (stderr, "ERROR: JTAG %d-bit WishBone access must be multiple "
1192
               "of %d bytes in length.\n", access_bytes * 8, access_bytes);
1193
      res_p = 0;
1194
    }
1195 97 jeremybenn
 
1196 98 jeremybenn
  return  res_p;
1197
 
1198
}       /* validate_wb_fields () */
1199
 
1200
 
1201
/*---------------------------------------------------------------------------*/
1202
/*!Validate WRITE_COMMAND fields for SPR
1203
 
1204
   Check that a WRITE_COMMAND's fields are valid for SPR access. Only prints
1205
   messages, since the protocol does not allow for any errors.
1206
 
1207
   - 8 and 16-bit access is not permitted.
1208
 
1209
   - size must be 4 bytes (1 word). Any other value is an error.
1210
 
1211
   - address must be less than MAX_SPRS. If a larger value is specified, it
1212
     will be reduced module MAX_SPRS (which is hopefully a power of 2). This
1213
     is only a warning, not an error.
1214
 
1215
   Error/warning messages are printed to explain any validation problems.
1216
 
1217
   @todo Should multiple SPR accesses be allowed in a single access?
1218
 
1219
   @note The size of the data is one greater than the length specified in the
1220
         original WRITE_COMMAND.
1221
 
1222
   @param[in] acc_type  The access type field
1223
   @param[in] addr      The address field
1224
   @param[in] size      The number of bytes to transfer (field is 1 less than
1225
                        this).
1226
 
1227
   @return  1 (TRUE) if we could validate (even if addr needs truncating),
1228
 
1229
/*---------------------------------------------------------------------------*/
1230
static int
1231
validate_spr_fields (unsigned char      acc_type,
1232
                     unsigned long int  addr,
1233
                     unsigned long int  size)
1234
{
1235
  int  res_p = 1;                       /* Result */
1236
 
1237
  /* Determine the size and direction of the access */
1238
  switch (acc_type)
1239
    {
1240
    case JAT_WRITE8:
1241
    case JAT_READ8:
1242
      fprintf (stderr, "ERROR: JTAG 8-bit access for SPR not supported.\n");
1243
      res_p = 0;
1244
      break;
1245
 
1246
    case JAT_WRITE16:
1247
    case JAT_READ16:
1248
      fprintf (stderr, "ERROR: JTAG 16-bit access for SPR not supported.\n");
1249
      res_p = 0;
1250
      break;
1251
 
1252
    case JAT_WRITE32:
1253
    case JAT_READ32:
1254
      break;
1255
 
1256
    default:
1257
      fprintf (stderr, "ERROR: unknown JTAG SPR access type %u.\n",
1258
               acc_type);
1259
      res_p = 0;
1260
      break;
1261 82 jeremybenn
    }
1262
 
1263 98 jeremybenn
  /* Validate access size */
1264
  if (4 != size)
1265
    {
1266
      fprintf (stderr, "ERROR: JTAG SPR access 0x%lx bytes not supported.\n",
1267
               size);
1268
      res_p = 0;
1269
    }
1270 97 jeremybenn
 
1271 98 jeremybenn
  /* Validate address. This will be truncated if wrong, so not an error. */
1272
  if (addr >= MAX_SPRS)
1273
    {
1274
      fprintf (stderr, "Warning: truncated JTAG SPR address 0x%08lx.\n",
1275
               addr);
1276
    }
1277 82 jeremybenn
 
1278 98 jeremybenn
  return  res_p;                        /* Success */
1279 82 jeremybenn
 
1280 98 jeremybenn
}       /* validate_spr_fields () */
1281 82 jeremybenn
 
1282 98 jeremybenn
 
1283 82 jeremybenn
/*---------------------------------------------------------------------------*/
1284 98 jeremybenn
/*!Specify details for a subsequent GO_COMMAND
1285 82 jeremybenn
 
1286
   Process a WRITE_COMMAND register. The format is:
1287
 
1288
          +---------+-------+--------+---------+--------+---------+---+
1289
          |         |       |        |         |        |  WRITE  |   |
1290
   TDI -> | Ignored |  CRC  | Length | Address | Access | COMMAND | 0 | -> TDO
1291
          |         |       |        |         |  Type  |  (0x2)  |   |
1292
          +---------+-------+--------+---------+--------+---------+---+
1293
              36        32      16        32        4         4
1294
             bits      bits    bits      bits     bits      bits
1295
 
1296
   The returned register has the format:
1297
 
1298
          +-------+--------+---------+
1299
          |       |        |         |
1300
   TDI -> |  CRC  | Status |  00..00 | -> TDO
1301
          |       |        |         |
1302
          +-------+--------+---------+
1303
              32       4        89
1304
             bits    bits      bits
1305
 
1306
 
1307
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
1308
   is computed on the first 57 bits, the CRC out on the 4 status bits.
1309
 
1310 98 jeremybenn
   There are no bits for reporting bit specification errors other than CRC
1311
   mismatch. The subsequent GO_COMMAND will report an error in reading from
1312
   Wishbone or over/under-run. We report any inconsistencies here with warning
1313
   messages, correcting them if possible.
1314 82 jeremybenn
 
1315 98 jeremybenn
   All errors invalidate any prior data. This will ensure any subsequent usage
1316
   continues to trigger faults, rather than a failed WRITE_COMMAND being
1317
   missed.
1318
 
1319
   This is a register of a fixed size, which we verify initially.
1320
 
1321
   @param[in,out] jreg      The register to shift in, and the register shifted
1322
                            back out.
1323
   @param[in]     num_bits  The number of bits supplied.                     */
1324 82 jeremybenn
/*---------------------------------------------------------------------------*/
1325 98 jeremybenn
static void
1326
write_command (unsigned char *jreg,
1327
               int            num_bits)
1328 82 jeremybenn
{
1329 98 jeremybenn
  /* Validate register size, which is fixed */
1330
  const int  REG_BITS = 36 + 32 +16 + 32 + 4 + 4 + 1;
1331
 
1332
  if (REG_BITS != num_bits)
1333
    {
1334
      runtime.debug.write_defined_p = 0;
1335
      fprintf (stderr,
1336
               "ERROR: JTAG WRITE_COMMAND %d bits, when %d bits expected.\n",
1337
               num_bits, REG_BITS);
1338
      return;
1339
    }
1340
 
1341 82 jeremybenn
  /* Break out the fields */
1342 97 jeremybenn
  uint8_t   acc_type = reverse_bits (((jreg[0] & 0xe0) >> 5) |
1343
                                     ((jreg[1] & 0x01) << 3) , 4);
1344 82 jeremybenn
  uint32_t  addr     = reverse_bits (((uint32_t) (jreg[ 1] & 0xfe) >>  1) |
1345
                                     ((uint32_t)  jreg[ 2]         <<  7) |
1346
                                     ((uint32_t)  jreg[ 3]         << 15) |
1347
                                     ((uint32_t)  jreg[ 4]         << 23) |
1348
                                     ((uint32_t) (jreg[ 5] & 0x01) << 31), 32);
1349
  uint16_t  len      = reverse_bits (((uint32_t) (jreg[ 5] & 0xfe) >>  1) |
1350
                                     ((uint32_t)  jreg[ 6]         <<  7) |
1351
                                     ((uint32_t) (jreg[ 7] & 0x01) << 15), 16);
1352
  uint32_t  crc_in   = reverse_bits (((uint32_t) (jreg[ 7] & 0xfe) >>  1) |
1353
                                     ((uint32_t)  jreg[ 8]         <<  7) |
1354
                                     ((uint32_t)  jreg[ 9]         << 15) |
1355
                                     ((uint32_t)  jreg[10]         << 23) |
1356
                                     ((uint32_t) (jreg[11] & 0x01) << 31), 32);
1357
 
1358
  /* Compute the expected CRC */
1359
  uint32_t  crc_computed;
1360
 
1361
  crc_computed = crc32 (0,                   1, 0xffffffff);
1362
  crc_computed = crc32 (JCMD_WRITE_COMMAND,  4, crc_computed);
1363
  crc_computed = crc32 (acc_type,            4, crc_computed);
1364
  crc_computed = crc32 (addr,               32, crc_computed);
1365
  crc_computed = crc32 (len,                16, crc_computed);
1366
 
1367
  /* Status flags */
1368
  enum jtag_status  status = JS_OK;
1369
 
1370 98 jeremybenn
  /* We only do anything with this packet if the CRC's match */
1371
  if (crc_computed == crc_in)
1372 82 jeremybenn
    {
1373 98 jeremybenn
      unsigned long int  data_size = (unsigned long int) len + 1UL;
1374
 
1375
      switch (runtime.debug.mod_id)
1376
        {
1377
        case JM_WISHBONE:
1378
 
1379
          if (validate_wb_fields (acc_type, addr, data_size))
1380
            {
1381
              runtime.debug.write_defined_p = 1;
1382
              runtime.debug.acc_type        = acc_type;
1383
              runtime.debug.addr            = addr;
1384
              runtime.debug.size            = data_size;
1385
            }
1386
          else
1387
            {
1388
              runtime.debug.write_defined_p = 0;
1389
            }
1390
 
1391
          break;
1392
 
1393
        case JM_CPU0:
1394
 
1395
          /* Oversize addresses are permitted, but cause a validation warning
1396
             and are truncated here. */
1397
          if (validate_spr_fields (acc_type, addr, data_size))
1398
            {
1399
              runtime.debug.write_defined_p = 1;
1400
              runtime.debug.acc_type        = acc_type;
1401
              runtime.debug.addr            = addr % MAX_SPRS;
1402
              runtime.debug.size            = data_size;
1403
            }
1404
          else
1405
            {
1406
              runtime.debug.write_defined_p = 0;
1407
            }
1408
 
1409
          break;
1410
 
1411
        case JM_CPU1:
1412
 
1413
          runtime.debug.write_defined_p = 0;
1414
          fprintf (stderr,
1415
                   "ERROR: JTAG WRITE_COMMAND for CPU1 not supported.\n");
1416
          break;
1417
 
1418
        case JM_UNDEFINED:
1419
 
1420
          runtime.debug.write_defined_p = 0;
1421
          fprintf (stderr,
1422
                   "ERROR: JTAG WRITE_COMMAND with no module selected.\n");
1423
          break;
1424
 
1425
        default:
1426
 
1427
          /* All other modules will have triggered an error on selection. */
1428
          runtime.debug.write_defined_p = 0;
1429
          break;
1430
        }
1431 82 jeremybenn
    }
1432
  else
1433
    {
1434 98 jeremybenn
      /* CRC Mismatch: record the error */
1435
      runtime.debug.write_defined_p  = 0;
1436
      status                        |= JS_CRC_IN_ERROR;
1437 82 jeremybenn
    }
1438
 
1439 98 jeremybenn
 
1440
  /* Construct the outgoing register */
1441
  construct_response (jreg, status, 0xffffffff, 0, 89);
1442
 
1443 82 jeremybenn
}       /* write_command () */
1444
 
1445
 
1446
/*---------------------------------------------------------------------------*/
1447
/*!Read the control bits from a CPU.
1448
 
1449
   Process a READ_CONTROL register. The format is:
1450
 
1451
          +---------+-------+---------+---+
1452
          |         |       |  READ   |   |
1453
   TDI -> | Ignored |  CRC  | CONTROL | 0 | -> TDO
1454
          |         |       |  (0x3)  |   |
1455
          +---------+-------+---------+---+
1456 98 jeremybenn
              88        32       4
1457 82 jeremybenn
             bits      bits    bits
1458
 
1459
   The returned register has the format:
1460
 
1461
          +-------+--------+--------+---------+
1462
          |       |        |        |         |
1463
   TDI -> |  CRC  | Status |  Data  |  00..00 | -> TDO
1464
          |       |        |        |         |
1465
          +-------+--------+--------+---------+
1466
              32       4       52        37
1467
             bits    bits     bits      bits
1468
 
1469
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
1470
   is computed on the first 57 bits, the CRC out on the 4 status bits.
1471
 
1472 98 jeremybenn
   This is a register of a fixed size, which we verify initially.
1473 82 jeremybenn
 
1474 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
1475
                            back out.
1476
   @param[in]     num_bits  The number of bits supplied.                     */
1477 82 jeremybenn
/*---------------------------------------------------------------------------*/
1478 98 jeremybenn
static void
1479
read_control (unsigned char *jreg,
1480
              int            num_bits)
1481 82 jeremybenn
{
1482 98 jeremybenn
  /* Validate register size, which is fixed */
1483
  const int  REG_BITS = 88 + 32 + 4 + 1;
1484
 
1485
  if (REG_BITS != num_bits)
1486
    {
1487
      fprintf (stderr,
1488
               "ERROR: JTAG READ_CONTROL %d bits, when %d bits expected.\n",
1489
               num_bits, REG_BITS);
1490
      return;
1491
    }
1492
 
1493 82 jeremybenn
  /* Break out the fields. */
1494
  uint32_t  crc_in = reverse_bits (((uint32_t) (jreg[0] & 0xe0) >>  5) |
1495
                                   ((uint32_t)  jreg[1]         <<  3) |
1496
                                   ((uint32_t)  jreg[2]         << 11) |
1497
                                   ((uint32_t)  jreg[3]         << 19) |
1498
                                   ((uint32_t) (jreg[4] & 0x1f) << 27), 32);
1499
 
1500
  /* Compute the expected CRC */
1501
  uint32_t  crc_computed;
1502
 
1503
  crc_computed = crc32 (0,                   1, 0xffffffff);
1504
  crc_computed = crc32 (JCMD_READ_CONTROL,  4, crc_computed);
1505
 
1506
  /* CRC to go out */
1507
  uint32_t  crc_out = 0xffffffff;
1508
 
1509
  /* Status flags */
1510
  enum jtag_status  status = JS_OK;
1511
 
1512 98 jeremybenn
  /* Only do anything if the CRC's match */
1513
  if (crc_computed == crc_in)
1514 82 jeremybenn
    {
1515 98 jeremybenn
      uint64_t  data = 0;
1516 82 jeremybenn
 
1517 98 jeremybenn
      switch (runtime.debug.mod_id)
1518
        {
1519
        case JM_CPU0:
1520
 
1521
          /* Valid module. Only bit we can sensibly read is the stall
1522
             bit. Compute the CRC, reverse the data and construct the
1523
             outgoing register. */
1524
          data    = (uint64_t) runtime.cpu.stalled << JCB_STALL;
1525
          break;
1526
 
1527
        case JM_UNDEFINED:
1528
          fprintf (stderr,
1529
                   "ERROR: JTAG READ_CONTROL with no module selected.\n");
1530
          break;
1531
 
1532
        case JM_WISHBONE:
1533
          fprintf (stderr,
1534
                   "ERROR: JTAG READ_CONTROL of WishBone not supported.\n");
1535
          break;
1536
 
1537
        case JM_CPU1:
1538
          fprintf (stderr,
1539
                   "ERROR: JTAG READ_CONTROL of CPU1 not supported.\n");
1540
          break;
1541
 
1542
        default:
1543
          /* All other modules will have triggered an error on selection. */
1544
          break;
1545
        }
1546
 
1547
      /* Compute the CRC, reverse and store the data, and construct the
1548
         response with the status. */
1549 82 jeremybenn
      crc_out = crc32 (data,  52, crc_out);
1550 98 jeremybenn
      data    = reverse_bits (data, 52);
1551
 
1552
      jreg[ 4] |= (data <<  5) & 0xf8;
1553
      jreg[ 5] |= (data >>  3) & 0x07;
1554
      jreg[ 6] |= (data >> 11) & 0xff;
1555
      jreg[ 7] |= (data >> 19) & 0xff;
1556
      jreg[ 8] |= (data >> 27) & 0xff;
1557
      jreg[ 9] |= (data >> 35) & 0xff;
1558
      jreg[10] |= (data >> 43) & 0xff;
1559
      jreg[11] |= (data >> 51) & 0x01;
1560 82 jeremybenn
    }
1561
  else
1562
    {
1563 98 jeremybenn
      /* CRC Mismatch: record the error */
1564
      status |= JS_CRC_IN_ERROR;
1565 82 jeremybenn
    }
1566
 
1567 98 jeremybenn
 
1568 82 jeremybenn
  /* Construct the response with the status */
1569
  return  construct_response (jreg, status, crc_out, 52, 37);
1570
 
1571
}       /* read_control () */
1572
 
1573
 
1574
/*---------------------------------------------------------------------------*/
1575
/*!Write the control bits to a CPU.
1576
 
1577
   Process a WRITE_CONTROL register. The format is:
1578
 
1579
          +---------+-------+--------+---------+---+
1580
          |         |       |        |  WRITE  |   |
1581
   TDI -> | Ignored |  CRC  |  Data  | CONTROL | 0 | -> TDO
1582
          |         |       |        |  (0x4)  |   |
1583
          +---------+-------+--------+---------+---+
1584
              36        32      52        4
1585
             bits      bits    bits     bits
1586
 
1587
   The returned register has the format:
1588
 
1589
          +-------+--------+---------+
1590
          |       |        |         |
1591
   TDI -> |  CRC  | Status |  00..00 | -> TDO
1592
          |       |        |         |
1593
          +-------+--------+---------+
1594
              32       4        89
1595
             bits    bits      bits
1596
 
1597
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
1598
   is computed on the first 57 bits, the CRC out on the 4 status bits.
1599
 
1600 98 jeremybenn
   This is a register of a fixed size, which we verify initially.
1601
 
1602 82 jeremybenn
   @param[in,out] jreg  The register to shift in, and the register shifted
1603
                        back out.
1604 98 jeremybenn
   @param[in]     num_bits  The number of bits supplied.                     */
1605 82 jeremybenn
/*---------------------------------------------------------------------------*/
1606 98 jeremybenn
static void
1607
write_control (unsigned char *jreg,
1608
               int            num_bits)
1609 82 jeremybenn
{
1610 98 jeremybenn
  /* Validate register size, which is fixed */
1611
  const int  REG_BITS = 36 + 32 + 52 + 4 + 1;
1612
 
1613
  if (REG_BITS != num_bits)
1614
    {
1615
      fprintf (stderr,
1616
               "ERROR: JTAG WRITE_CONTROL %d bits, when %d bits expected.\n",
1617
               num_bits, REG_BITS);
1618
      return;
1619
    }
1620
 
1621 82 jeremybenn
  /* Break out the fields. */
1622
  uint64_t  data   = reverse_bits (((uint64_t) (jreg[ 0] & 0xe0) >>  5) |
1623
                                   ((uint64_t)  jreg[ 1]         <<  3) |
1624
                                   ((uint64_t)  jreg[ 2]         << 11) |
1625
                                   ((uint64_t)  jreg[ 3]         << 19) |
1626
                                   ((uint64_t)  jreg[ 4]         << 27) |
1627
                                   ((uint64_t)  jreg[ 5]         << 35) |
1628
                                   ((uint64_t)  jreg[ 6]         << 43) |
1629
                                   ((uint64_t) (jreg[ 7] & 0x01) << 51), 52);
1630
  uint32_t  crc_in = reverse_bits (((uint32_t) (jreg[ 7] & 0xfe) >>  1) |
1631
                                   ((uint32_t)  jreg[ 8]         <<  7) |
1632
                                   ((uint32_t)  jreg[ 9]         << 15) |
1633
                                   ((uint32_t)  jreg[10]         << 23) |
1634
                                   ((uint32_t) (jreg[11] & 0x01) << 31), 32);
1635
 
1636
  /* Compute the expected CRC */
1637
  uint32_t  crc_computed;
1638
 
1639
  crc_computed = crc32 (0,                   1, 0xffffffff);
1640
  crc_computed = crc32 (JCMD_WRITE_CONTROL,  4, crc_computed);
1641
  crc_computed = crc32 (data,               52, crc_computed);
1642
 
1643
  /* Status flags */
1644
  enum jtag_status  status = JS_OK;
1645
 
1646 98 jeremybenn
  /* Only use the data if CRC's match */
1647
  if (crc_computed == crc_in)
1648 82 jeremybenn
    {
1649 98 jeremybenn
      int  reset_bit;
1650
      int  stall_bit;
1651 82 jeremybenn
 
1652 98 jeremybenn
      switch (runtime.debug.mod_id)
1653 82 jeremybenn
        {
1654 98 jeremybenn
        case JM_CPU0:
1655
 
1656
          /* Good data and valid module. Reset, stall or unstall the register
1657
             as required. If reset is requested, there is no point considering
1658
             stalling! */
1659
          reset_bit = (0x1 == ((data >> JCB_RESET) & 0x1));
1660
          stall_bit = (0x1 == ((data >> JCB_STALL) & 0x1));
1661
 
1662
          if (reset_bit)
1663
            {
1664
              sim_reset ();
1665
            }
1666
          else
1667
            {
1668
              set_stall_state (stall_bit);
1669
            }
1670
 
1671
          break;
1672
 
1673
        case JM_UNDEFINED:
1674
          fprintf (stderr,
1675
                   "ERROR: JTAG WRITE_CONTROL with no module selected.\n");
1676
          break;
1677
 
1678
        case JM_WISHBONE:
1679
          fprintf (stderr,
1680
                   "ERROR: JTAG WRITE_CONTROL of WishBone not supported.\n");
1681
          break;
1682
 
1683
        case JM_CPU1:
1684
          fprintf (stderr,
1685
                   "ERROR: JTAG WRITE_CONTROL of CPU1 not supported.\n");
1686
          break;
1687
 
1688
        default:
1689
          /* All other modules will have triggered an error on selection. */
1690
          break;
1691 82 jeremybenn
        }
1692
    }
1693
  else
1694
    {
1695 98 jeremybenn
      /* CRC Mismatch: record the error */
1696
      status |= JS_CRC_IN_ERROR;
1697 82 jeremybenn
    }
1698
 
1699
  /* Construct the response with the status */
1700
  return  construct_response (jreg, status, 0xffffffff, 0, 89);
1701
 
1702
}       /* write_control () */
1703
 
1704
 
1705
/*---------------------------------------------------------------------------*/
1706
/*!Initialize the JTAG system
1707
 
1708
   For now just reset the JTAG interface                                     */
1709
/*---------------------------------------------------------------------------*/
1710
void
1711
jtag_init ()
1712
{
1713
  (void) jtag_reset ();
1714
 
1715
}       /* jtag_init () */
1716
 
1717
 
1718
/*---------------------------------------------------------------------------*/
1719
/*!Reset the JTAG interface
1720
 
1721 98 jeremybenn
   Mark the current JTAG instruction as undefined.                           */
1722 82 jeremybenn
/*---------------------------------------------------------------------------*/
1723 98 jeremybenn
void
1724 82 jeremybenn
jtag_reset ()
1725
{
1726
  runtime.debug.instr = JI_UNDEFINED;
1727
 
1728
}       /* jtag_reset () */
1729
 
1730
 
1731
/*---------------------------------------------------------------------------*/
1732
/*!Shift a JTAG instruction register
1733
 
1734
   @note Like all the JTAG interface functions, this must not be called
1735
         re-entrantly while a call to any other function (e.g. or1kim_run ())
1736
         is in progress. It is the responsibility of the caller to ensure this
1737
         constraint is met, for example by use of a SystemC mutex.
1738
 
1739
   The register is represented as a vector of bytes, with the byte at offset
1740
   zero being shifted first, and the least significant bit in each byte being
1741
   shifted first. Where the register will not fit in an exact number of bytes,
1742
   the odd bits are in the highest numbered byte, shifted to the low end.
1743
 
1744
   The format is:
1745
 
1746
          +-------------+
1747
          |             |
1748
   TDI -> | Instruction | -> TDO
1749
          |             |
1750
          +-------------+
1751
                 4
1752
               bits
1753
 
1754 98 jeremybenn
   We first verify that we have received the correct number of bits. If not we
1755
   put out a warning, and for consistency return the number of bits supplied
1756
   as the number of cycles the shift took.
1757
 
1758 82 jeremybenn
   With this debug interface, registers are shifted MS bit first, so we must
1759
   reverse the bits to get the actual value.
1760
 
1761
   We record the selected instruction. For completeness the register is parsed
1762
   and a warning given if any register other than DEBUG is shifted.
1763
 
1764 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
1765
                            back out.
1766
   @param[in]     num_bits  The number of bits supplied.                     */
1767 82 jeremybenn
/*---------------------------------------------------------------------------*/
1768 98 jeremybenn
void
1769
jtag_shift_ir (unsigned char *jreg,
1770
               int            num_bits)
1771 82 jeremybenn
{
1772 98 jeremybenn
  if (4 != num_bits)
1773
    {
1774
      fprintf (stderr, "ERROR: Invalid JTAG instruction length %d bits.\n",
1775
               num_bits);
1776
      return;
1777
    }
1778
 
1779 82 jeremybenn
  runtime.debug.instr = reverse_bits (jreg[0] & 0xf, 4);
1780
 
1781
  switch (runtime.debug.instr)
1782
    {
1783
    case JI_EXTEST:
1784 98 jeremybenn
      fprintf (stderr, "Warning: JTAG EXTEST shifted.\n");
1785 82 jeremybenn
      break;
1786
 
1787
    case JI_SAMPLE_PRELOAD:
1788 98 jeremybenn
      fprintf (stderr, "Warning: JTAG SAMPLE/PRELOAD shifted.\n");
1789 82 jeremybenn
      break;
1790
 
1791
    case JI_IDCODE:
1792 98 jeremybenn
      fprintf (stderr, "Warning: JTAG IDCODE shifted.\n");
1793 82 jeremybenn
      break;
1794
 
1795
    case JI_DEBUG:
1796
      /* Do nothing for this one */
1797
      break;
1798
 
1799
    case JI_MBIST:
1800 98 jeremybenn
      fprintf (stderr, "Warning: JTAG MBIST shifted.\n");
1801 82 jeremybenn
      break;
1802
 
1803
    case JI_BYPASS:
1804 98 jeremybenn
      fprintf (stderr, "Warning: JTAG BYPASS shifted.\n");
1805 82 jeremybenn
      break;
1806
 
1807
    default:
1808 98 jeremybenn
      fprintf (stderr, "ERROR: Unknown JTAG instruction 0x%1x shifted.\n",
1809 82 jeremybenn
               runtime.debug.instr);
1810
      break;
1811
    }
1812
}       /* jtag_shift_ir () */
1813
 
1814
 
1815
/*---------------------------------------------------------------------------*/
1816
/*!Shift a JTAG data register
1817
 
1818
   @note Like all the JTAG interface functions, this must not be called
1819
         re-entrantly while a call to any other function (e.g. or1kim_run ())
1820
         is in progress. It is the responsibility of the caller to ensure this
1821
         constraint is met, for example by use of a SystemC mutex.
1822
 
1823
   The register is represented as a vector of bytes, with the byte at offset
1824
   zero being shifted first, and the least significant bit in each byte being
1825
   shifted first. Where the register will not fit in an exact number of bytes,
1826
   the odd bits are in the highest numbered byte, shifted to the low end.
1827
 
1828
   This is only meaningful if the DEBUG register instruction is already
1829
   selected. If not, the data register is rejected.
1830
 
1831
   The register is parsed to determine which of the six possible register
1832
   types it could be.
1833 98 jeremybenn
   - SELECT_MODULE
1834 82 jeremybenn
   - WRITE_COMMNAND
1835
   - READ_COMMAND
1836
   - GO_COMMAND
1837
   - WRITE_CONTROL
1838
   - READ_CONTROL
1839
 
1840
   @note In practice READ_COMMAND is not used. However the functionality is
1841
         provided for future compatibility.
1842
 
1843
   The parsing is hierarchical. The first bit determines if we have
1844 98 jeremybenn
   SELECT_MODULE, if not, the next 4 bits determine the command.
1845 82 jeremybenn
 
1846 98 jeremybenn
   @param[in,out] jreg      The register to shift in, and the register shifted
1847
                            back out.
1848
   @param[in]     num_bits  The number of bits supplied.                     */
1849 82 jeremybenn
/*---------------------------------------------------------------------------*/
1850 98 jeremybenn
void
1851
jtag_shift_dr (unsigned char *jreg,
1852
               int            num_bits)
1853 82 jeremybenn
{
1854
  if (JI_DEBUG != runtime.debug.instr)
1855
    {
1856
      fprintf (stderr, "ERROR: Attempt to shift JTAG data register when "
1857 98 jeremybenn
               "DEBUG not instruction.\n");
1858
      return;
1859 82 jeremybenn
    }
1860
 
1861 98 jeremybenn
  int  select_module_p = (1 == (jreg[0] & 0x1));
1862 82 jeremybenn
 
1863 98 jeremybenn
  if (select_module_p)
1864 82 jeremybenn
    {
1865 98 jeremybenn
      select_module (jreg, num_bits);
1866 82 jeremybenn
    }
1867
  else
1868
    {
1869 98 jeremybenn
      switch (reverse_bits ((jreg[0] >> 1) & 0xf, 4))
1870 82 jeremybenn
        {
1871 98 jeremybenn
        case JCMD_GO_COMMAND:    go_command (jreg, num_bits); break;
1872
        case JCMD_READ_COMMAND:  read_command (jreg, num_bits); break;
1873
        case JCMD_WRITE_COMMAND: write_command (jreg, num_bits); break;
1874
        case JCMD_READ_CONTROL:  read_control (jreg, num_bits); break;
1875
        case JCMD_WRITE_CONTROL: write_control (jreg, num_bits); break;
1876 82 jeremybenn
 
1877
        default:
1878 98 jeremybenn
          /* Not a command we recognize. */
1879
          fprintf (stderr, "ERROR: DEBUG command not recognized.\n");
1880
          break;
1881 82 jeremybenn
        }
1882
    }
1883
}       /* jtag_shift_dr () */

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