| 1 |
82 |
jeremybenn |
/* jtag.c -- JTAG modeling
|
| 2 |
|
|
|
| 3 |
|
|
Copyright (C) 2010 Embecosm Limited
|
| 4 |
|
|
|
| 5 |
|
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
|
| 6 |
|
|
|
| 7 |
|
|
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
|
| 8 |
|
|
|
| 9 |
|
|
This program is free software; you can redistribute it and/or modify it
|
| 10 |
|
|
under the terms of the GNU General Public License as published by the Free
|
| 11 |
|
|
Software Foundation; either version 3 of the License, or (at your option)
|
| 12 |
|
|
any later version.
|
| 13 |
|
|
|
| 14 |
|
|
This program is distributed in the hope that it will be useful, but WITHOUT
|
| 15 |
|
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 16 |
|
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
| 17 |
|
|
more details.
|
| 18 |
|
|
|
| 19 |
|
|
You should have received a copy of the GNU General Public License along
|
| 20 |
|
|
with this program. If not, see <http://www.gnu.org/licenses/>. */
|
| 21 |
|
|
|
| 22 |
|
|
/* This program is commented throughout in a fashion suitable for processing
|
| 23 |
|
|
with Doxygen. */
|
| 24 |
|
|
|
| 25 |
|
|
|
| 26 |
|
|
#ifndef JTAG__H
|
| 27 |
|
|
#define JTAG__H
|
| 28 |
|
|
|
| 29 |
|
|
/*! Number of JTAG clock cycles a reset sequence takes */
|
| 30 |
|
|
#define JTAG_RESET_CYCLES 5
|
| 31 |
|
|
|
| 32 |
|
|
/*! Enumeration of the JTAG instruction types */
|
| 33 |
|
|
enum jtag_instr {
|
| 34 |
|
|
JI_UNDEFINED = -1, /* Won't fit in bitfield */
|
| 35 |
|
|
JI_EXTEST = 0x0,
|
| 36 |
|
|
JI_SAMPLE_PRELOAD = 0x1,
|
| 37 |
|
|
JI_IDCODE = 0x2,
|
| 38 |
|
|
JI_DEBUG = 0x8,
|
| 39 |
|
|
JI_MBIST = 0x9,
|
| 40 |
|
|
JI_BYPASS = 0xf
|
| 41 |
|
|
};
|
| 42 |
|
|
|
| 43 |
|
|
/*! Enumeration of the JTAG module IDs */
|
| 44 |
|
|
enum jtag_mod_id {
|
| 45 |
|
|
JM_UNDEFINED = -1, /* Won't fit in bitfield */
|
| 46 |
|
|
JM_WISHBONE = 0x0,
|
| 47 |
|
|
JM_CPU0 = 0x1,
|
| 48 |
|
|
JM_CPU1 = 0x2
|
| 49 |
|
|
};
|
| 50 |
|
|
|
| 51 |
|
|
/*! Enumeration of the DEBUG command types */
|
| 52 |
|
|
enum jtag_cmd {
|
| 53 |
|
|
JCMD_UNDEFINED = -1, /* Won't fit in bitfield */
|
| 54 |
|
|
JCMD_GO_COMMAND = 0x0,
|
| 55 |
|
|
JCMD_READ_COMMAND = 0x1,
|
| 56 |
|
|
JCMD_WRITE_COMMAND = 0x2,
|
| 57 |
|
|
JCMD_READ_CONTROL = 0x3,
|
| 58 |
|
|
JCMD_WRITE_CONTROL = 0x4
|
| 59 |
|
|
};
|
| 60 |
|
|
|
| 61 |
|
|
/*! Enumeration of the access types for WRITE_COMMAND */
|
| 62 |
|
|
enum jtag_acc_type {
|
| 63 |
|
|
JAT_UNDEFINED = -1, /* Won't fit in bitfield */
|
| 64 |
|
|
JAT_WRITE8 = 0, /* WishBone only */
|
| 65 |
|
|
JAT_WRITE16 = 1, /* WishBone only */
|
| 66 |
|
|
JAT_WRITE32 = 2,
|
| 67 |
|
|
JAT_READ8 = 4, /* WishBone only */
|
| 68 |
|
|
JAT_READ16 = 5, /* WishBone only */
|
| 69 |
|
|
JAT_READ32 = 6
|
| 70 |
|
|
};
|
| 71 |
|
|
|
| 72 |
|
|
/*! Enumeration of the status field bits */
|
| 73 |
|
|
enum jtag_status {
|
| 74 |
|
|
JS_OK = 0x0, /*!< No error */
|
| 75 |
|
|
JS_CRC_IN_ERROR = 0x1, /*!< Supplied CRC error */
|
| 76 |
|
|
JS_MODULE_MISSING = 0x2, /*!< Non-existent module select */
|
| 77 |
|
|
JS_WISHBONE_ERROR = 0x4, /*!< Problem accessing Wishgone */
|
| 78 |
|
|
JS_OVER_UNDERRUN = 0x8 /*!< Over/under-run of data */
|
| 79 |
|
|
};
|
| 80 |
|
|
|
| 81 |
|
|
/*! Enumeration of the control bits */
|
| 82 |
|
|
enum jtag_control_bits {
|
| 83 |
|
|
JCB_RESET = 51, /*!< Reset the processor */
|
| 84 |
|
|
JCB_STALL = 50, /*!< Stall the processor */
|
| 85 |
|
|
};
|
| 86 |
|
|
|
| 87 |
|
|
/* Function prototypes for external use */
|
| 88 |
|
|
extern void jtag_init ();
|
| 89 |
|
|
extern int jtag_reset ();
|
| 90 |
|
|
extern int jtag_shift_ir (unsigned char *jreg);
|
| 91 |
|
|
extern int jtag_shift_dr (unsigned char *jreg);
|
| 92 |
|
|
|
| 93 |
|
|
#endif /* JTAG__H */
|
