OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [debug/] [jtag.h] - Blame information for rev 861

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 82 jeremybenn
/* jtag.c -- JTAG modeling
2
 
3
   Copyright (C) 2010 Embecosm Limited
4
 
5
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
6
 
7
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
8
 
9
   This program is free software; you can redistribute it and/or modify it
10
   under the terms of the GNU General Public License as published by the Free
11
   Software Foundation; either version 3 of the License, or (at your option)
12
   any later version.
13
 
14
   This program is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17
   more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
21
 
22
/* This program is commented throughout in a fashion suitable for processing
23
   with Doxygen. */
24
 
25
 
26
#ifndef JTAG__H
27
#define JTAG__H
28
 
29
/*! Enumeration of the JTAG instruction types */
30
enum  jtag_instr {
31
  JI_UNDEFINED      =  -1,              /* Won't fit in bitfield */
32
  JI_EXTEST         = 0x0,
33
  JI_SAMPLE_PRELOAD = 0x1,
34
  JI_IDCODE         = 0x2,
35
  JI_DEBUG          = 0x8,
36
  JI_MBIST          = 0x9,
37
  JI_BYPASS         = 0xf
38
};
39
 
40
/*! Enumeration of the JTAG module IDs */
41
enum  jtag_mod_id {
42
  JM_UNDEFINED =  -1,                   /* Won't fit in bitfield */
43
  JM_WISHBONE  = 0x0,
44
  JM_CPU0      = 0x1,
45
  JM_CPU1      = 0x2
46
};
47
 
48
/*! Enumeration of the DEBUG command types */
49
enum  jtag_cmd {
50
  JCMD_UNDEFINED     = -1,              /* Won't fit in bitfield */
51
  JCMD_GO_COMMAND    = 0x0,
52
  JCMD_READ_COMMAND  = 0x1,
53
  JCMD_WRITE_COMMAND = 0x2,
54
  JCMD_READ_CONTROL  = 0x3,
55
  JCMD_WRITE_CONTROL = 0x4
56
};
57
 
58
/*! Enumeration of the access types for WRITE_COMMAND */
59
enum  jtag_acc_type {
60
  JAT_UNDEFINED  = -1,                  /* Won't fit in bitfield */
61
  JAT_WRITE8     = 0,                    /* WishBone only */
62
  JAT_WRITE16    = 1,                   /* WishBone only */
63
  JAT_WRITE32    = 2,
64
  JAT_READ8      = 4,                   /* WishBone only */
65
  JAT_READ16     = 5,                   /* WishBone only */
66
  JAT_READ32     = 6
67
};
68
 
69
/*! Enumeration of the status field bits */
70
enum jtag_status {
71
  JS_OK             = 0x0,              /*!< No error */
72
  JS_CRC_IN_ERROR   = 0x1,              /*!< Supplied CRC error */
73
  JS_MODULE_MISSING = 0x2,              /*!< Non-existent module select */
74
  JS_WISHBONE_ERROR = 0x4,              /*!< Problem accessing Wishgone */
75
  JS_OVER_UNDERRUN  = 0x8               /*!< Over/under-run of data */
76
};
77
 
78
/*! Enumeration of the control bits */
79
enum jtag_control_bits {
80
  JCB_RESET = 51,                       /*!< Reset the processor */
81
  JCB_STALL = 50,                       /*!< Stall the processor */
82
};
83
 
84
/* Function prototypes for external use */
85
extern void  jtag_init ();
86 98 jeremybenn
extern void  jtag_reset ();
87
extern void  jtag_shift_ir (unsigned char *jreg,
88
                            int            num_bits);
89
extern void  jtag_shift_dr (unsigned char *jreg,
90
                            int            num_bits);
91 82 jeremybenn
 
92
#endif  /* JTAG__H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.