OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [or1ksim.info] - Blame information for rev 104

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 104 jeremybenn
This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
2
../../doc/or1ksim.texi.
3 19 jeremybenn
 
4
INFO-DIR-SECTION Embedded development
5
START-INFO-DIR-ENTRY
6
* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
7
                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 104 jeremybenn
     tar jxf or1ksim-0.4.0rc1.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
82 19 jeremybenn
default to OpenRISC 1000 32-bit with a warning
83
 
84 104 jeremybenn
     ../or1ksim-0.4.0rc1/configure --target=or32-uclinux ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 104 jeremybenn
For testing (using `make check'), the `--target' parameter _must_ be
92
specified, to allow the target tool chain to be selected. If the tools
93
have been installed using the standard OpenRISC script, then this
94
should be set to `or32-elf'.
95 19 jeremybenn
 
96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
101 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
`--enable-execution=dynamic'
108
     Or1ksim has developed to improve functionality and performance.
109
     This feature allows three versions of Or1ksim to be built
110
 
111
    `--enable-execution=simple'
112
          Build the original simple interpreting simulator
113
 
114
    `--enable-execution=complex'
115 82 jeremybenn
          Build a more complex interpreting simulator.  Experiments
116
          suggest this is 50% faster than the simple simulator.  This
117
          is the default.
118 19 jeremybenn
 
119
    `--enable-execution=dynamic'
120 82 jeremybenn
          Build a dynamically compiling simulator.  This is the way
121
          many modern ISS are built.  This represents a work in
122
          progress.  Currently Or1ksim will compile, but segfaults if
123
          configured with this option.
124 19 jeremybenn
 
125
 
126
     The default is `--enable-execution=complex'.
127
 
128
`--enable-ethphy'
129
`--disable-ethphy'
130
     If enabled, this option allows the Ethernet to be simulated by
131
     connecting via a socket (the alternative reads and writes, from
132 82 jeremybenn
     and to files).  This must then be configured using the relevant
133
     fields in the `ethernet' section of the configuration file.  *Note
134 19 jeremybenn
     Ethernet Configuration: Ethernet Configuration.
135
 
136
     The default is for this to be disabled.
137
 
138
`--enable-range-stats'
139
`--disable-range-stats'
140
     If enabled, this option allows statistics to be collected to
141 82 jeremybenn
     analyse register access over time.  The default is for this to be
142 19 jeremybenn
     disabled.
143
 
144
`--enable-ov-flag'
145
`--disable-ov-flag'
146
     If enabled, this option causes instructions to set the overflow
147 82 jeremybenn
     flag.  The instructions affected by this are `l.add', `l.addc',
148 19 jeremybenn
     `l.addi', `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli',
149
     `l.or', `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra',
150
     `l.srai', `l.sub', `l.xor' and `l.xori'.
151
 
152
     The default is for this to be disabled.
153
 
154
          Caution: This appears a very dangerous option, to the extent
155 82 jeremybenn
          of arguably being a bug.  Whether or not flags are set is
156
          part of the OpenRISC 1000 architectural specification.
157
          Within the above list, the arithmetic instructions (`l.add',
158
          `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
159
          `l.sub'), together with `l.addic' which is missed out, set
160
          the overflow flag.  All the others (`l.and', `l.andi',
161
          `l.or', `l.ori', `l.sll', `l.slli', `l.srl', `l.srli',
162
          `l.sra', `l.srai', `l.xor' and `l.xori') do not.
163 19 jeremybenn
 
164
          Thus it is impossible to get correct behavior whichever way
165
          this option is set.
166
 
167
`--enable-arith-flag'
168
`--disable-arith-flag'
169
     If enabled, this option causes instructions to set the flag (`F'
170 82 jeremybenn
     bit) in the supervision register.  The instructions affected by
171 19 jeremybenn
     this are `l.add', `l.addc', `l.addi', `l.and' and `l.andi'.
172
 
173
     The default is for this to be disabled.
174
 
175
          Caution: As with `--enable-ov-flag', this appears another
176
          very dangerous option, to the extent of arguably being a bug.
177
          It also appears to be only partially implemented--why only
178
          the instructions early in the alphabet?
179
 
180
          Whether or not flags are set is part of the OpenRISC 1000
181 82 jeremybenn
          architectural specification.  The only flags which should set
182 19 jeremybenn
          this are the "set flag" instructions: `l.sfeq', `l.sfeqi',
183
          `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui', `l.sfgts',
184
          `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles', `l.sflesi',
185
          `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi', `l.sfltu',
186
          `l.sfltui', `l.sfne' and `l.sfnei'.
187
 
188
          The flags are correctly set (irrespective of
189
          `--enable-arith_flag').
190
 
191
          Correct behavior is thus achieved if this flag is not set.
192
          `--enable-arith-flag' should never be used.
193
 
194
 
195
`--enable-debug'
196
`--disable-debug'
197
     This is a feature of the Argtable2 package used to process
198 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
199
     Argtable2.  It is provided for completeness, but there is no
200
     reason why this feature should ever be needed by any Or1ksim user.
201 19 jeremybenn
 
202 82 jeremybenn
`--enable-all-tests'
203
`--disable-all-tests'
204
     Some of the tests (at the time of writing just one) will not
205
     compile without error.  If enabled with this flag, all test
206
     programs will be compiled with `make check'.
207 19 jeremybenn
 
208 82 jeremybenn
     This flag is intended for those working on the test package, who
209
     wish to get the missing test(s) working.
210
 
211
 
212 19 jeremybenn

213
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
214
 
215
1.3 Building and Installing
216
===========================
217
 
218 82 jeremybenn
Build the tool with:
219 19 jeremybenn
 
220
     make all
221 82 jeremybenn
 
222
If you have the OpenRISC tool chain and DejaGNU installed, you can
223
verify the tool as follows (otherwise omit this step):
224
 
225
     make check
226
 
227
Install the tool with:
228
 
229 19 jeremybenn
     make install
230
 
231
This will install the three variations of the Or1ksim tool,
232
`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the
233
Or1ksim library, `libsim', the header file, `or1ksim.h' and this
234
documentation in `info' format.
235
 
236
     Note: Testing Or1ksim with `make check' is not yet supported.
237
 
238
The documentation may be created and installed in alternative formats
239
(PDF, Postscript, DVI, HTML) with for example:
240
 
241
     make pdf
242
     make install-pdf
243
 
244

245
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
246
 
247
1.4 Known Problems and Issues
248
=============================
249
 
250 82 jeremybenn
The following problems and issues are known about with Or1ksim
251 104 jeremybenn
0.4.0rc1.  The OpenRISC tracker may be used to see the current state of
252
these issues and to raise new problems and feature requests.  It may be
253
found at `http://www.opencores.org/ptracker.cgi/view/or1k/398'.
254 19 jeremybenn
 
255
   * The Supervision Register Little Endian Enable (LEE) bit is
256 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
257 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
258
 
259
   * The NPC is a read/write register, but after being written it
260 82 jeremybenn
     clears the pipeline.  This means that if the processor is stalled,
261 19 jeremybenn
     the value should subsequently read back as 0, until the processor
262 82 jeremybenn
     is unstalled and able to refill its pipeline.  By default Or1ksim
263 19 jeremybenn
     always reports back the value of NPC, even when it has been
264
     written while stalled.
265
 
266
     There is now an option, `--strict-npc', which will enforce this
267 82 jeremybenn
     behavior.  At some stage in the future it will become the default
268 19 jeremybenn
     behavior, but for now it is an option, since its use will break
269
     GDB.
270
 
271
   * The memory components are given names in the configuration file.
272
     However there is currently no way for Or1ksim to report that name
273
     back to the user (for example to identify which memory block
274
     corresponds to a particular access).
275
 
276
   * Or1ksim allows the processor to be stalled (from the command
277 82 jeremybenn
     line), even if there is no debugger present.  This seems to be a
278 19 jeremybenn
     meaningless operation.
279
 
280
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
281 82 jeremybenn
     instances using the library.  This is clearly a problem when
282
     considering multi-core applications.  However it stems from the
283
     original design, and can only be fixed by a complete rewrite.  The
284 19 jeremybenn
     entire source code uses static global constants liberally!
285
 
286 104 jeremybenn
   * There is no support for single precision floating point
287
     instructions in Or1ksim if configured in the CPU (*note CPU
288
     Configuration: CPU Configuration.).  These are implemented using
289
     the floating point support in the host C library, which will
290
     usually be IEEE 745 compliant.  There is at present no support for
291
     double precision floating point instructions, since these are
292
     meaningless with 32-bit registers.
293 19 jeremybenn
 
294 104 jeremybenn
     Floating point support within OpenRISC is intended to follow IEEE
295
     745, which offers a degree of configurability. However at present
296
     the FPSCR register is not supported, so there is no mechanism for
297
     configuring floating point behavior. Thus the default
298
     functionality of the host C library will be used.
299 19 jeremybenn
 
300 104 jeremybenn
   * The single precision floating point multiply and add instruction,
301
     `lf.madd.s', is not clearly specified in the original architectural
302
     manual. User should consult the `OpenRISC 1200 version 2
303
     Supplementary Programmer's Reference Manual' for a specification
304
     of the functionality implemented.
305
 
306
 
307 19 jeremybenn

308
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
309
 
310
2 Usage
311
*******
312
 
313
* Menu:
314
 
315
* Standalone Simulator::
316
* Profiling Utility::
317
* Memory Profiling Utility::
318
* Simulator Library::
319
 
320

321
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
322
 
323
2.1 Standalone Simulator
324
========================
325
 
326
The general form the standalone command is:
327
 
328
     or32-uclinux-sim [-vhi] [-f FILE] [--nosrv] [--srv=[N]] [-d STR]
329
                      [--enable-profile] [--enable-mprofile] [FILE]
330
 
331 82 jeremybenn
Many of the options have both a short and a long form.  For example
332
`-h' or `--help'.
333 19 jeremybenn
 
334
`-v'
335
`--version'
336
     Print out the version and copyright notice for Or1ksim and exit.
337
 
338
`-h'
339
`--help'
340
     Print out help about the command line options and what they mean.
341
 
342
`-f FILE'
343
`--file FILE'
344
     Read configuration commands from the specified file, looking first
345
     in the current directory, and otherwise in the `$HOME/.or1k'
346 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
347
     in those two locations is used.  Failure to find the file is a
348
     fatal error.  *Note Configuration: Configuration, for detailed
349
     information on configuring Or1ksim.
350 19 jeremybenn
 
351
`--nosrv'
352 82 jeremybenn
     Do not start up the debug server.  This overrides any setting
353
     specified in the configuration file.  This option may not be
354
     specified with `--srv'.  If it is, a rude message is printed and
355
     the `--nosrv' option is ignored.
356 19 jeremybenn
 
357
`--srv'
358
 
359
`--srv=N'
360 82 jeremybenn
     Start up the debug server.  If the parameter, N, is specified, use
361 19 jeremybenn
     that as the TCP/IP port for the server, otherwise a random value
362 82 jeremybenn
     from the private port range (41920-65535) will be used.  This
363
     option may not be specified with `--nosrv'.  If it is, a rude
364
     message is printed and the `--nosrv' option is ignored.
365 19 jeremybenn
 
366
`-d=CONFIG_STRING'
367
`--debug-config=CONFIG_STRING'
368 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
369
     use by developers only, and is not covered further here.  See the
370 19 jeremybenn
     source code for more details.
371
 
372
`-i'
373
`--interactive'
374
     After starting, drop into the Or1ksim interactive command shell.
375
 
376
`--strict-npc'
377
     In real hardware, setting the next program counter (NPC, SPR 16),
378 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
379
     until the pipeline refills, reading the NPC will return zero.
380
     This is typically the case when debugging, since the processor is
381 19 jeremybenn
     stalled.
382
 
383
     Historically, Or1ksim has always returned the value of the NPC,
384 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
385
     is used, then Or1ksim will mirror real hardware more accurately.
386
     If the NPC is changed while the processor is stalled, subsequent
387 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
388
 
389
     This is not currently the default behavior, since tools such as
390
     GDB have been implemented assuming the historic Or1ksim behavior.
391
     However at some time in the future it will become the default.
392
 
393
`--enable-profile'
394
     Enable instruction profiling.
395
 
396
`--enable-mprofile'
397
     Enable memory profiling.
398
 
399
 
400

401
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
402
 
403
2.2 Profiling Utility
404
=====================
405
 
406 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
407
It may be invoked as a standalone command, or from the Or1ksim CLI.
408
The general form the standalone command is:
409 19 jeremybenn
 
410
     or32-uclinux-profile [-vhcq] [-g=FILE]
411
 
412 82 jeremybenn
Many of the options have both a short and a long form.  For example
413
`-h' or `--help'.
414 19 jeremybenn
 
415
`-v'
416
`--version'
417
     Print out the version and copyright notice for the Or1ksim
418
     profiling utility and exit.
419
 
420
`-h'
421
`--help'
422
     Print out help about the command line options and what they mean.
423
 
424
`-c'
425
`--cumulative'
426
     Show cumulative sum of cycles in functions
427
 
428
`-q'
429
`--quiet'
430
     Suppress messages
431
 
432
`-g=FILE'
433
`--generate=FILE'
434 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
435 19 jeremybenn
     `sim.profile' is used.
436
 
437
 
438

439
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Simulator Library,  Prev: Profiling Utility,  Up: Usage
440
 
441
2.3 Memory Profiling Utility
442
============================
443
 
444 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
445
be invoked as a standalone command, or from the Or1ksim CLI.  The
446 19 jeremybenn
general form the standalone command is:
447
 
448
     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
449
 
450 82 jeremybenn
Many of the options have both a short and a long form.  For example
451
`-h' or `--help'.
452 19 jeremybenn
 
453
`-v'
454
`--version'
455
     Print out the version and copyright notice for the Or1ksim memory
456
     profiling utility and exit.
457
 
458
`-h'
459
`--help'
460
     Print out help about the command line options and what they mean.
461
 
462
`-m=M'
463
`--mode=M'
464 82 jeremybenn
     Specify the mode out output.  Permitted options are
465 19 jeremybenn
 
466
    `detailed'
467
    `d'
468 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
469 19 jeremybenn
 
470
    `pretty'
471
    `p'
472
          Pretty printed output.
473
 
474
    `access'
475
    `a'
476
          Memory accesses only.
477
 
478
    `width'
479
    `w'
480
          Access width only.
481
 
482
 
483
`-g=N'
484
`--group=N'
485
     Group 2^n bits of successive addresses together.
486
 
487
`-f=FILE'
488
`--filename=FILE'
489 82 jeremybenn
     The data file to analyse.  If not specified, the default,
490 19 jeremybenn
     `sim.profile' is used.
491
 
492
`FROM'
493
`TO'
494
     FROM and TO are respectively the start and end address of the
495
     region of memory to be analysed.
496
 
497
 
498

499
File: or1ksim.info,  Node: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
500
 
501
2.4 Simulator Library
502
=====================
503
 
504
Or1ksim may be used as a static of dynamic library, `libsim.a' or
505 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
506 19 jeremybenn
should be added to the link command.
507
 
508
The header file `or1ksim.h' contains appropriate declarations of the
509 82 jeremybenn
functions exported by the Or1ksim library.  These are:
510 19 jeremybenn
 
511 93 jeremybenn
 -- `or1ksim.h': int or1ksim_init (const char
512
     *CONFIG_FILE, const char *IMAGE_FILE, void *CLASS_PTR, int
513
     (*UPR)(void *CLASS_PTR, unsigned long int ADDR, unsigned char
514
     MASK[], unsigned char RDATA[], int DATA_LEN), int (*UPW)(void
515
     *CLASS_PTR, unsigned long int ADDR, unsigned char MASK[], unsigned
516
     char WDATA[], int DATA_LEN))
517
 
518 19 jeremybenn
     The initialization function is supplied with the name of a
519
     configuration file, CONFIG_FILE, an executable image, IMAGE_FILE,
520
     a pointer to the calling class, CLASS_PTR (since the library may
521
     be used from C++) and two up-call functions, one for reads, UPR,
522
     and one for writes, UPW.
523
 
524
     *Note Configuration: Configuration, for detailed information on
525
     configuring Or1ksim and the format of the configuration file.
526
 
527
     UPW is called for any write to an address external to the model
528 82 jeremybenn
     (determined by a `generic' section in the configuration file).
529
     UPR is called for any reads to an external address.  The CLASS_PTR
530
     is passed back with these upcalls, allowing the function to
531
     associate the call with the class which originally initialized the
532 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
533
     non-zero otherwise.  At the present time the meaning of non-zero
534
     values is not defined but this may change in the future.
535 19 jeremybenn
 
536 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
537 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
538 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
539
     address, since the upcall function must handle all generic
540
     devices, using the full address for decoding.
541 19 jeremybenn
 
542 93 jeremybenn
     Endianness is not completely transparent, since Or1ksim is
543
     transferring byte vectors, not multi-byte values.
544 19 jeremybenn
 
545 93 jeremybenn
          Caution: This is a change from version 0.3.0. It simplifies
546
          the interface, and makes Or1ksim more consistent with payload
547
          representation in SystemC TLM 2.0.
548 19 jeremybenn
 
549 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
550
          single words (4 bytes), using masks if smaller values are
551
          required.  In this it mimcs the behavior of the WishBone bus.
552
 
553
 
554 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
555
     Run the simulator for the simulated duration specified (in
556
     seconds).
557
 
558
 
559
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
560
     Change the duration of a run specified in an earlier call to
561 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
562 19 jeremybenn
     realizes it needs to change the duration of the run specified in
563
     the call to `or1ksim_run' that has been interrupted by the upcall.
564
 
565
     The time specified is the amount of time that the run must continue
566
     for (i.e the duration from _now_, not the duration from the
567
     original call to `or1ksim_run').
568
 
569
 
570
 -- `or1ksim.h': void or1ksim_set_time_point ()
571 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
572 19 jeremybenn
 
573
 
574
 -- `or1ksim.h': double or1ksim_get_time_period ()
575
     Return the simulated time (in seconds) that has elapsed since the
576
     last call to `or1ksim_set_time_point'.
577
 
578
 
579
 -- `or1ksim.h': int or1ksim_is_le ()
580
     Return 1 (logical true) if the Or1ksim simulation is
581
     little-endian, 0 otherwise.
582
 
583
 
584
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
585 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
586
     specified in the configuration file.
587 19 jeremybenn
 
588
 
589
 -- `or1ksim.h': void or1ksim_interrupt (int I)
590 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
591
     interrupt is then immediately cleared automatically.  A warning
592 19 jeremybenn
     will be generated and the interrupt request ignored if level
593
     sensitive interrupts have been configured with the programmable
594
     interrupt controller (*note Interrupt Configuration: Interrupt
595
     Configuration.).
596
 
597
 
598
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
599 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
600 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
601 82 jeremybenn
     `or1ksim_interrupt_clear'.  A warning will be generated, and the
602 19 jeremybenn
     interrupt request ignored if edge sensitive interrupts have been
603
     configured with the programmable interrupt controller (*note
604
     Interrupt Configuration: Interrupt Configuration.).
605
 
606
 
607
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
608
     Clear a level-triggered interrupt on interrupt line I, which was
609 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
610 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
611
     edge sensitive interrupts have been configured with the
612
     programmable interrupt controller (*note Interrupt Configuration:
613
     Interrupt Configuration.).
614
 
615
 
616 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
617
     Drive a reset sequence through the JTAG interface. Return the
618
     (model) time taken for this action.  Remember that the JTAG has
619
     its own clock, which can be an order of magnitude slower than the
620
     main clock, so even a reset (5 JTAG cycles) could take 50
621
     processor clock cycles to complete.
622
 
623
 
624
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned
625
     char *JREG, int NUM_BITS)
626
 
627
     Shift the supplied register through the JTAG instruction register.
628
     Return the (model) time taken for this action. The register is
629
     supplied as a byte vector, with the least significant bits in the
630
     least significant byte.  If the total number of bits is not an
631
     exact number of bytes, then the odd bits are found in the least
632
     significant end of the highest numbered byte.
633
 
634
     For example a 12-bit register would have bits 0-7 in byte 0 and
635
     bits 11-8 in the least significant 4 bits of byte 1.
636
 
637
 
638
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned
639
     char *JREG, int NUM_BITS)
640
 
641
     Shift the supplied register through the JTAG data register.
642
     Return the (model) time taken for this action. The register is
643
     supplied as a byte vector, with the least significant bits in the
644
     least significant byte.  If the total number of bits is not an
645
     exact number of bytes, then the odd bits are found in the least
646
     significant end of the highest numbered byte.
647
 
648
     For example a 12-bit register would have bits 0-7 in byte 0 and
649
     bits 11-8 in the least significant 4 bits of byte 1.
650
 
651
 
652 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
653
installation directory (as specified with the `--prefix' option to the
654
`configure' script).
655
 
656
For example if the main installation directory is `/opt/or1ksim', the
657 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
658 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
659
(`libsim.so').
660
 
661
To link against the library add the `-lsim' flag when linking and do
662
one of the following:
663
 
664
   * Add the library directory to the `LD_LIBRARY_PATH' environment
665 82 jeremybenn
     variable during execution.  For example:
666 19 jeremybenn
 
667
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
668
 
669
   * Add the library directory to the `LD_RUN_PATH' environment
670 82 jeremybenn
     variable during linking.  For example:
671 19 jeremybenn
 
672
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
673
 
674
   * Use the linker `--rpath' option and specify the library directory
675 82 jeremybenn
     when linking your program.  For example
676 19 jeremybenn
 
677 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
678 19 jeremybenn
 
679
   * Add the library directory to `/etc/ld.so.conf'
680
 
681
 
682

683
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
684
 
685
3 Configuration
686
***************
687
 
688 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
689 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
690 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
691
the default `sim.cfg' is used.  The file is looked for first in the
692 19 jeremybenn
current directory, then in the `$HOME/.or1k' directory of the user.
693
 
694
* Menu:
695
 
696
* Configuration File Format::
697
* Simulator Configuration::
698
* Core OpenRISC Configuration::
699
* Peripheral Configuration::
700
 
701

702
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
703
 
704
3.1 Configuration File Format
705
=============================
706
 
707
The configuration file is a plain text file.
708
 
709
* Menu:
710
 
711
* Configuration File Preprocessing::
712
* Configuration File Syntax::
713
 
714

715
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
716
 
717
3.1.1 Configuration File Preprocessing
718
--------------------------------------
719
 
720 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
721 19 jeremybenn
`/*' and `*/').
722
 
723
Configure files may be included, using
724
 
725
     include FILENAME_TO_INCLUDE
726
 
727

728
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
729
 
730
3.1.2 Configuration File Syntax
731
-------------------------------
732
 
733
The configuration file is divided into a series of sections, with the
734
general form:
735
 
736
     section SECTION_NAME
737
 
738
       ...
739
 
740
     end
741
 
742
Sections may also have sub-sections within them (currently only the
743
ATA/ATAPI disc interface uses this).
744
 
745
Within a section, or sub-section are a series of parameter assignments,
746
one per line, withe the general form
747
 
748
       PARAMETER = VALUE
749
 
750
Depending on the parameter, the value may be a named value (an
751
enumeration), an integer (specified in any format acceptable in C) or a
752 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
753
mean "true" or "on" and the value "0" to mean "false" or "off".  An
754 19 jeremybenn
example from a memory section shows each of these
755
 
756
     section memory
757
       type    = random
758
       pattern = 0x00
759
       name    = "FLASH"
760
       ...
761
     end
762
 
763
Many parameters are optional and take reasonable default values if not
764 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
765 19 jeremybenn
parameter in `section memory') _must_ be specified.
766
 
767
Subsections are introduced by a keyword, with a parameter value (no `='
768 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
769 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
770
 
771
     section ata
772
       ...
773
       device 0
774
         type    = 1
775
         file = "FILENAME"
776
         ...
777
       enddevice
778
       ...
779
     end
780
 
781
Some sections (for example `section sim') should appear only once.
782
Others (for example `section memory' may appear multiple times.
783
 
784
Sections may be omitted, _unless they contain parameters which are
785 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
786 19 jeremybenn
is optional (for example whether it has a UART), then that
787 82 jeremybenn
functionality will not be provided.  If the section describes a part of
788 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
789
parameters of that section will take their default values.
790
 
791
All optional parts of the functionality are always described by
792
sections including a `enabled' parameter, which can be set to 0 to
793
ensure that functionality is explicitly omitted.
794
 
795
Even if a section is disabled, all its parameters will be read and
796 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
797
the Or1ksim command line (*note Interactive Command Line: Interactive
798 19 jeremybenn
Command Line.).
799
 
800
     Tip: It generally clearer to have sections describing _all_
801
     components, with omitted functionality explicitly indicated by
802
     setting the `enabled' parameter to 0
803
 
804
The following sections describe the various configuration sections and
805
the parameters which may be set in each.
806
 
807

808
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
809
 
810
3.2 Simulator Configuration
811
===========================
812
 
813
* Menu:
814
 
815
* Simulator Behavior::
816
* Verification API Configuration::
817
* CUC Configuration::
818
 
819

820
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
821
 
822
3.2.1 Simulator Behavior
823
------------------------
824
 
825 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
826
appear only once.  The following parameters may be specified.
827 19 jeremybenn
 
828
`verbose = 0|1'
829 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
830 19 jeremybenn
 
831
`debug = 0-9'
832 82 jeremybenn
 
833
     higher the value the greater the number of messages.  Default 0.
834
     Negative values will be treated as 0 (with a warning).  Values
835
     that are too large will be treated as 9 (with a warning).
836 19 jeremybenn
 
837
`profile = 0|1'
838
     If 1 (true) generate a profiling file using the file specified in
839 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
840 19 jeremybenn
 
841
`prof_file = ``FILENAME'''
842 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
843
     Default `sim.profile'.  For backwards compatibility, the
844
     alternative name `prof_fn' is supported for this parameter, but
845
     deprecated.
846 19 jeremybenn
 
847
`mprofile = 0|1'
848
     If 1 (true) generate a memory profiling file using the file
849
     specified in the `mprof_file' parameter or otherwise
850 82 jeremybenn
     `sim.mprofile'.  Default 0.
851 19 jeremybenn
 
852
`mprof_fn = ``FILENAME'''
853
     Specifies the file to be used with the `mprofile' parameter.
854 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
855 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
856
     deprecated.
857
 
858
`history = 0|1'
859 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
860 19 jeremybenn
 
861
          Note: Setting this parameter seriously degrades performance.
862
 
863
          Note: If this execution flow tracking is enabled, then
864
          `dependstats' must be enabled in the CPU configuration
865
          section (*note CPU Configuration: CPU Configuration.).
866
 
867
`exe_log = 0|1'
868 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
869
     file specified in parameter `exe_log_file'.  Default 0.
870 19 jeremybenn
 
871
          Note: Setting this parameter seriously degrades performance.
872
 
873
`exe_log_type = default|hardware|simple|software'
874
     Type of execution log to produce.
875
 
876
    `default'
877 82 jeremybenn
          Produce default output for the execution log.  In the current
878 19 jeremybenn
          implementation this is the equivalent of `hardware'.
879
 
880
    `hardware'
881
          After each instruction execution, log the number of
882
          instructions executed so far, the next instruction to execute
883
          (in hex), the general purpose registers (GPRs), status
884
          register, exception program counter, exception, effective
885
          address register and exception status register.
886
 
887
    `simple'
888
          After each instruction execution, log the number of
889
          instructions executed so far and the next instruction to
890
          execute, symbolically disassembled.
891
 
892
    `software'
893
          After each instruction execution, log the number of
894
          instructions executed so far and the next instruction to
895 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
896 19 jeremybenn
          each operand to the instruction.
897
 
898
 
899 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
900 19 jeremybenn
     insensitive) will be treated as the default with a warning.
901
 
902
          Note: Execution logs can be _very_ big.
903
 
904
`exe_log_start = VALUE'
905 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
906 19 jeremybenn
 
907
`exe_log_end = VALUE'
908 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
909
     once started logging will continue until the simulator exits).
910 19 jeremybenn
 
911
`exe_log_marker = VALUE'
912
     Specifies the number of instructions between printing horizontal
913 82 jeremybenn
     markers.  Default is to produce no markers.
914 19 jeremybenn
 
915
`exe_log_file = FILENAME'
916
     Filename for the execution log filename if `exe_log' is enabled.
917 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
918 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
919
     deprecated.
920
 
921
`clkcycle = VALUE[ps|ns|us|ms]'
922 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
923
     specified, `ps' is assumed.  Default 4000ps (250MHz).
924 19 jeremybenn
 
925
 
926

927
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
928
 
929
3.2.2 Verification API (VAPI) Configuration
930
-------------------------------------------
931
 
932
The Verification API (VAPI) provides a TCP/IP interface to allow
933 82 jeremybenn
components of the simulation to be controlled externally.  *Note
934 19 jeremybenn
Verification API: Verification API, for more details.
935
 
936 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
937
section may appear at most once.  The following parameters may be
938 19 jeremybenn
specified.
939
 
940
`enabled = 0|1'
941
     If 1 (true), verification API is enabled and its server started.
942
     If 0 (the default), it is disabled.
943
 
944
`server_port = VALUE'
945
     When VAPI is enabled, communication will be via TCP/IP on the port
946 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
947 19 jeremybenn
     The default value is 50000.
948
 
949 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
950 19 jeremybenn
          practice suggests users should adopt port values in the
951 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
952 19 jeremybenn
 
953
`log_enabled = 0|1'
954
     If 1 (true), all VAPI requests and sent commands will be logged.
955 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
956 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
957
 
958
          Caution: This can generate a substantial amount of file I/O
959
          and seriously degrade simulator performance.
960
 
961
`hide_device_id = 0|1'
962 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
963
     device ID.  This feature (when set to 1) is provided for backwards
964 19 jeremybenn
     compatibility with an old version of VAPI.
965
 
966
`vapi_log_file = "FILENAME"'
967
     Use `filename' as the file for logged data is logging is enabled
968 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
969 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
970
     supported for this parameter, but deprecated.
971
 
972
 
973

974
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
975
 
976
3.2.3 Custom Unit Compiler (CUC) Configuration
977
----------------------------------------------
978
 
979
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
980 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
981
beyond the initial prototype phase.  The configuration parameters are
982 19 jeremybenn
described here for the record.
983
 
984 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
985
appear at most once.  The following parameters may be specified.
986 19 jeremybenn
 
987
`memory_order = none|weak|strong|exact'
988
     This parameter specifies the memory ordering required:
989
 
990
    `memory_order=none'
991
          Different memory ordering, even if there are dependencies.
992
          Bursts can be made, width can change.
993
 
994 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
995 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
996
          change.
997
 
998 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
999 19 jeremybenn
 
1000
          Exactly the same memory ordering and widths.
1001
 
1002
 
1003 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1004 19 jeremybenn
     orderings are ignored with a warning.
1005
 
1006
`calling_convention = 0|1'
1007 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1008 19 jeremybenn
     (the default), they may use other convenitions.
1009
 
1010
`enable_bursts = 0 | 1'
1011 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1012 19 jeremybenn
     not detected.
1013
 
1014
`no_multicycle = 0 | 1'
1015 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1016
     (the default), multicycle logic paths will be generated.
1017 19 jeremybenn
 
1018
`timings_file = "FILENAME"'
1019 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1020
     default value is `"virtex.tim"'.  For backwards compatibility, the
1021 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1022
     deprecated.
1023
 
1024
 
1025

1026
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1027
 
1028
3.3 Configuring the OpenRISC Architectural Components
1029
=====================================================
1030
 
1031
* Menu:
1032
 
1033
* CPU Configuration::
1034
* Memory Configuration::
1035
* Memory Management Configuration::
1036
* Cache Configuration::
1037
* Interrupt Configuration::
1038
* Power Management Configuration::
1039
* Branch Prediction Configuration::
1040
* Debug Interface Configuration::
1041
 
1042

1043
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1044
 
1045
3.3.1 CPU Configuration
1046
-----------------------
1047
 
1048 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1049
appear only once.  At present Or1ksim does not model multi-CPU systems.
1050 19 jeremybenn
The following parameters may be specified.
1051
 
1052
`ver = VALUE'
1053
 
1054
`cfg = VALUE'
1055
 
1056
`rev = VALUE'
1057
     The values are used to form the corresponding fields in the `VR'
1058 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1059 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1060
     and `cfg', 6 bits for `rev').
1061
 
1062
`upr = VALUE'
1063
     Used as the value of the Unit Present Register (UPR) Special
1064 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1065 19 jeremybenn
     i.e.
1066
        * UPR present (0x00000001)
1067
 
1068
        * Data cache present (0x00000002)
1069
 
1070
        * Instruction cache present (0x00000004)
1071
 
1072
        * Data MMY present (0x00000008)
1073
 
1074
        * Instruction MMU present (0x00000010)
1075
 
1076
        * Debug unit present (0x00000040)
1077
 
1078
        * Power management unit present (0x00000100)
1079
 
1080
        * Programmable interrupt controller present (0x00000200)
1081
 
1082
        * Tick timer present (0x00000400)
1083
 
1084
     However, with the exection of the UPR present (0x00000001) and tick
1085
     timer present, the various fields will be modified with the values
1086
     specified in their corresponding configuration sections.
1087
 
1088
`cfgr = VALUE'
1089
     Sets the CPU configuration register (Special Purpose Register 2) to
1090 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1091
     instruction set.  Attempts to set any other value are accepted, but
1092 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1093
 
1094
`sr = VALUE'
1095
     Sets the supervision register Special Purpose Register (SPR 0x11)
1096 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1097 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1098
 
1099 98 jeremybenn
          Note: This is particularly useful when an image is held in
1100
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1101
          so that interrupt vectors are basedf at 0xf0000000, rather
1102
          than 0x0.
1103
 
1104 19 jeremybenn
`superscalar = 0|1'
1105 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1106 19 jeremybenn
     0.
1107
 
1108
     In the current simulator, the only functional effect of superscalar
1109
     mode is to affect the calculation of the number of cycles taken to
1110
     execute an instruction.
1111
 
1112
          Caution: The code for this does not appear to be complete or
1113
          well tested, so users are advised not to use this option.
1114
 
1115
`hazards = 0|1'
1116 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1117
     value is 0.
1118 19 jeremybenn
 
1119
     In the current simulator, the only functional effect is to cause
1120
     logging of hazard waiting information if the CPU is superscalar.
1121
     However nowhere in the simulator is this data actually computed,
1122
     so the net result is probably to have no effect.
1123
 
1124
     if harzards are tracked, current hazards can be displayed using the
1125
     simulator's `r' command.
1126
 
1127
          Caution: The code for this does not appear to be complete or
1128
          well tested, so users are advised not to use this option.
1129
 
1130
`dependstats = 0|1'
1131 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1132
     value 0.
1133 19 jeremybenn
 
1134
     If these values are calculated, the depencies can be displayed
1135
     using the simulator's `stat' command.
1136
 
1137
          Note: This field must be enabled, if execution execution flow
1138
          tracking (field `history') has been requested in the simulator
1139
          configuration section (*note Simulator Behavior: Simulator
1140
          Behavior.).
1141
 
1142
`sbuf_len = VALUE'
1143
     The length of the store buffer is set to VALUE, which must be no
1144 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1145
     warning.  Negative values will be treated as 0 with a warning.
1146
     Use 0 to disable the store buffer.
1147 19 jeremybenn
 
1148
     When the store buffer is active, stores are accumulated and
1149
     committed when I/O is idle.
1150
 
1151 100 julius
`hardfloat = 0|1'
1152
     If 1, hardfloat instructions are enabled. Default value 0.
1153 19 jeremybenn
 
1154 104 jeremybenn
 
1155 19 jeremybenn

1156
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1157
 
1158
3.3.2 Memory Configuration
1159
--------------------------
1160
 
1161 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1162 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1163 19 jeremybenn
 
1164 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1165
     controller. If a memory controller is enabled, then the standard
1166
     OpenRISC C libraries will initialize it to expect 64MB memory
1167
     blocks, and any memory declarations _must_ reflect this.  The
1168
     section describing memory controller configuration describes the
1169
     steps necessary for using smaller or larger memory sections (*note
1170
     Memory Controller Configuration: Memory Controller Configuration.).
1171
 
1172
     If a memory controller is _not_ enabled, then the standard C
1173
     library code will generate memory access errors.  The solution is
1174
     to declare an additional writable memory block, mimicing the memory
1175
     controller's register bank as follows.
1176
 
1177
          section memory
1178
            pattern = 0x00
1179
            type = unknown
1180
            name = "MC shadow"
1181
            baseaddr = 0x93000000
1182
            size     = 0x00000080
1183
            delayr = 2
1184
            delayw = 4
1185
          end
1186
 
1187
 
1188
The following parameters may be specified.
1189
 
1190 19 jeremybenn
`type=random|pattern|unknown|zero'
1191 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1192 19 jeremybenn
     default value is `unknown'.
1193
 
1194
    `random'
1195 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1196 19 jeremybenn
          random generator may be set using the `random_seed' field in
1197
          this section (see below), thus ensuring the same "random"
1198
          values are used each time.
1199
 
1200
    `pattern'
1201
          Set the memory values to be a pattern value, which is set
1202
          using the `pattern' field in this section (see below).
1203
 
1204
    `unknown'
1205 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1206 19 jeremybenn
          This option will yield faster initialization of the simulator.
1207
 
1208
    `zero'
1209 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1210 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1211
          such.
1212
 
1213
               Note: As a consequence, if the `pattern' field is
1214
               _subsequently_ specified in this section, the value in
1215
               that field will be used instead of zero to initialize
1216
               the memory.
1217
 
1218
 
1219
`random_seed = VALUE'
1220 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1221 19 jeremybenn
     has any effect for memory type `random'.
1222
 
1223
     The default value is -1, which means the seed will be set from a
1224
     call to the `time' function, thus ensuring different random values
1225 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1226 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1227
     values used in any particular run.
1228
 
1229
`pattern = VALUE'
1230 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1231
     default value is 0.  This only has any effect for memory type
1232
     `pattern'.  The least significant 8 bits of this value is used to
1233
     initialize each byte.  More than 8 bits can be specified, but will
1234 19 jeremybenn
     ignored with a warning.
1235
 
1236
          Tip: The default value, is equivalent to setting the memory
1237 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1238 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1239
          and not specifying a value for `pattern'.
1240
 
1241
`baseaddr = VALUE'
1242 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1243 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1244
     The default value is 0.
1245
 
1246
`size = VALUE'
1247 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1248
     be a multiple of 4 (i.e.  word aligned).  The default value is
1249
     1024.
1250 19 jeremybenn
 
1251
          Note: When allocating memory, the simulator will allocate the
1252
          nearest 2^n bytes greater than or equal to VALUE, and will not
1253
          notice memory misses in any part of the memory between VALUE
1254
          and the amount allocated.
1255
 
1256
          As a consequence users are strongly recommended to specify
1257 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1258 19 jeremybenn
          amount of memory is required, it should be specified as
1259
          separate, contiguous blocks, each of which is a power of 2 in
1260
          size.
1261
 
1262
`name = "TEXT"'
1263 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1264
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1265 19 jeremybenn
     `"anonymous memory block"'.
1266
 
1267
          Note: It is not clear that this information is currently ever
1268 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1269 19 jeremybenn
          command of the simulator ignores it.
1270
 
1271
`ce = VALUE'
1272 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1273 19 jeremybenn
     instance should have a unique chip enable index, which should be
1274 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1275 19 jeremybenn
     controller when identifying different memory instances.
1276
 
1277 98 jeremybenn
     There is no requirement to set  `ce' if a memory controller is not
1278
     enabled. The default value is -1 (invalid).
1279 19 jeremybenn
 
1280
`mc = VALUE'
1281 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1282 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1283
     for a memory controller (*note Memory Controller Configuration:
1284
     Memory Controller Configuration.).
1285
 
1286 98 jeremybenn
     There is no requirement to set  `mc' if a memory controller is not
1287
     enabled. Default value is 0, which is also the default value of a
1288
     memory controller `index' field.  This is suitable therefore for
1289
     designs with just one memory controller.
1290 19 jeremybenn
 
1291
`delayr = VALUE'
1292 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1293
     memory does not support reading.  Default value 1.  The simulator
1294 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1295
     count when reading from main memory.
1296
 
1297
`delayw = VALUE'
1298 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1299
     memory does not support writing.  Default value 1.  The simulator
1300 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1301
     count when writing to main memory.
1302
 
1303
`log = "FILE"'
1304
     If specified, `file' names a file for all memory accesses to be
1305 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1306 19 jeremybenn
     that the memory is not logged.
1307
 
1308
 
1309

1310
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1311
 
1312
3.3.3 Memory Management Configuration
1313
-------------------------------------
1314
 
1315
Memory Management Unit (MMU) configuration is described in `section
1316
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1317 82 jeremybenn
Each section should appear at most once.  The following parameters may
1318 19 jeremybenn
be specified.
1319
 
1320
`enabled = 0|1'
1321
     If 1 (true), the data or instruction (as appropriate) MMU is
1322 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1323 19 jeremybenn
 
1324
`nsets = VALUE'
1325
     Sets the number of data or instruction (as appropriate) TLB sets to
1326 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1327
     which do not fit these criteria are ignored with a warning.  The
1328 19 jeremybenn
     default value is 1.
1329
 
1330
`nways = VALUE'
1331
     Sets the number of data or instruction (as appropriate) TLB ways to
1332 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1333
     this range are ignored with a warning.  The default value is 1.
1334 19 jeremybenn
 
1335
`pagesize = VALUE'
1336
     The data or instruction (as appropriate) MMU page size is set to
1337 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1338
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1339 19 jeremybenn
 
1340
`entrysize = VALUE'
1341
     The data or instruction (as appropriate) MMU entry size is set to
1342 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1343
     of 2 are ignored with a warning.  The default value is 1.
1344 19 jeremybenn
 
1345
          Note: Or1ksim does not appear to use the `entrysize' parameter
1346 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1347 19 jeremybenn
          not seem to matter.
1348
 
1349
`ustates = VALUE'
1350
     The number of instruction usage states for the data or instruction
1351
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1352 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1353 19 jeremybenn
     value is 2.
1354
 
1355
          Note: Or1ksim does not appear to use the `ustates' parameter
1356 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1357 19 jeremybenn
          not seem to matter.
1358
 
1359
`hitdelay = VALUE'
1360
     Set the number of cycles a data or instruction (as appropriate) MMU
1361 82 jeremybenn
     hit costs.  Default value 1.
1362 19 jeremybenn
 
1363
`missdelay = VALUE'
1364
     Set the number of cycles a data or instruction (as appropriate) MMU
1365 82 jeremybenn
     miss costs.  Default value 1.
1366 19 jeremybenn
 
1367
 
1368

1369
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1370
 
1371
3.3.4 Cache Configuration
1372
-------------------------
1373
 
1374
Cache configuration is described in `section dc' (for the data cache)
1375 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1376
appear at most once.  The following parameters may be specified.
1377 19 jeremybenn
 
1378
`enabled = 0|1'
1379
     If 1 (true), the data or instruction (as appropriate) cache is
1380 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1381 19 jeremybenn
 
1382
`nsets = VALUE'
1383
     Sets the number of data or instruction (as appropriate) cache sets
1384
     to VALUE, which must be a power of two, not exceeding
1385
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1386 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1387
     both defined in the code to be 1024).  The default value is 1.
1388 19 jeremybenn
 
1389
`nways = VALUE'
1390
     Sets the number of data or instruction (as appropriate) cache ways
1391
     to VALUE, which must be a power of two, not exceeding
1392
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1393 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1394
     both defined in the code to be 32).  The default value is 1.
1395 19 jeremybenn
 
1396
`blocksize = VALUE'
1397
     The data or instruction (as appropriate) cache block size is set to
1398 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1399 19 jeremybenn
 
1400
`ustates = VALUE'
1401
     The number of instruction usage states for the data or instruction
1402
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1403
     The default value is 2.
1404
 
1405
`hitdelay = VALUE'
1406 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1407
     cache hit costs.  Default value 1.
1408 19 jeremybenn
 
1409
`missdelay = VALUE'
1410 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1411
     cache miss costs.  Default value 1.
1412 19 jeremybenn
 
1413
`load_hitdelay = VALUE'
1414 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1415
     costs.  Default value 2.
1416 19 jeremybenn
 
1417
`load_missdelay = VALUE'
1418 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1419
     miss costs.  Default value 2.
1420 19 jeremybenn
 
1421
`store_hitdelay = VALUE'
1422 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1423
     costs.  Default value 0.
1424 19 jeremybenn
 
1425
`store_missdelay = VALUE'
1426 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1427
     miss costs.  Default value 0.
1428 19 jeremybenn
 
1429
 
1430

1431
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1432
 
1433
3.3.5 Interrupt Configuration
1434
-----------------------------
1435
 
1436
Programmable Interrupt Controller (PIC) configuration is described in
1437 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1438
mechanism for handling multiple interrupt controllers.  The following
1439 19 jeremybenn
parameters may be specified.
1440
 
1441
`enabled = 0|1'
1442 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1443
 
1444 19 jeremybenn
 
1445
`edge_trigger = 0|1'
1446
     If 1 (true, the default), the programmable interrupt controller is
1447 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1448 19 jeremybenn
 
1449
 
1450

1451
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1452
 
1453
3.3.6 Power Management Configuration
1454
------------------------------------
1455
 
1456 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1457 19 jeremybenn
(which only happens when the power management unit is enabled) of
1458
setting the different bits in the power management Special Purpose
1459
Register (PMR, SPR 0x4000) is
1460
 
1461
`SDF (bit mask 0x0000000f)'
1462
     No effect - these bits are ignored
1463
 
1464
`DME (bit mask 0x00000010)'
1465
`SME (bit mask 0x00000020)'
1466
     Both these bits cause the processor to stop executing
1467 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1468 19 jeremybenn
     VAPI etc) carry on as normal.
1469
 
1470
`DCGE (bit mask 0x00000004)'
1471
     No effect - this bit is ignored
1472
 
1473
`SUME (bit mask 0x00000008)'
1474
     Enabling this bit causes a message to be printed, advising that the
1475
     processor is suspending and the simulator exits.
1476
 
1477
 
1478
On reset all bits are cleared.
1479
 
1480 82 jeremybenn
Power management configuration is described in `section pm'.  This
1481
section may appear at most once.  The following parameter may be
1482 19 jeremybenn
specified.
1483
 
1484
`enabled = 0|1'
1485 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1486
     is disabled.
1487 19 jeremybenn
 
1488
 
1489

1490
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1491
 
1492
3.3.7 Branch Prediction Configuration
1493
-------------------------------------
1494
 
1495
From examining the code base, it seems the branch prediction function
1496 82 jeremybenn
is not fully implemented.  At present the functionality seems
1497
restricted to collection of statistics.
1498 19 jeremybenn
 
1499 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1500
section may appear at most once.  The following parameters may be
1501 19 jeremybenn
specified.
1502
 
1503
`enabled = 0|1'
1504 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1505 19 jeremybenn
     is disabled.
1506
 
1507
`btic = 0|1'
1508
     If 1 (true), the branch target instruction cache model is enabled.
1509
     If 0 (the default), it is disabled.
1510
 
1511
`sbp_bf_fwd = 0|1'
1512 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1513 19 jeremybenn
 
1514
     instruction.
1515
 
1516
`sbp_bnf_fwd = 0|1'
1517 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1518
     If 0 (the default), do not use forward prediction for this
1519 19 jeremybenn
     instruction.
1520
 
1521
`hitdelay = VALUE'
1522 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1523 19 jeremybenn
     value 0.
1524
 
1525
`missdelay = VALUE'
1526 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1527 19 jeremybenn
     value 0.
1528
 
1529
 
1530

1531
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1532
 
1533
3.3.8 Debug Interface Configuration
1534
-----------------------------------
1535
 
1536
The debug unit and debug interface configuration is described in
1537 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1538 19 jeremybenn
parameters may be specified.
1539
 
1540
`enabled = 0|1'
1541 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1542 19 jeremybenn
     disabled.
1543
 
1544
          Note: This enables the functionality of the debug unit (its
1545 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1546
          external interface to the debug unit.  For that, see
1547 19 jeremybenn
          `gdb_enabled' and `rsp_enabled' below.
1548
 
1549
`rsp_enabled = 0|1'
1550
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1551
     provding an interface to an external GNU debugger, using the port
1552
     specified in the `rsp_port' field (see below), or the
1553 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1554 19 jeremybenn
     not started, and no external interface is provided.
1555
 
1556
     For more detailed information on the interface to the GNU Debugger
1557
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1558
     Practical Experience with the OpenRISC 1000 Architecture', by
1559
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1560
 
1561 82 jeremybenn
          Note: `rsp_enabled' may not be enabled with `gdb_enabled' (see
1562
          below).  If both are enabled, a warning is issued and only
1563
          the "Remote Serial Protocol" interface is enabled.
1564 19 jeremybenn
 
1565
`rsp_port = VALUE'
1566
     VALUE specifies the port to be used for the GDB "Remote Serial
1567 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1568
     51000.  If the value 0 is specified, Or1ksim will instead look for
1569 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1570
 
1571
          Tip: There is no registered port for Or1ksim "Remote Serial
1572 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1573
          users should adopt port values in the "Dynamic" or "Private"
1574
          port range, i.e.  49152-65535.
1575 19 jeremybenn
 
1576
`gdb_enabled = 0|1'
1577
     If 1 (true), the OpenRISC Remote JTAG protocol server is started,
1578
     provding an interface to an external GNU debugger, using the port
1579
     specified in the `server_port' field (see below), or the `or1ksim'
1580 82 jeremybenn
     TCP/IP service.  If 0 (the default), the server is not started,
1581
     and no external interface is provided.
1582 19 jeremybenn
 
1583
     For more detailed information on the interface to the GNU Debugger
1584
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1585
     Practical Experience with the OpenRISC 1000 Architecture', by
1586
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1587
 
1588
          Note: The OpenRISC Remote JTAG protocol is unique to
1589 82 jeremybenn
          OpenRISC, and remains only for backward compatibility.  New
1590 19 jeremybenn
          users should adopt the standard GDB "Remote Serial Protocol"
1591
          interface (see `rsp_enabled' above) providing access to a
1592
          wider range of GDB functionality.
1593
 
1594 82 jeremybenn
          Note: `gdb_enabled' may not be enabled with `rsp_enabled'.
1595
          If both are enabled, a warning is issued and only the "Remote
1596 19 jeremybenn
          Serial Protocol" interface is enabled.
1597
 
1598
`server_port = VALUE'
1599
     VALUE specifies the port to be used for the OpenRISC Rmote JTAG
1600 82 jeremybenn
     protocol interface to the GNU Debugger (GDB).  Default value
1601
     51000.  If the value 0 is specified, Or1ksim will instead look for
1602
     a TCP/IP service named `or1ksim'.
1603 19 jeremybenn
 
1604
          Tip: There is no registered port for Or1ksim Remote JTAG
1605 82 jeremybenn
          Interface or service `or1ksim'.  Good practice suggests users
1606 19 jeremybenn
          should adopt port values in the "Dynamic" or "Private" port
1607 82 jeremybenn
          range, i.e.  49152-65535.
1608 19 jeremybenn
 
1609
`vapi_id = VALUE'
1610
     VALUE specifies the value of the Verification API (VAPI) base
1611 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1612 19 jeremybenn
     Verification API, for more details.
1613
 
1614
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1615
     JTAG protocol transactions will be logged to the VAPI log file, if
1616 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
1617
     the debug unit.  No VAPI commands are sent, nor requests handled.
1618 19 jeremybenn
 
1619
 
1620

1621
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
1622
 
1623
3.4 Configuring Memory Mapped Peripherals
1624
=========================================
1625
 
1626 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1627 19 jeremybenn
(unlike other components) by default they are enabled.
1628
 
1629
* Menu:
1630
 
1631
* Memory Controller Configuration::
1632
* UART Configuration::
1633
* DMA Configuration::
1634
* Ethernet Configuration::
1635
* GPIO Configuration::
1636
* Display Interface Configuration::
1637
* Frame Buffer Configuration::
1638
* Keyboard Configuration::
1639
* Disc Interface Configuration::
1640
* Generic Peripheral Configuration::
1641
 
1642

1643
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
1644
 
1645
3.4.1 Memory Controller Configuration
1646
-------------------------------------
1647
 
1648
The memory controller used in Or1ksim is the component implemented at
1649 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
1650 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
1651 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1652
memory mapped component, which resides on the main OpenRISC Wishbone
1653
data bus.
1654 19 jeremybenn
 
1655 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
1656 19 jeremybenn
section may appear multiple times, specifying multiple memory
1657 98 jeremybenn
controllers.
1658 19 jeremybenn
 
1659 98 jeremybenn
     Caution: The standard OpenRISC C libraries will initialize the
1660
     memory controller to expect 64MB memory blocks, and any memory
1661
     declarations _must_ reflect this.
1662
 
1663
     If smaller memory blocks are declared with a memory controller,
1664
     then sufficient memory will not be allocated by Or1ksim, but out of
1665
     range memory accesses will not be trapped. For example declaring a
1666
     memory section from 0-4MB with a memory controller enabled would
1667
     mean that accesses between 4MB and 64MB would be permitted, but
1668
     having no allocated memory would likely cause a segmentation fault.
1669
 
1670
     If the user is determined to use smaller memories with the memory
1671
     controller, then custom initialization code must be provided, to
1672
     ensure the memory controller traps out-of-memory accesses.
1673
 
1674
The following parameters may be specified.
1675
 
1676 19 jeremybenn
`enabled = 0|1'
1677 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
1678
     0, it is disabled.
1679 19 jeremybenn
 
1680
          Note: The memory controller can effectively also be disabled
1681
          by setting an appropriate power on control register value
1682 82 jeremybenn
          (see below).  However this should only be used if it is
1683 19 jeremybenn
          desired to specifically model this behavior of the memory
1684
          controller, not as a way of disabling the memory controller
1685
          in general.
1686
 
1687
`baseaddr = VALUE'
1688
     Set the base address of the memory controller's memory mapped
1689 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
1690 19 jeremybenn
     sensible value.
1691
 
1692
     The memory controller has a 7 bit address bus, with a total of 19
1693
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1694
     addresses 0x50 through 0x7c are not used).
1695
 
1696
`poc = VALUE'
1697
     Specifies the value of the power on control register, The least
1698
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
1699
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
1700
     the type of memory connected (use 0 for a disabled interface, 1
1701
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
1702
     devices).
1703
 
1704
     If other bits are specified, they are ignored with a warning.
1705
 
1706
          Caution: The default value, 0, corresponds to a disabled
1707
          8-bit bus, and is likely not the most suitable value
1708
 
1709
`index = VALUE'
1710
     Specify the index of this memory controller amongst all the memory
1711 82 jeremybenn
     controllers.  This value should be unique for each memory
1712 19 jeremybenn
     controller, and is used to associate specific memories with the
1713
     controller, through the `mc' field in the `section memory'
1714
     configuration (*note Memory Configuration: Memory Configuration.).
1715
 
1716
     The default value, 0, is suitable when there is only one memory
1717
     controller.
1718
 
1719
 
1720

1721
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
1722
 
1723
3.4.2 UART Configuration
1724
------------------------
1725
 
1726
The UART implemented in Or1ksim follows the specification of the
1727 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
1728 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
1729
 
1730
The component provides a number of interfaces to emulate the behavior
1731
of an external terminal connected to the UART.
1732
 
1733 82 jeremybenn
UART configuration is described in `section uart'.  This section may
1734
appear multiple times, specifying multiple UARTs.  The following
1735 19 jeremybenn
parameters may be specified.
1736
 
1737
`enabled = 0|1'
1738 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
1739 19 jeremybenn
     disabled.
1740
 
1741
`baseaddr = VALUE'
1742
     Set the base address of the UART's memory mapped registers to
1743 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1744 19 jeremybenn
 
1745
     The UART has a 3 bit address bus, with a total of 8 8-bit
1746
     registers, at addresses 0x0 through 0x7.
1747
 
1748
`channel = "TYPE:ARGS"'
1749
     Specify the channel representing the terminal connected to the UART
1750
     Rx & Tx pins.
1751
 
1752
    `channel="file:`rxfile',`txfile'"'
1753
          Read input characters from the file `rxfile' and write output
1754
          characters to the file `txfile' (which will be created if
1755
          required).
1756
 
1757
    `channel="xterm:ARGS"'
1758
          Create an xterm on startup, write UART Tx traffic to the
1759
          xterm and take Rx traffic from the keyboard when the xterm
1760 82 jeremybenn
          window is selected.  Additional arguments to the xterm
1761
          command (for example specifying window size may be specified
1762
          in ARGS, or this may be left blank.
1763 19 jeremybenn
 
1764
    `channel="tcp:VALUE"'
1765
          Open the TCP/IP port specified by VALUE and read and write
1766
          UART traffic from and to it.
1767
 
1768
          Typically a telnet session is connected to the other end of
1769
          this port.
1770
 
1771
               Tip: There is no registered port for Or1ksim telnet UART
1772 82 jeremybenn
               connection.  Priviledged access is required to read
1773 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
1774
               Instead users should use port values in the "Dynamic" or
1775 82 jeremybenn
               "Private" port range, i.e.  49152-65535.
1776 19 jeremybenn
 
1777
    `channel="fd:`rxfd',`txfd'"'
1778
          Read and write characters from and to the existing open
1779
          numerical file descriptors, file `rxfd' and `txfd'.
1780
 
1781
    `channel="tty:device=/dev/ttyS0,baud=9600"'
1782
          Read and write characters from and to a physical serial port.
1783
          The precise device (shown here as `/dev/ttyS0') may vary from
1784
          machine to machine.
1785
 
1786
 
1787
     The default value for this field is `"xterm:"'.
1788
 
1789
`irq = VALUE'
1790 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
1791 19 jeremybenn
 
1792
`16550 = 0|1'
1793 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
1794
     default), it has the functionality of a 16450.  The principal
1795 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
1796
 
1797
`jitter = VALUE'
1798
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
1799 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
1800 19 jeremybenn
 
1801
          Note: This functionality has yet to be implemented, so this
1802
          parameter has no effect.
1803
 
1804
`vapi_id = VALUE'
1805
     VALUE specifies the value of the Verification API (VAPI) base
1806 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
1807 19 jeremybenn
     Verification API, for more details, which details the use of the
1808
     VAPI with the UART.
1809
 
1810
 
1811

1812
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
1813
 
1814
3.4.3 DMA Configuration
1815
-----------------------
1816
 
1817
The DMA controller used in Or1ksim is the component implemented at
1818 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
1819 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
1820 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1821
memory mapped component, which resides on the main OpenRISC Wishbone
1822
data bus.  The present implementation is incomplete, intended only to
1823
support the Ethernet interface (*note Ethernet Configuration::),
1824
although the Ethernet interface is not yet completed.
1825 19 jeremybenn
 
1826 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
1827
appear multiple times, specifying multiple DMA controllers.  The
1828 19 jeremybenn
following parameters may be specified.
1829
 
1830
`enabled = 0|1'
1831 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
1832
     it is disabled.
1833 19 jeremybenn
 
1834
`baseaddr = VALUE'
1835
     Set the base address of the DMA's memory mapped registers to
1836 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1837 19 jeremybenn
 
1838
     The DMA controller has a 10 bit address bus, with a total of 253
1839 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
1840
     0x010 control the overall behavior of the DMA controller.  There
1841
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
1842
     channels available.  Addresses 0x014 through 0x01c are not used.
1843 19 jeremybenn
 
1844
`irq = VALUE'
1845 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
1846 19 jeremybenn
     0.
1847
 
1848
`vapi_id = VALUE'
1849
     VALUE specifies the value of the Verification API (VAPI) base
1850 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
1851 19 jeremybenn
     API: Verification API, for more details, which details the use of
1852
     the VAPI with the DMA controller.
1853
 
1854
 
1855

1856
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
1857
 
1858
3.4.4 Ethernet Configuration
1859
----------------------------
1860
 
1861
The Ethernet MAC used in Or1ksim is the component implemented at
1862 98 jeremybenn
OpenCores, and found in the top level SVN directory, `ethmac'.  It also
1863
forms part of the OpenRISC SoC, ORPSoC.  It is described in the
1864 19 jeremybenn
document `Ethernet IP Core Specification' by Igor Mohor, which can be
1865 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1866
which resides on the main OpenRISC Wishbone data bus.
1867 19 jeremybenn
 
1868 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
1869
section may appear multiple times, specifying multiple Ethernet
1870
interfaces.  The following parameters may be specified.
1871 19 jeremybenn
 
1872
`enabled = 0|1'
1873 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
1874
     is disabled.
1875 19 jeremybenn
 
1876
`baseaddr = VALUE'
1877
     Set the base address of the MAC's memory mapped registers to
1878 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1879 19 jeremybenn
 
1880
     The Ethernet MAC has a 7-bit address bus, with a total of 21
1881 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
1882 19 jeremybenn
 
1883
          Note: The Ethernet specification describes a Tx control
1884 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
1885
          is not implemented in the Or1ksim model.
1886 19 jeremybenn
 
1887
`dma = VALUE'
1888
     VALUE specifies the DMA controller with which this Ethernet is
1889 82 jeremybenn
     associated.  The default value is 0.
1890 19 jeremybenn
 
1891
          Note: Support for external DMA is not provided in the current
1892 82 jeremybenn
          implementation, and this value is ignored.  In any case there
1893 19 jeremybenn
          is no equivalent field to which this can be matched in the
1894
          current DMA component implementation (*note DMA
1895
          Configuration: DMA Configuration.).
1896
 
1897
`irq = VALUE'
1898 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
1899 19 jeremybenn
 
1900
`rtx_type = 0|1'
1901
     If 1 (true) use a socket interface to the Ethernet (see parameter
1902 82 jeremybenn
     `sockif' below).  If 0 (the default), use a file interface,
1903
     reading and writing from and to the files specified in the
1904
     `rxfile' and `txfile' parameters (see below).
1905 19 jeremybenn
 
1906
          Note: By default the socket interface is not provided in
1907 82 jeremybenn
          Or1ksim.  If it is required, this must be requested when
1908 19 jeremybenn
          configuring, by use of the `--enable-ethphy' option to
1909
          `configure'.
1910
 
1911
               configure --target=or32-uclinux --enable-ethphy ...
1912
 
1913
`rx_channel = RXVALUE'
1914
`tx_channel = TXVALUE'
1915
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
1916 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
1917 19 jeremybenn
 
1918
          Note: As noted above, support for external DMA is not
1919
          provided in the current implementation, and so these values
1920
          are ignored.
1921
 
1922
`rxfile = "RXFILE"'
1923
`txfile = "TXFILE"'
1924
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
1925
     as input and TXFILE specifies the fie to use as output.
1926
 
1927 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
1928
     packet length (32 bits), followed by that many bytes of data.
1929
     Once the input file is empty, the Ethernet MAC behaves as though
1930
     there were no data on the Ethernet.  The default values of these
1931 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
1932
 
1933 82 jeremybenn
     The input file must exist and be readable.  The output file must be
1934
     writable and will be created if necessary.  If either of these
1935 19 jeremybenn
     conditions is not met, a warning will be given.
1936
 
1937
`sockif = "SERVICE"'
1938
     When `rtx_type' is 1 (see above), SERVICE specifies the service to
1939 82 jeremybenn
     use for communication.  This may be TCP/IP or UDP/IP.  The default
1940 19 jeremybenn
     value of this parameter is `"or1ksim_eth"'.
1941
 
1942
`vapi_id = VALUE'
1943
     VALUE specifies the value of the Verification API (VAPI) base
1944 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
1945 19 jeremybenn
     Verification API, for more details, which details the use of the
1946
     VAPI with the DMA controller.
1947
 
1948
 
1949

1950
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
1951
 
1952
3.4.5 GPIO Configuration
1953
------------------------
1954
 
1955
The GPIO used in Or1ksim is the component implemented at OpenCores, and
1956 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
1957 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
1958 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
1959 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
1960
 
1961 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
1962
appear multiple times, specifying multiple GPIO devices.  The following
1963 19 jeremybenn
parameters may be specified.
1964
 
1965
`enabled = 0|1'
1966 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
1967 19 jeremybenn
     disabled.
1968
 
1969
`baseaddr = VALUE'
1970
     Set the base address of the GPIO's memory mapped registers to
1971 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1972 19 jeremybenn
 
1973
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
1974
     registers, although the number of bits that are actively used
1975 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
1976 19 jeremybenn
 
1977
`irq = VALUE'
1978 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
1979 19 jeremybenn
 
1980
`vapi_id = VALUE'
1981
     VALUE specifies the value of the Verification API (VAPI) base
1982 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
1983 19 jeremybenn
     Verification API, for more details, which details the use of the
1984 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
1985 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
1986
     but deprecated.
1987
 
1988
 
1989

1990
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
1991
 
1992
3.4.6 Display Interface Configuration
1993
-------------------------------------
1994
 
1995
Or1ksim models a VGA interface to an external monitor.  The VGA
1996
controller used in Or1ksim is the component implemented at OpenCores,
1997 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
1998 82 jeremybenn
for the optional hardware cursors.  It is described in the document
1999 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
2000 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2001
which resides on the main OpenRISC Wishbone data bus.
2002 19 jeremybenn
 
2003
The current implementation provides only functionality to dump the
2004
screen to a file at intervals.
2005
 
2006 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
2007 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
2008
The following parameters may be specified.
2009
 
2010
`enabled = 0|1'
2011 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
2012 19 jeremybenn
     disabled.
2013
 
2014
`baseaddr = VALUE'
2015
     Set the base address of the VGA controller's memory mapped
2016 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2017 19 jeremybenn
     sensible value.
2018
 
2019
     The VGA controller has a 12-bit address bus, with 7 32-bit
2020
     registers, at addresses 0x000 through 0x018, and two color lookup
2021 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2022 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2023
     are not used.
2024
 
2025
`irq = VALUE'
2026 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2027 19 jeremybenn
     0.
2028
 
2029
`refresh_rate = VALUE'
2030 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2031 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2032
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2033
     50 times per simulated second.
2034
 
2035
`txfile = "FILE"'
2036
     FILE specifies the base of the filename for screen dumps.
2037
     Successive screen dumps will be in BMP format, in files with the
2038
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2039 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2040 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2041
     supported for this parameter, but deprecated.
2042
 
2043
 
2044

2045
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2046
 
2047
3.4.7 Frame Buffer Configuration
2048
--------------------------------
2049
 
2050 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2051 19 jeremybenn
     configuration fields are described here, but the component should
2052 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2053 19 jeremybenn
     to make screen dumps to file.
2054
 
2055 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2056
may appear multiple times, specifying multiple frame buffers.  The
2057 19 jeremybenn
following parameters may be specified.
2058
 
2059
`enabled = 0|1'
2060 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2061 19 jeremybenn
     is disabled.
2062
 
2063
`baseaddr = VALUE'
2064
     Set the base address of the frame buffer's memory mapped registers
2065 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2066
     value.
2067 19 jeremybenn
 
2068
     The frame buffer has an 121-bit address bus, with 4 32-bit
2069
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2070 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2071 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2072
 
2073
`refresh_rate = VALUE'
2074 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2075 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2076
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2077
     50 times per simulated second.
2078
 
2079
`txfile = "FILE"'
2080
     FILE specifies the base of the filename for screen dumps.
2081
     Successive screen dumps will be in BMP format, in files with the
2082
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2083 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2084 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2085
     supported for this parameter, but deprecated.
2086
 
2087
 
2088

2089
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2090
 
2091
3.4.8 Keyboard Configuration (PS2)
2092
----------------------------------
2093
 
2094 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2095 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2096 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2097
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2098 19 jeremybenn
standard, this is presumably what is expected with this device.
2099
 
2100
The implementation only provides for keyboard support, which is
2101 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2102 19 jeremybenn
 
2103
     Caution: A standard i8042 device has two registers at addresses
2104 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2105
     suggests that the Or1ksim component places these registers at
2106
     addresses 0x00 and 0x04.
2107 19 jeremybenn
 
2108
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2109
     implements the i8042 device driver, anticipating these registers
2110 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2111 19 jeremybenn
     code will work.
2112
 
2113
     This component should be used with caution.
2114
 
2115 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2116
appear multiple times, specifying multiple keyboard interfaces.  The
2117 19 jeremybenn
following parameters may be specified.
2118
 
2119
`enabled = 0|1'
2120 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2121 19 jeremybenn
     disabled.
2122
 
2123
`baseaddr = VALUE'
2124
     Set the base address of the keyboard's memory mapped registers to
2125 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2126 19 jeremybenn
 
2127
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2128
     registers, at addresses 0x000 and 0x004.
2129
 
2130
          Caution: As noted above, a standard Intel 8042 interface
2131
          would expect to find these registers at locations 0x60 and
2132
          0x64, thus requiring at least a 7-bit bus.
2133
 
2134
`irq = VALUE'
2135 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2136 19 jeremybenn
     value 0.
2137
 
2138
`rxfile = "FILE"'
2139
     `file' specifies a file containing raw key stroke data, which
2140 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2141 19 jeremybenn
     `"kbd_in"'.
2142
 
2143
 
2144

2145
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2146
 
2147
3.4.9 Disc Interface Configuration
2148
----------------------------------
2149
 
2150
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2151
IDE Controller) component implemented at OpenCores, and found in the
2152 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2153 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2154 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2155
which resides on the main OpenRISC Wishbone data bus.
2156 19 jeremybenn
 
2157 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2158
may appear multiple times, specifying multiple disc controllers.  The
2159 19 jeremybenn
following parameters may be specified.
2160
 
2161
`enabled = 0|1'
2162 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2163 19 jeremybenn
     0, it is disabled.
2164
 
2165
`baseaddr = VALUE'
2166
     Set the base address of the ATA/ATAPI interface's memory mapped
2167 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2168 19 jeremybenn
     sensible value.
2169
 
2170
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2171 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2172
     ATA/ATAPI interface selected (see `dev_id' below), not all
2173
     registers will be available.
2174 19 jeremybenn
 
2175
`irq = VALUE'
2176 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2177 19 jeremybenn
     value 0.
2178
 
2179
`dev_id = 1|2|3'
2180
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2181 82 jeremybenn
     interface to model.  The default value is 1.
2182 19 jeremybenn
 
2183
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2184
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2185
     registers and the `RXD'/`TXD' registers.
2186
 
2187
`rev = VALUE'
2188
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2189 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2190
     be in the range 0-15.  Larger values are truncated with a warning.
2191 19 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2192
     forms bits 24-27.
2193
 
2194
`pio_mode0_t1 = VALUE'
2195
`pio_mode0_t2 = VALUE'
2196
`pio_mode0_t4 = VALUE'
2197
`pio_mode0_teoc = VALUE'
2198
     These parameters specify the timings for use with Programmed
2199 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2200 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2201 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2202 19 jeremybenn
     they do, they will be ignored with a warning.
2203
 
2204
     See the ATA/ATAPI-5 specification for explanations of each of these
2205 82 jeremybenn
     timing parameters.  The default values are:
2206 19 jeremybenn
 
2207
          pio_mode0_t1   =  6
2208
          pio_mode0_t2   = 28
2209
          pio_mode0_t4   =  2
2210
          pio_mode0_teoc = 23
2211
 
2212
`dma_mode0_tm = VALUE'
2213
`dma_mode0_td = VALUE'
2214
`dma_mode0_teoc = VALUE'
2215
     These parameters specify the timings for use with DMA transfers.
2216
     They are specified as the number of clock cycles - 2, rounded up
2217
     to the next highest integer, or zero if that would be negative.
2218 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2219
     ignored with a warning.
2220 19 jeremybenn
 
2221
     See the ATA/ATAPI-5 specification for explanations of each of these
2222 82 jeremybenn
     timing parameters.  The default values are:
2223 19 jeremybenn
 
2224
          dma_mode0_tm   =  4
2225
          dma_mode0_td   = 21
2226
          dma_mode0_teoc = 21
2227
 
2228
 
2229
3.4.9.1 ATA/ATAPI Device Configuration
2230
......................................
2231
 
2232 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2233 19 jeremybenn
device subsection is introduced by
2234
 
2235
     device VALUE
2236
 
2237 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2238
ends with `enddevice'.  Note that if the same device number is
2239
specified more than once, the previous values will be overwritten.
2240
Within the `device' subsection, the following parameters may appear:
2241 19 jeremybenn
 
2242
`type = VALUE'
2243
     VALUEspecifies the type of device: 0 (the default) for "not
2244
     connected", 1 for hard disk simulated in a file and 2 for local
2245
     system hard disk.
2246
 
2247
`file = "FILENAME"'
2248
     `filename' specifies the file to be used for a simulated ATA
2249 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2250 19 jeremybenn
     `"ata-FileN"', where N is the device number.
2251
 
2252
`size = VALUE'
2253
     VALUE specifies the size of a simulated ATA device if the file
2254 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2255 19 jeremybenn
 
2256
`packet = 0|1'
2257 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2258 19 jeremybenn
     default), do not implement the PACKET command feature set.
2259
 
2260
`firmware = "STR"'
2261
     Firmware to report in response to the "Identify Device" command.
2262
     Default `"02207031"'.
2263
 
2264
`heads = VALUE'
2265 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2266 19 jeremybenn
     heads.
2267
 
2268
`sectors = VALUE'
2269 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2270 19 jeremybenn
 
2271
`mwdma = 0|1|2|-1'
2272 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2273 19 jeremybenn
     disable.
2274
 
2275
`pio = 0|1|2|3|4'
2276 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2277 19 jeremybenn
 
2278
 
2279

2280
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2281
 
2282
3.4.10 Generic Peripheral Configuration
2283
---------------------------------------
2284
 
2285
When used as a library (*note Simulator Library: Simulator Library.),
2286
Or1ksim makes provision for any additional peripheral to be implemented
2287 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2288
generates "upcall"s to an external handler.  This interface can support
2289 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2290
for OSCI SystemC (see `http://www.systemc.org').
2291
 
2292
Generic peripheral configuration is described in `section generic'.
2293
This section may appear multiple times, specifying multiple external
2294 82 jeremybenn
peripherals.  The following parameters may be specified.
2295 19 jeremybenn
 
2296
`enabled = 0|1'
2297 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2298 19 jeremybenn
     0, it is disabled.
2299
 
2300
`baseaddr = VALUE'
2301
     Set the base address of the generic peripheral's memory mapped
2302 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2303 19 jeremybenn
     sensible value.
2304
 
2305
     The size of the memory mapped register space is controlled by the
2306
     `size' paramter, described below.
2307
 
2308
`size = VALUE'
2309
     Set the size of the generic peripheral's memory mapped register
2310 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2311 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2312
     parameter `baseaddr' (see above) will be directed to the external
2313
     interface.
2314
 
2315 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2316
     value is zero.  If VALUE is not an exact power of two, accesses to
2317 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2318
     generate a warning, and have no effect (reads will return zero).
2319
 
2320
`name = "STR"'
2321 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2322 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2323 82 jeremybenn
     reporting its status.  The default value is
2324 19 jeremybenn
     `"anonymous external peripheral"'.
2325
 
2326
`byte_enabled = 0|1'
2327
`hw_enabled = 0|1'
2328
`word_enabled = 0|1'
2329
     If 1 (true, the default), these parameters respectively enable the
2330 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2331 19 jeremybenn
     accesses of that width will fail.
2332
 
2333
 
2334

2335
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2336
 
2337
4 Interactive Command Line
2338
**************************
2339
 
2340
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2341 82 jeremybenn
provides the user with an interactive command line.  The commands
2342 19 jeremybenn
available, which may not be abbreviated, are:
2343
 
2344
`q'
2345
     Exit the simulator
2346
 
2347
`r'
2348 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2349 19 jeremybenn
     just executed and next to be executed instructions symbolically
2350
     and the state of the flag in the Supervision Register.
2351
 
2352
`t'
2353
     Execute the next instruction and then display register/instruction
2354
     information as with the `r' command (see above).
2355
 
2356
`run NUM [ hush ]'
2357 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2358 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2359
     above) _unless_ `hush' is specified.
2360
 
2361
`pr REG VALUE'
2362
     Patch register REG with VALUE.
2363
 
2364
`dm FROMADDR [ TOADDR ]'
2365 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2366
     not given, 64 bytes are displayed, starting at FROMADDR.
2367 19 jeremybenn
 
2368
          Caution: The output from this command is broken (a bug).
2369 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2370 19 jeremybenn
          instead of printing out the address at the start of each row,
2371
          it prints the address (of the first of the 16 bytes) before
2372
          _each_ byte.
2373
 
2374
`de FROMADDR [ TOADDR ]'
2375 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2376 19 jeremybenn
     given, 16 instructions are disassembled.
2377
 
2378
     The disassembly is entirely numerical, and gives no symbolic
2379
     information.
2380
 
2381
`pm ADDR VALUE'
2382
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2383
 
2384
`pc VALUE'
2385
     Patch the program counter with VALUE.
2386
 
2387
`cm FROMADDR TOADDR SIZE'
2388
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2389
 
2390
`break ADDR'
2391
     Toggle the breakpoint set at ADDR.
2392
 
2393
`breaks'
2394
     List all set breakpoints
2395
 
2396
`reset'
2397 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2398
     so execution will restart from the reset vector location, 0x100.
2399 19 jeremybenn
 
2400
`hist'
2401
     If saving the execution history has been configured (*note
2402
     Simulator Behavior: Simulator Behavior.), display the execution
2403
     history.
2404
 
2405
`stall'
2406
     Stall the processor, so that control is passed to the debug unit.
2407 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2408 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2409
     debuggers such as GDB.
2410
 
2411
`unstall'
2412 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2413
     This command is useful when debugging the JTAG interface, used by
2414 19 jeremybenn
     debuggers such as GDB.
2415
 
2416
`stats CATEGORY | clear'
2417
     Print the statistics for the given CATEGORY, if available, or
2418 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2419 19 jeremybenn
 
2420
    1
2421
          Miscellaneous statistics: branch predictions (if branch
2422
          predictions are enabled), branch target cache model (if
2423
          enabled), cache (if enbaled), MMU (if enabled) and number of
2424
          addtional load & store cycles.
2425
 
2426
          *Note Configuring the OpenRisc Achitectural Components: Core
2427
          OpenRISC Configuration, for details of how to enable these
2428
          various features.
2429
 
2430
    2
2431 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2432 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2433
 
2434
    3
2435 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2436 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2437
 
2438
    4
2439 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2440 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2441
          Configuration.).
2442
 
2443
    5
2444 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2445 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2446
 
2447
    6
2448 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2449 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2450
 
2451
 
2452
`info'
2453
     Display detailed information about the simulator configuration.
2454
     This is quite a lengthy about, because all MMU TLB information is
2455
     displayed.
2456
 
2457
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2458
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2459 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2460 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2461 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2462 19 jeremybenn
 
2463
     To save to a file, use the redirection function (described after
2464
     this table, below).
2465
 
2466
`dh FROMADDR [ TOADDR ]'
2467
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2468 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2469 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2470
 
2471
     To save to a file, use the redirection function (described after
2472
     this table, below).
2473
 
2474
`setdbch'
2475 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2476 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2477
     channels on the command line.
2478
 
2479
`set SECTION PARAM = VALUE'
2480
     Set the configuration parameter PARA in section SECTION to VALUE.
2481
     *Note Configuration: Configuration, for details of configuration
2482
     parameters and their settings.
2483
 
2484
`debug'
2485 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2486 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2487
     this parameter.
2488
 
2489
          Caution: This is effectively enabling or disabling the debug
2490 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2491 19 jeremybenn
          However using the remote debug interface while the debug unit
2492
          is disabled will lead to undefined behavior and likely crash
2493
          Or1ksim
2494
 
2495
`cuc'
2496
     Enter the the Custom Unit Compiler command prompt (*note CUC
2497
     Configuration: CUC Configuration.).
2498
 
2499
          Caution: The CUC must be properly configured, for this to
2500 82 jeremybenn
          succeed.  In particular a timing file must be available and
2501
          readable.  Otherwise Or1ksim will crash.
2502 19 jeremybenn
 
2503
`help'
2504
     Print out brief information about each command available.
2505
 
2506
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2507 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2508 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2509
     Profiling Utility.).
2510
 
2511
`profile [-vhcq] [-g FILE]'
2512 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2513
     usage as the standalone command (*note Profiling Utility:
2514
     Profiling Utility.).
2515 19 jeremybenn
 
2516
 
2517
For all commands, it is possible to redirect the output to a file, by
2518
using the redirection operator, `>'.
2519
 
2520
     COMMAND > FILENAME
2521
 
2522
This is particularly useful for commands dumping a large amount of
2523
output, such as `dv'.
2524
 
2525
     Caution: Unfortunately there is a serious bug with the redirection
2526 82 jeremybenn
     operator.  It does not return output to standard output after the
2527
     command completes.  Until this bug is fixed, file redirection
2528 19 jeremybenn
     should not be used.
2529
 
2530

2531
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2532
 
2533
5 Verification API (VAPI)
2534
*************************
2535
 
2536
The Verification API (VAPI) provides a TCP/IP interface to allow
2537 82 jeremybenn
components of the simulation to be controlled externally.  The
2538
interface is polled for new requests on each simulated clock cycle.
2539
Components within the simulator may send responses to such requests.
2540 19 jeremybenn
 
2541 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2542
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2543
with a single piece of data (also a 32 bit integer).  On the send side,
2544
it provides for sending a single VAPI ID and data.  However there is no
2545
explicit command-response structure.  Some components just accept
2546
requests (e.g.  to set values), some just generate sends (to report
2547 19 jeremybenn
values), and some do both.
2548
 
2549
Each component has a base ID (32 bit) and its commands will start from
2550 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2551
amongst components.  Request commands will be directed to the component
2552 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2553
 
2554
Thus if there are two components with base IDs of 0x200 and 0x300, and
2555
a request with VAPI ID of 0x203 is received, it will be directed to the
2556
first component as its command #3.
2557
 
2558
The results of VAPI interactions are logged (by default in `vapi.log'
2559
unless an alternative is specified in `section vapi').
2560
 
2561
Currently the following components support VAPI:
2562
 
2563
Debug Unit
2564
     Although the Debug Unit can specify a base VAPI ID, it is not used
2565
     to send commands or receive requests.
2566
 
2567
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2568
     exchanges are logged in the VAPI log file.
2569
 
2570
UART
2571
     If a base VAPI ID is specified, the UART sends details of any
2572
     chars or break characters sent, with dteails of the line control
2573
     register etc encoded in the data packet sent.
2574
 
2575
     This supports a single VAPI command request, but encodes a
2576
     sub-command in the top 8 bits of the associated data.
2577
 
2578
    `0x00'
2579
          This stuffs the least significant 8 bits of the data into the
2580
          serial register of the UART and the next 8 bits into the line
2581
          control register, effectively providing control of the next
2582
          character to be sent or received.
2583
 
2584
    `0x01'
2585
          The divisor latch bytes are set from the least significant 16
2586
          bits of the data.
2587
 
2588
    `0x02'
2589
          The line control register is set from bits 15-8 of the data.
2590
 
2591
    `0x03'
2592
          The UART skew is set from the least significant 16 bits of
2593
          the data
2594
 
2595
    `0x04'
2596
          If the 16th most significant bit of the data is 1, start
2597 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
2598
          are sent or cleared after the number of UART clock divider
2599
          ticks specified by the data (immediately if the data is zero).
2600 19 jeremybenn
 
2601
 
2602
DMA
2603
     Although the DMA unit supports a base VAPI ID in its configuration
2604
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
2605
     implemented.
2606
 
2607
Ethernet
2608 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
2609 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
2610 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
2611 19 jeremybenn
     VAPI requests.
2612
 
2613
    `ETH_VAPI_DATA (0)'
2614
 
2615
    `ETH_VAPI_CTRL (0)'
2616
 
2617
GPIO
2618
     If a base VAPI ID is specified, the GPIO sends out on its base
2619
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
2620
     VAPI ID) any changes in outputs.
2621
 
2622 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
2623 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
2624
     GPIO.
2625
 
2626
    `GPIO_VAPI_DATA (0)'
2627
          Set the next input to the commands data field
2628
 
2629
    `GPIO_VAPI_AUX (1)'
2630
          Set the GPIO auxiliary inputs to the data field
2631
 
2632
    `GPIO_VAPI_CLOCK (2)'
2633
          Add an external GPIO clock trigger of period specified in the
2634
          data field.
2635
 
2636
    `GPIO_VAPI_RGPIO_OE (3)'
2637
          Set the GPIO output enable to the data field
2638
 
2639
    `GPIO_VAPI_RGPIO_INTE (4)'
2640
          Set the next interrupt to the data field
2641
 
2642
    `GPIO_VAPI_RGPIO_PTRIG (5)'
2643
          Set the next trigger to the data field
2644
 
2645
    `GPIO_VAPI_RGPIO_AUX (6)'
2646
          Set the next auxiliary input to the data field
2647
 
2648
    `GPIO_VAPI_RGPIO_CTRL (7)'
2649
          Set th next control input to the data field
2650
 
2651
 
2652
 
2653

2654
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
2655
 
2656
6 A Guide to Or1ksim Internals
2657
******************************
2658
 
2659 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
2660 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
2661 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
2662
Linux manual page for `etags'.  A tag file can be created with:
2663 19 jeremybenn
 
2664
     make tags
2665
 
2666
* Menu:
2667
 
2668
* Coding Conventions::
2669
* Global Data Structures::
2670
* Concepts::
2671
* Internal Debugging::
2672 104 jeremybenn
* Regression Testing::
2673 19 jeremybenn
 
2674

2675
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
2676
 
2677
6.1 Coding Conventions for Or1ksim
2678
==================================
2679
 
2680
This chapter provides some guidelines for coding, to facilitate
2681
extensions to Or1ksim
2682
 
2683
_GNU Coding Standard_
2684
     Code should follow the GNU coding standard for C
2685 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
2686 19 jeremybenn
     through the `indent' program.
2687
 
2688
_`#include' headers_
2689
     All C source code files should include `config.h' before any other
2690
     file.
2691
 
2692
     This should be followed by inclusion of any system headers (but see
2693
     the comments about portability and `port.h' below) and then by any
2694
     Or1ksim package headers.
2695
 
2696
     If `port.h' is required, it should be the first package header to
2697
     be included after the system headers.
2698
 
2699
     All C source code and header files should directly include any
2700 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
2701
     other header having already included it.  The two exceptions are
2702 19 jeremybenn
 
2703
       1. All header files may assume that `config.h' has already been
2704
          included.
2705
 
2706
       2. System headers which impose portability problems should be
2707
          included by using the package header `port.h', rather than
2708 82 jeremybenn
          the system headers themselves.  This is the case for code
2709 19 jeremybenn
          requiring
2710
 
2711
             * `strndup' (from `string.h')
2712
 
2713
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
2714
 
2715
             * `isblank' (from `ctype.h')
2716
 
2717
 
2718
 
2719
_`#include' files once only_
2720
     All include files should be protected by `#ifndef' to ensure their
2721 82 jeremybenn
     definitions are only included once.  For instance a header file
2722 19 jeremybenn
     `X-Y.H' should surround its contents with:
2723
 
2724
          #ifndef X_Y__H
2725
          #define X_Y__H
2726
 
2727
          
2728
 
2729
          #endif  /* X_Y__H */
2730
 
2731
_Avoid `typedef'_
2732
     The GNU coding style for C does not have a clear way to distinguish
2733 82 jeremybenn
     between user type name and user variables.  For this reason
2734 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
2735 82 jeremybenn
     defined types.  This makes the code much easier to read.
2736 19 jeremybenn
 
2737
     There are some `typedef' declarations in the `argtable2' library
2738
     and the ELF and COFF headers, because this code is taken from
2739
     other places.
2740
 
2741
     Within Or1ksim legacy uses of `typedef' have largely been purged,
2742
     except in the Custom Unit Compiler (*note Custom Unit Compiler
2743
     (CUC) Configuration: CUC Configuration.).
2744
 
2745
     The remaining uses of `typedef' occur in two places:
2746
 
2747
        * `port/port.h' defines types to replace those in header files
2748
          that are not available (character functions, string
2749
          duplication, integer types).
2750
 
2751
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
2752
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
2753
          and signed register (`orreg_t') values.
2754
 
2755
 
2756
     Where new types are defined, they should appear in one of these two
2757 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
2758
     `arch.h' should always have the suffix `_h'.
2759 19 jeremybenn
 
2760
_Don't begin names with underscore_
2761
     Names beginning with `_' are intended to be part of the C
2762 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
2763 19 jeremybenn
 
2764
_Keep Non-global top level entities static_
2765
     All top level entities (functions, variables), which are not
2766
     explicitly part of a global interface should be declared static.
2767
     This ensures that unwanted connections are not inadvertently built
2768
     across the program.
2769
 
2770
_Use of `inline'_
2771 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
2772 19 jeremybenn
     out for themselves what is best in this respect.
2773
 
2774
_Initialization_
2775 82 jeremybenn
     All data structures should be explicitly initialized.  In
2776
     particular code should not rely on static data structures being
2777
     initialized to zero.
2778 19 jeremybenn
 
2779
     The rationale is that in future static data structures may become
2780 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
2781 19 jeremybenn
     historically.
2782
 
2783
     A specific case is with new peripherals, which should always
2784
     include a `start' function to pre-initialize all configuration
2785
     parameters to sensible defaults
2786
 
2787
_Configuration Validation_
2788
     All configuration values should be validated, preferably when
2789
     encountered, if not when the `section' is closed, or otherwise at
2790
     run time when the parameter is first used.
2791
 
2792
 
2793

2794
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
2795
 
2796
6.2 Global Data Structures
2797
==========================
2798
 
2799
`config'
2800
     The global variable `config' of type `struct config' holds the
2801
     configuration data for some of the Or1ksim components which are
2802 82 jeremybenn
     always present.  At present the components are:
2803 19 jeremybenn
 
2804
        * The simulator defined in `section sim' (*note Simulator
2805
          Configuration: Simulator Configuration.).
2806
 
2807
        * The Verification API (VAPI) defined  in `section vapi' (*note
2808
          Verification API (VAPI) Configuration: Verification API
2809
          Configuration.).
2810
 
2811
        * The Custom Unit Compiler (CUC), defined in `section cuc'
2812
          (*note Custom Unit Compiler (CUC) Configuration: CUC
2813
          Configuration.).
2814
 
2815
        * The CPU, defined in `section cpu' (*note CPU Configuration:
2816
          CPU Configuration.).
2817
 
2818
        * The data cache (but not the instruction cache), defined in
2819
          `section dc' (*note Cache Configuration: Cache
2820
          Configuration.).
2821
 
2822
        * The power management unit, defined in `section pm' (*note
2823
          Power Management Configuration: Power Management
2824
          Configuration.).
2825
 
2826
        * The programmable interrupt controller, defined in
2827
          `section pic' (*note Interrupt Configuration: Interrupt
2828
          Configuration.).
2829
 
2830
        * Branch prediciton, defined in `section bpb' (*note Branch
2831
          Prediction Configuration: Branch Prediction Configuration.).
2832
 
2833
        * The debug unit, defined in `section debug' (*note Debug
2834
          Interface Configuration: Debug Interface Configuration.).
2835
 
2836
 
2837
     This struct is made of a collection of structs, one for each
2838 82 jeremybenn
     component.  For example the simulator configuration is held in
2839 19 jeremybenn
     `config.sim'.
2840
 
2841
`config'
2842
     This is a linked list of data structures holding configuration data
2843
     for all sections which are not held in the main `config' data
2844 82 jeremybenn
     structure.  In general these are components (such as peripherals
2845
     and memory) which may occur multiple times.  However it also
2846
     handles some architectural components which may occur only once,
2847
     such as the memory management units, the instruction cache, the
2848
     interrupt controller and branch prediction.
2849 19 jeremybenn
 
2850
`runtime'
2851
     The global variable `runtime' of type `struct runtime' holds all
2852 82 jeremybenn
     the runtime information about the simulation.  To access this
2853 19 jeremybenn
     variable, `sim-config.h' must be included.
2854
 
2855
     This struct is itself made of 3 other structs, `cpu' (for CPU run
2856
     time state), `vapi' (for Verification API state) and `cuc' (for
2857
     Custom Unit Compiler state).
2858
 
2859
 
2860

2861
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
2862
 
2863
6.3 Concepts
2864
============
2865
 
2866
_Output Redirection_
2867 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
2868 19 jeremybenn
     should be explicitly written to this stream, or may use the
2869
     `PRINTF' macro, which will write its arguments to this output
2870
     stream.
2871
 
2872
_Reset Hooks_
2873
     Any peripheral may register a routine to be called when the the
2874
     processor is reset by calling `reg_sim_reset', providing a
2875 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
2876 19 jeremybenn
     that function will be called with the data stucture pointer as
2877
     argument.
2878
 
2879
 
2880

2881 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
2882 19 jeremybenn
 
2883
6.4 Internal Debugging
2884
======================
2885
 
2886
The function `debug' is like `printf', but with an extra first
2887 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
2888
the simulator configuration (*note Simulator Behavior: Simulator
2889
Behavior.) is greater than or equal to this value, the remaining
2890
arguments are printed to the current output stream (*note Output
2891
Redirection: Output Redirection.).
2892 19 jeremybenn
 
2893

2894 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
2895
 
2896
6.5 Regression Testing
2897
======================
2898
 
2899
Or1ksim now includes a regression test suite for both standalone and
2900
library usage as described earlier (*note Building and Installing:
2901
Build and Install.).  Running the tests requires that the OpenRISC
2902
toolchain and DejaGNU are both installed.
2903
 
2904
Tests are written using `expect', a derivative of TCL.  Documentation
2905
of DejaGnu, `expect' and TCL are freely available on the Web.  The
2906
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
2907
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
2908
provides a concise introduction.
2909
 
2910
All test code is found in the `testsuite' directory.  The key files and
2911
directories used are as follows.
2912
 
2913
`global-conf.exp'
2914
     This is the global DejaGNU configuration file used to set up
2915
     parameters common to all tests.  If the user has the environment
2916
     varialbe `DEJAGNU' defined, it will be used instead, but this is
2917
     not recommended.
2918
 
2919
`Makefile.am'
2920
     This is the top level `automake' file for the testsuite.  The only
2921
     changes likely to be needed here is additional local cleanup of
2922
     files created by new tests.
2923
 
2924
`README'
2925
     This contains details of all the tests
2926
 
2927
`config'
2928
     This contains DejaGnu board configurations.  Since the tests are
2929
     generally run on a Unix host, this should just contain `Unix.exp'.
2930
 
2931
`lib'
2932
     This contains DejaGnu tool specific configurations.  "Tool" has a
2933
     specific meaning in DejaGNU, referring just to a grouping of
2934
     tests.  In this case there are two such "tools", "or1ksim" and
2935
     "libsim" for tests of the standalone tool and tests of the library.
2936
 
2937
     Corresponding to this, there are two tool specific configuration
2938
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
2939
     procedures for common use among the tests.
2940
 
2941
`libsim.tests'
2942
`or1ksim.tests'
2943
     These are the directories of tests of the Or1ksim library.  They
2944
     also include Or1ksim configuration files and each has a
2945
     `Makefile.am' file.  `Makefile.am' should be updated whenever
2946
     files are added to this directory, to ensure they are included in
2947
     the distribution.
2948
 
2949
`test-code'
2950
     These are all the test programs to be compiled on the host (each
2951
     in its own directory).  In general these are programs to support
2952
     testing of the library, and build various programs linking in the
2953
     library.
2954
 
2955
`test-code'
2956
     These are all the test programs to be compiled with the OpenRISC
2957
     tool chain to run with either standalone Or1ksim or the library.
2958
     This directory includes its own `configure.ac', since it must set
2959
     up a separate tool chain based on the target, not the host.
2960
 
2961
 
2962
To add a new test needs the following steps.
2963
 
2964
   * Put new host C code in its own directory within `test-code'. Add
2965
     the directory to the existing `Makefile.am' in the `test-code'
2966
     directory and create a `Makefile.am' in the new directory to drive
2967
     building the test program(s). Don't forget to add the new
2968
     `Makefile' to the top level `configure.ac' so it gets generated.
2969
     Not all tests require code here.
2970
 
2971
   * Put new target C code in its own directory within
2972
     `test-code-or1k'. Once again modify & create `Makefile.am'. this
2973
     time though modify the `configure.ac' in the `test-code-or1k' so
2974
     the `Makefile' gets generated. The existing programs provide
2975
     examples to start from, including custom linker scripts where
2976
     needed.
2977
 
2978
   * Add one or more tests and configuration files to the relevant
2979
     "tool" test directory. Use the existing tests as templates. They
2980
     make heavy use of the `expect'/TCL procedures in the `config'
2981
     directory to facilitate driving the tests.
2982
 
2983
 
2984

2985 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
2986
 
2987
7 GNU Free Documentation License
2988
********************************
2989
 
2990
                      Version 1.2, November 2002
2991
 
2992
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
2993
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
2994
 
2995
     Everyone is permitted to copy and distribute verbatim copies
2996
     of this license document, but changing it is not allowed.
2997
 
2998
  0. PREAMBLE
2999
 
3000
     The purpose of this License is to make a manual, textbook, or other
3001
     functional and useful document "free" in the sense of freedom: to
3002
     assure everyone the effective freedom to copy and redistribute it,
3003
     with or without modifying it, either commercially or
3004
     noncommercially.  Secondarily, this License preserves for the
3005
     author and publisher a way to get credit for their work, while not
3006
     being considered responsible for modifications made by others.
3007
 
3008
     This License is a kind of "copyleft", which means that derivative
3009
     works of the document must themselves be free in the same sense.
3010
     It complements the GNU General Public License, which is a copyleft
3011
     license designed for free software.
3012
 
3013
     We have designed this License in order to use it for manuals for
3014
     free software, because free software needs free documentation: a
3015
     free program should come with manuals providing the same freedoms
3016
     that the software does.  But this License is not limited to
3017
     software manuals; it can be used for any textual work, regardless
3018
     of subject matter or whether it is published as a printed book.
3019
     We recommend this License principally for works whose purpose is
3020
     instruction or reference.
3021
 
3022
  1. APPLICABILITY AND DEFINITIONS
3023
 
3024
     This License applies to any manual or other work, in any medium,
3025
     that contains a notice placed by the copyright holder saying it
3026
     can be distributed under the terms of this License.  Such a notice
3027
     grants a world-wide, royalty-free license, unlimited in duration,
3028
     to use that work under the conditions stated herein.  The
3029
     "Document", below, refers to any such manual or work.  Any member
3030
     of the public is a licensee, and is addressed as "you".  You
3031
     accept the license if you copy, modify or distribute the work in a
3032
     way requiring permission under copyright law.
3033
 
3034
     A "Modified Version" of the Document means any work containing the
3035
     Document or a portion of it, either copied verbatim, or with
3036
     modifications and/or translated into another language.
3037
 
3038
     A "Secondary Section" is a named appendix or a front-matter section
3039
     of the Document that deals exclusively with the relationship of the
3040
     publishers or authors of the Document to the Document's overall
3041
     subject (or to related matters) and contains nothing that could
3042
     fall directly within that overall subject.  (Thus, if the Document
3043
     is in part a textbook of mathematics, a Secondary Section may not
3044
     explain any mathematics.)  The relationship could be a matter of
3045
     historical connection with the subject or with related matters, or
3046
     of legal, commercial, philosophical, ethical or political position
3047
     regarding them.
3048
 
3049
     The "Invariant Sections" are certain Secondary Sections whose
3050
     titles are designated, as being those of Invariant Sections, in
3051
     the notice that says that the Document is released under this
3052
     License.  If a section does not fit the above definition of
3053
     Secondary then it is not allowed to be designated as Invariant.
3054
     The Document may contain zero Invariant Sections.  If the Document
3055
     does not identify any Invariant Sections then there are none.
3056
 
3057
     The "Cover Texts" are certain short passages of text that are
3058
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3059
     that says that the Document is released under this License.  A
3060
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3061
     be at most 25 words.
3062
 
3063
     A "Transparent" copy of the Document means a machine-readable copy,
3064
     represented in a format whose specification is available to the
3065
     general public, that is suitable for revising the document
3066
     straightforwardly with generic text editors or (for images
3067
     composed of pixels) generic paint programs or (for drawings) some
3068
     widely available drawing editor, and that is suitable for input to
3069
     text formatters or for automatic translation to a variety of
3070
     formats suitable for input to text formatters.  A copy made in an
3071
     otherwise Transparent file format whose markup, or absence of
3072
     markup, has been arranged to thwart or discourage subsequent
3073
     modification by readers is not Transparent.  An image format is
3074
     not Transparent if used for any substantial amount of text.  A
3075
     copy that is not "Transparent" is called "Opaque".
3076
 
3077
     Examples of suitable formats for Transparent copies include plain
3078
     ASCII without markup, Texinfo input format, LaTeX input format,
3079
     SGML or XML using a publicly available DTD, and
3080
     standard-conforming simple HTML, PostScript or PDF designed for
3081
     human modification.  Examples of transparent image formats include
3082
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3083
     can be read and edited only by proprietary word processors, SGML or
3084
     XML for which the DTD and/or processing tools are not generally
3085
     available, and the machine-generated HTML, PostScript or PDF
3086
     produced by some word processors for output purposes only.
3087
 
3088
     The "Title Page" means, for a printed book, the title page itself,
3089
     plus such following pages as are needed to hold, legibly, the
3090
     material this License requires to appear in the title page.  For
3091
     works in formats which do not have any title page as such, "Title
3092
     Page" means the text near the most prominent appearance of the
3093
     work's title, preceding the beginning of the body of the text.
3094
 
3095
     A section "Entitled XYZ" means a named subunit of the Document
3096
     whose title either is precisely XYZ or contains XYZ in parentheses
3097
     following text that translates XYZ in another language.  (Here XYZ
3098
     stands for a specific section name mentioned below, such as
3099
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3100
     To "Preserve the Title" of such a section when you modify the
3101
     Document means that it remains a section "Entitled XYZ" according
3102
     to this definition.
3103
 
3104
     The Document may include Warranty Disclaimers next to the notice
3105
     which states that this License applies to the Document.  These
3106
     Warranty Disclaimers are considered to be included by reference in
3107
     this License, but only as regards disclaiming warranties: any other
3108
     implication that these Warranty Disclaimers may have is void and
3109
     has no effect on the meaning of this License.
3110
 
3111
  2. VERBATIM COPYING
3112
 
3113
     You may copy and distribute the Document in any medium, either
3114
     commercially or noncommercially, provided that this License, the
3115
     copyright notices, and the license notice saying this License
3116
     applies to the Document are reproduced in all copies, and that you
3117
     add no other conditions whatsoever to those of this License.  You
3118
     may not use technical measures to obstruct or control the reading
3119
     or further copying of the copies you make or distribute.  However,
3120
     you may accept compensation in exchange for copies.  If you
3121
     distribute a large enough number of copies you must also follow
3122
     the conditions in section 3.
3123
 
3124
     You may also lend copies, under the same conditions stated above,
3125
     and you may publicly display copies.
3126
 
3127
  3. COPYING IN QUANTITY
3128
 
3129
     If you publish printed copies (or copies in media that commonly
3130
     have printed covers) of the Document, numbering more than 100, and
3131
     the Document's license notice requires Cover Texts, you must
3132
     enclose the copies in covers that carry, clearly and legibly, all
3133
     these Cover Texts: Front-Cover Texts on the front cover, and
3134
     Back-Cover Texts on the back cover.  Both covers must also clearly
3135
     and legibly identify you as the publisher of these copies.  The
3136
     front cover must present the full title with all words of the
3137
     title equally prominent and visible.  You may add other material
3138
     on the covers in addition.  Copying with changes limited to the
3139
     covers, as long as they preserve the title of the Document and
3140
     satisfy these conditions, can be treated as verbatim copying in
3141
     other respects.
3142
 
3143
     If the required texts for either cover are too voluminous to fit
3144
     legibly, you should put the first ones listed (as many as fit
3145
     reasonably) on the actual cover, and continue the rest onto
3146
     adjacent pages.
3147
 
3148
     If you publish or distribute Opaque copies of the Document
3149
     numbering more than 100, you must either include a
3150
     machine-readable Transparent copy along with each Opaque copy, or
3151
     state in or with each Opaque copy a computer-network location from
3152
     which the general network-using public has access to download
3153
     using public-standard network protocols a complete Transparent
3154
     copy of the Document, free of added material.  If you use the
3155
     latter option, you must take reasonably prudent steps, when you
3156
     begin distribution of Opaque copies in quantity, to ensure that
3157
     this Transparent copy will remain thus accessible at the stated
3158
     location until at least one year after the last time you
3159
     distribute an Opaque copy (directly or through your agents or
3160
     retailers) of that edition to the public.
3161
 
3162
     It is requested, but not required, that you contact the authors of
3163
     the Document well before redistributing any large number of
3164
     copies, to give them a chance to provide you with an updated
3165
     version of the Document.
3166
 
3167
  4. MODIFICATIONS
3168
 
3169
     You may copy and distribute a Modified Version of the Document
3170
     under the conditions of sections 2 and 3 above, provided that you
3171
     release the Modified Version under precisely this License, with
3172
     the Modified Version filling the role of the Document, thus
3173
     licensing distribution and modification of the Modified Version to
3174
     whoever possesses a copy of it.  In addition, you must do these
3175
     things in the Modified Version:
3176
 
3177
       A. Use in the Title Page (and on the covers, if any) a title
3178
          distinct from that of the Document, and from those of
3179
          previous versions (which should, if there were any, be listed
3180
          in the History section of the Document).  You may use the
3181
          same title as a previous version if the original publisher of
3182
          that version gives permission.
3183
 
3184
       B. List on the Title Page, as authors, one or more persons or
3185
          entities responsible for authorship of the modifications in
3186
          the Modified Version, together with at least five of the
3187
          principal authors of the Document (all of its principal
3188
          authors, if it has fewer than five), unless they release you
3189
          from this requirement.
3190
 
3191
       C. State on the Title page the name of the publisher of the
3192
          Modified Version, as the publisher.
3193
 
3194
       D. Preserve all the copyright notices of the Document.
3195
 
3196
       E. Add an appropriate copyright notice for your modifications
3197
          adjacent to the other copyright notices.
3198
 
3199
       F. Include, immediately after the copyright notices, a license
3200
          notice giving the public permission to use the Modified
3201
          Version under the terms of this License, in the form shown in
3202
          the Addendum below.
3203
 
3204
       G. Preserve in that license notice the full lists of Invariant
3205
          Sections and required Cover Texts given in the Document's
3206
          license notice.
3207
 
3208
       H. Include an unaltered copy of this License.
3209
 
3210
       I. Preserve the section Entitled "History", Preserve its Title,
3211
          and add to it an item stating at least the title, year, new
3212
          authors, and publisher of the Modified Version as given on
3213
          the Title Page.  If there is no section Entitled "History" in
3214
          the Document, create one stating the title, year, authors,
3215
          and publisher of the Document as given on its Title Page,
3216
          then add an item describing the Modified Version as stated in
3217
          the previous sentence.
3218
 
3219
       J. Preserve the network location, if any, given in the Document
3220
          for public access to a Transparent copy of the Document, and
3221
          likewise the network locations given in the Document for
3222
          previous versions it was based on.  These may be placed in
3223
          the "History" section.  You may omit a network location for a
3224
          work that was published at least four years before the
3225
          Document itself, or if the original publisher of the version
3226
          it refers to gives permission.
3227
 
3228
       K. For any section Entitled "Acknowledgements" or "Dedications",
3229
          Preserve the Title of the section, and preserve in the
3230
          section all the substance and tone of each of the contributor
3231
          acknowledgements and/or dedications given therein.
3232
 
3233
       L. Preserve all the Invariant Sections of the Document,
3234
          unaltered in their text and in their titles.  Section numbers
3235
          or the equivalent are not considered part of the section
3236
          titles.
3237
 
3238
       M. Delete any section Entitled "Endorsements".  Such a section
3239
          may not be included in the Modified Version.
3240
 
3241
       N. Do not retitle any existing section to be Entitled
3242
          "Endorsements" or to conflict in title with any Invariant
3243
          Section.
3244
 
3245
       O. Preserve any Warranty Disclaimers.
3246
 
3247
     If the Modified Version includes new front-matter sections or
3248
     appendices that qualify as Secondary Sections and contain no
3249
     material copied from the Document, you may at your option
3250
     designate some or all of these sections as invariant.  To do this,
3251
     add their titles to the list of Invariant Sections in the Modified
3252
     Version's license notice.  These titles must be distinct from any
3253
     other section titles.
3254
 
3255
     You may add a section Entitled "Endorsements", provided it contains
3256
     nothing but endorsements of your Modified Version by various
3257
     parties--for example, statements of peer review or that the text
3258
     has been approved by an organization as the authoritative
3259
     definition of a standard.
3260
 
3261
     You may add a passage of up to five words as a Front-Cover Text,
3262
     and a passage of up to 25 words as a Back-Cover Text, to the end
3263
     of the list of Cover Texts in the Modified Version.  Only one
3264
     passage of Front-Cover Text and one of Back-Cover Text may be
3265
     added by (or through arrangements made by) any one entity.  If the
3266
     Document already includes a cover text for the same cover,
3267
     previously added by you or by arrangement made by the same entity
3268
     you are acting on behalf of, you may not add another; but you may
3269
     replace the old one, on explicit permission from the previous
3270
     publisher that added the old one.
3271
 
3272
     The author(s) and publisher(s) of the Document do not by this
3273
     License give permission to use their names for publicity for or to
3274
     assert or imply endorsement of any Modified Version.
3275
 
3276
  5. COMBINING DOCUMENTS
3277
 
3278
     You may combine the Document with other documents released under
3279
     this License, under the terms defined in section 4 above for
3280
     modified versions, provided that you include in the combination
3281
     all of the Invariant Sections of all of the original documents,
3282
     unmodified, and list them all as Invariant Sections of your
3283
     combined work in its license notice, and that you preserve all
3284
     their Warranty Disclaimers.
3285
 
3286
     The combined work need only contain one copy of this License, and
3287
     multiple identical Invariant Sections may be replaced with a single
3288
     copy.  If there are multiple Invariant Sections with the same name
3289
     but different contents, make the title of each such section unique
3290
     by adding at the end of it, in parentheses, the name of the
3291
     original author or publisher of that section if known, or else a
3292
     unique number.  Make the same adjustment to the section titles in
3293
     the list of Invariant Sections in the license notice of the
3294
     combined work.
3295
 
3296
     In the combination, you must combine any sections Entitled
3297
     "History" in the various original documents, forming one section
3298
     Entitled "History"; likewise combine any sections Entitled
3299
     "Acknowledgements", and any sections Entitled "Dedications".  You
3300
     must delete all sections Entitled "Endorsements."
3301
 
3302
  6. COLLECTIONS OF DOCUMENTS
3303
 
3304
     You may make a collection consisting of the Document and other
3305
     documents released under this License, and replace the individual
3306
     copies of this License in the various documents with a single copy
3307
     that is included in the collection, provided that you follow the
3308
     rules of this License for verbatim copying of each of the
3309
     documents in all other respects.
3310
 
3311
     You may extract a single document from such a collection, and
3312
     distribute it individually under this License, provided you insert
3313
     a copy of this License into the extracted document, and follow
3314
     this License in all other respects regarding verbatim copying of
3315
     that document.
3316
 
3317
  7. AGGREGATION WITH INDEPENDENT WORKS
3318
 
3319
     A compilation of the Document or its derivatives with other
3320
     separate and independent documents or works, in or on a volume of
3321
     a storage or distribution medium, is called an "aggregate" if the
3322
     copyright resulting from the compilation is not used to limit the
3323
     legal rights of the compilation's users beyond what the individual
3324
     works permit.  When the Document is included in an aggregate, this
3325
     License does not apply to the other works in the aggregate which
3326
     are not themselves derivative works of the Document.
3327
 
3328
     If the Cover Text requirement of section 3 is applicable to these
3329
     copies of the Document, then if the Document is less than one half
3330
     of the entire aggregate, the Document's Cover Texts may be placed
3331
     on covers that bracket the Document within the aggregate, or the
3332
     electronic equivalent of covers if the Document is in electronic
3333
     form.  Otherwise they must appear on printed covers that bracket
3334
     the whole aggregate.
3335
 
3336
  8. TRANSLATION
3337
 
3338
     Translation is considered a kind of modification, so you may
3339
     distribute translations of the Document under the terms of section
3340
     4.  Replacing Invariant Sections with translations requires special
3341
     permission from their copyright holders, but you may include
3342
     translations of some or all Invariant Sections in addition to the
3343
     original versions of these Invariant Sections.  You may include a
3344
     translation of this License, and all the license notices in the
3345
     Document, and any Warranty Disclaimers, provided that you also
3346
     include the original English version of this License and the
3347
     original versions of those notices and disclaimers.  In case of a
3348
     disagreement between the translation and the original version of
3349
     this License or a notice or disclaimer, the original version will
3350
     prevail.
3351
 
3352
     If a section in the Document is Entitled "Acknowledgements",
3353
     "Dedications", or "History", the requirement (section 4) to
3354
     Preserve its Title (section 1) will typically require changing the
3355
     actual title.
3356
 
3357
  9. TERMINATION
3358
 
3359
     You may not copy, modify, sublicense, or distribute the Document
3360
     except as expressly provided for under this License.  Any other
3361
     attempt to copy, modify, sublicense or distribute the Document is
3362
     void, and will automatically terminate your rights under this
3363
     License.  However, parties who have received copies, or rights,
3364
     from you under this License will not have their licenses
3365
     terminated so long as such parties remain in full compliance.
3366
 
3367
 10. FUTURE REVISIONS OF THIS LICENSE
3368
 
3369
     The Free Software Foundation may publish new, revised versions of
3370
     the GNU Free Documentation License from time to time.  Such new
3371
     versions will be similar in spirit to the present version, but may
3372
     differ in detail to address new problems or concerns.  See
3373
     `http://www.gnu.org/copyleft/'.
3374
 
3375
     Each version of the License is given a distinguishing version
3376
     number.  If the Document specifies that a particular numbered
3377
     version of this License "or any later version" applies to it, you
3378
     have the option of following the terms and conditions either of
3379
     that specified version or of any later version that has been
3380
     published (not as a draft) by the Free Software Foundation.  If
3381
     the Document does not specify a version number of this License,
3382
     you may choose any version ever published (not as a draft) by the
3383
     Free Software Foundation.
3384
 
3385
ADDENDUM: How to use this License for your documents
3386
====================================================
3387
 
3388
To use this License in a document you have written, include a copy of
3389
the License in the document and put the following copyright and license
3390
notices just after the title page:
3391
 
3392
       Copyright (C)  YEAR  YOUR NAME.
3393
       Permission is granted to copy, distribute and/or modify this document
3394
       under the terms of the GNU Free Documentation License, Version 1.2
3395
       or any later version published by the Free Software Foundation;
3396
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3397
       Texts.  A copy of the license is included in the section entitled ``GNU
3398
       Free Documentation License''.
3399
 
3400
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3401
replace the "with...Texts." line with this:
3402
 
3403
         with the Invariant Sections being LIST THEIR TITLES, with
3404
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3405
         being LIST.
3406
 
3407
If you have Invariant Sections without Cover Texts, or some other
3408
combination of the three, merge those two alternatives to suit the
3409
situation.
3410
 
3411
If your document contains nontrivial examples of program code, we
3412
recommend releasing these examples in parallel under your choice of
3413
free software license, such as the GNU General Public License, to
3414
permit their use in free software.
3415
 
3416

3417
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3418
 
3419
Index
3420
*****
3421
 
3422
 
3423
* Menu:
3424
3425
* --cumulative:                          Profiling Utility.   (line  26)
3426
* --debug-config:                        Standalone Simulator.
3427
                                                              (line  48)
3428 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3429 104 jeremybenn
                                                              (line 133)
3430 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3431 104 jeremybenn
                                                              (line  98)
3432 19 jeremybenn
* --disable-debug:                       Configuring the Build.
3433 104 jeremybenn
                                                              (line 126)
3434 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3435 104 jeremybenn
                                                              (line  59)
3436 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3437 104 jeremybenn
                                                              (line  75)
3438 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3439 104 jeremybenn
                                                              (line  30)
3440 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3441 104 jeremybenn
                                                              (line  69)
3442 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3443 104 jeremybenn
                                                              (line 132)
3444 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3445 104 jeremybenn
                                                              (line  97)
3446 19 jeremybenn
* --enable-debug:                        Configuring the Build.
3447 104 jeremybenn
                                                              (line 125)
3448 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3449 104 jeremybenn
                                                              (line  58)
3450 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3451 104 jeremybenn
                                                              (line  37)
3452 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3453
                                                              (line  77)
3454
* --enable-ov-flag:                      Configuring the Build.
3455 104 jeremybenn
                                                              (line  74)
3456 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3457
                                                              (line  74)
3458
* --enable-profiling:                    Configuring the Build.
3459 104 jeremybenn
                                                              (line  29)
3460 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3461 104 jeremybenn
                                                              (line  68)
3462 19 jeremybenn
* --file:                                Standalone Simulator.
3463
                                                              (line  24)
3464
* --filename:                            Memory Profiling Utility.
3465
                                                              (line  51)
3466
* --generate:                            Profiling Utility.   (line  34)
3467
* --group:                               Memory Profiling Utility.
3468
                                                              (line  47)
3469
* --help:                                Standalone Simulator.
3470
                                                              (line  20)
3471
* --help (memory profiling utility):     Memory Profiling Utility.
3472
                                                              (line  22)
3473
* --help (profiling utility):            Profiling Utility.   (line  22)
3474
* --interactive:                         Standalone Simulator.
3475
                                                              (line  54)
3476
* --mode:                                Memory Profiling Utility.
3477
                                                              (line  26)
3478
* --nosrv:                               Standalone Simulator.
3479
                                                              (line  32)
3480
* --quiet:                               Profiling Utility.   (line  30)
3481
* --srv:                                 Standalone Simulator.
3482
                                                              (line  40)
3483
* --strict-npc:                          Standalone Simulator.
3484
                                                              (line  57)
3485
* --version:                             Standalone Simulator.
3486
                                                              (line  16)
3487
* --version (memory profiling utility):  Memory Profiling Utility.
3488
                                                              (line  17)
3489
* --version (profiling utility):         Profiling Utility.   (line  17)
3490
* -c:                                    Profiling Utility.   (line  26)
3491
* -d:                                    Standalone Simulator.
3492
                                                              (line  48)
3493
* -f <1>:                                Memory Profiling Utility.
3494
                                                              (line  51)
3495
* -f:                                    Standalone Simulator.
3496
                                                              (line  24)
3497
* -g <1>:                                Memory Profiling Utility.
3498
                                                              (line  47)
3499
* -g:                                    Profiling Utility.   (line  34)
3500
* -h:                                    Standalone Simulator.
3501
                                                              (line  20)
3502
* -h (memory profiling utility):         Memory Profiling Utility.
3503
                                                              (line  22)
3504
* -h (profiling utility):                Profiling Utility.   (line  22)
3505
* -i:                                    Standalone Simulator.
3506
                                                              (line  54)
3507
* -m:                                    Memory Profiling Utility.
3508
                                                              (line  26)
3509
* -q:                                    Profiling Utility.   (line  30)
3510
* -v:                                    Standalone Simulator.
3511
                                                              (line  16)
3512
* -v (memory profiling utility):         Memory Profiling Utility.
3513
                                                              (line  17)
3514
* -v (profiling utility):                Profiling Utility.   (line  17)
3515
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3516
                                                              (line  49)
3517
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3518
                                                              (line  55)
3519
* 0x02 UART VAPI sub-command (UART verification): Verification API.
3520
                                                              (line  59)
3521
* 0x03 UART VAPI sub-command (UART verification): Verification API.
3522
                                                              (line  62)
3523
* 0x04 UART VAPI sub-command (UART verification): Verification API.
3524
                                                              (line  66)
3525
* 16550 (UART configuration):            UART Configuration.  (line  73)
3526 82 jeremybenn
* all tests enabled:                     Configuring the Build.
3527 104 jeremybenn
                                                              (line 133)
3528 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
3529 104 jeremybenn
                                                              (line 126)
3530 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
3531
                                                              (line   6)
3532
* ATA/ATAPI device configuration:        Disc Interface Configuration.
3533
                                                              (line  88)
3534
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
3535
                                                              (line  32)
3536
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
3537
                                                              (line  22)
3538
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
3539
* baseaddr (Ethernet configuration):     Ethernet Configuration.
3540
                                                              (line  22)
3541
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
3542
                                                              (line  20)
3543
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
3544
                                                              (line  22)
3545
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
3546
* baseaddr (keyboard configuration):     Keyboard Configuration.
3547
                                                              (line  36)
3548
* baseaddr (memory configuration):       Memory Configuration.
3549 98 jeremybenn
                                                              (line  87)
3550 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
3551 98 jeremybenn
                                                              (line  46)
3552 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
3553
* baseaddr (VGA configuration):          Display Interface Configuration.
3554
                                                              (line  26)
3555
* blocksize (cache configuration):       Cache Configuration. (line  29)
3556
* BPB configuration:                     Branch Prediction Configuration.
3557
                                                              (line   6)
3558
* branch prediction configuration:       Branch Prediction Configuration.
3559
                                                              (line   6)
3560
* break (Interactive CLI):               Interactive Command Line.
3561
                                                              (line  57)
3562
* breakpoint list (Interactive CLI):     Interactive Command Line.
3563
                                                              (line  60)
3564
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
3565
                                                              (line  57)
3566
* breaks (Interactive CLI):              Interactive Command Line.
3567
                                                              (line  60)
3568
* btic (branch prediction configuration): Branch Prediction Configuration.
3569
                                                              (line  19)
3570
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3571
                                                              (line  48)
3572
* cache configuration:                   Cache Configuration. (line   6)
3573
* calling_convention (CUC configuration): CUC Configuration.  (line  34)
3574
* ce (memory configuration):             Memory Configuration.
3575 98 jeremybenn
                                                              (line 117)
3576 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
3577
* channel (UART configuration):          UART Configuration.  (line  29)
3578
* clear breakpoint (Interactive CLI):    Interactive Command Line.
3579
                                                              (line  57)
3580 82 jeremybenn
* clkcycle (simulator configuration):    Simulator Behavior.  (line 103)
3581 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
3582
                                                              (line  54)
3583
* command line for Or1ksim standalone use: Standalone Simulator.
3584
                                                              (line   6)
3585
* complex model:                         Configuring the Build.
3586 104 jeremybenn
                                                              (line  37)
3587 19 jeremybenn
* config:                                Global Data Structures.
3588
                                                              (line   7)
3589
* config.bpb:                            Global Data Structures.
3590
                                                              (line  37)
3591
* config.cpu:                            Global Data Structures.
3592
                                                              (line  22)
3593
* config.cuc:                            Global Data Structures.
3594
                                                              (line  18)
3595
* config.dc:                             Global Data Structures.
3596
                                                              (line  25)
3597
* config.debug:                          Global Data Structures.
3598
                                                              (line  40)
3599
* config.pic:                            Global Data Structures.
3600
                                                              (line  33)
3601
* config.pm:                             Global Data Structures.
3602
                                                              (line  29)
3603
* config.sim:                            Global Data Structures.
3604
                                                              (line  11)
3605
* config.vapi:                           Global Data Structures.
3606
                                                              (line  14)
3607
* configuration dynamic structure:       Global Data Structures.
3608
                                                              (line  49)
3609
* configuration file structure:          Configuration File Format.
3610
                                                              (line   6)
3611
* configuration global structure:        Global Data Structures.
3612
                                                              (line   7)
3613
* configuration info (Interactive CLI):  Interactive Command Line.
3614
                                                              (line 119)
3615
* configuration of generic peripherals:  Generic Peripheral Configuration.
3616
                                                              (line   6)
3617
* configuration parameter setting (Interactive CLI): Interactive Command Line.
3618
                                                              (line 146)
3619
* configuring branch prediction:         Branch Prediction Configuration.
3620
                                                              (line   6)
3621
* configuring data & instruction caches: Cache Configuration. (line   6)
3622
* configuring data & instruction MMUs:   Memory Management Configuration.
3623
                                                              (line   6)
3624
* configuring DMA:                       DMA Configuration.   (line   6)
3625
* configuring memory:                    Memory Configuration.
3626
                                                              (line   6)
3627
* configuring Or1ksim:                   Configuration.       (line   6)
3628
* configuring power management:          Power Management Configuration.
3629
                                                              (line   6)
3630
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
3631
                                                              (line   6)
3632
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
3633
* configuring the CPU:                   CPU Configuration.   (line   6)
3634
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
3635
                                                              (line   6)
3636
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
3637
                                                              (line   6)
3638
* configuring the Ethernet interface:    Ethernet Configuration.
3639
                                                              (line   6)
3640
* configuring the frame buffer:          Frame Buffer Configuration.
3641
                                                              (line   6)
3642
* configuring the GPIO:                  GPIO Configuration.  (line   6)
3643
* configuring the interrupt controller:  Interrupt Configuration.
3644
                                                              (line   6)
3645
* configuring the keyboard interface:    Keyboard Configuration.
3646
                                                              (line   6)
3647
* configuring the memory controller:     Memory Controller Configuration.
3648
                                                              (line   6)
3649
* configuring the processor:             CPU Configuration.   (line   6)
3650
* configuring the PS2 interface:         Keyboard Configuration.
3651
                                                              (line   6)
3652
* configuring the UART:                  UART Configuration.  (line   6)
3653
* configuring the Verification API (VAPI): Verification API Configuration.
3654
                                                              (line   6)
3655
* configuring the VGA interface:         Display Interface Configuration.
3656
                                                              (line   6)
3657
* copying memory (Interactive CLI):      Interactive Command Line.
3658
                                                              (line  54)
3659
* CPU configuration:                     CPU Configuration.   (line   6)
3660
* CUC configuration:                     CUC Configuration.   (line   6)
3661
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
3662
                                                              (line 162)
3663
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
3664
* data cache configuration:              Cache Configuration. (line   6)
3665
* data MMU configuration:                Memory Management Configuration.
3666
                                                              (line   6)
3667
* DCGE (power management register):      Power Management Configuration.
3668
                                                              (line  21)
3669
* debug (Interactive CLI):               Interactive Command Line.
3670
                                                              (line 151)
3671
* debug (simulator configuration):       Simulator Behavior.  (line  13)
3672
* debug channel toggle (Interactive CLI): Interactive Command Line.
3673
                                                              (line 141)
3674
* debug interface configuration:         Debug Interface Configuration.
3675
                                                              (line   6)
3676
* debug mode toggle (Interactive CLI):   Interactive Command Line.
3677
                                                              (line 151)
3678
* debug unit configuration:              Debug Interface Configuration.
3679
                                                              (line   6)
3680
* Debug Unit verification (VAPI):        Verification API.    (line  34)
3681
* debugging enabled (Argtable2):         Configuring the Build.
3682 104 jeremybenn
                                                              (line 126)
3683
* DejaGnu board configurations:          Regression Testing.  (line  35)
3684
* DejaGnu configuration:                 Regression Testing.  (line  21)
3685
* DejaGNU tests directories:             Regression Testing.  (line  50)
3686
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
3687 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
3688 98 jeremybenn
                                                              (line 137)
3689 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
3690 98 jeremybenn
                                                              (line 143)
3691
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
3692 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
3693
                                                              (line  36)
3694
* disassemble (Interactive CLI):         Interactive Command Line.
3695
                                                              (line  41)
3696
* disc interface configuration:          Disc Interface Configuration.
3697
                                                              (line   6)
3698
* disc interface device configuration:   Disc Interface Configuration.
3699
                                                              (line  88)
3700
* display interface configuration:       Display Interface Configuration.
3701
                                                              (line   6)
3702
* displaying memory (Interactive CLI):   Interactive Command Line.
3703
                                                              (line  31)
3704
* displaying registers (Interactive CLI): Interactive Command Line.
3705
                                                              (line  14)
3706
* dm (Interactive CLI):                  Interactive Command Line.
3707
                                                              (line  31)
3708
* dma (Ethernet configuration):          Ethernet Configuration.
3709
                                                              (line  33)
3710
* DMA configuration:                     DMA Configuration.   (line   6)
3711
* DMA verification (VAPI):               Verification API.    (line  73)
3712
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
3713
                                                              (line  70)
3714
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3715
                                                              (line  71)
3716
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
3717
                                                              (line  69)
3718
* DME (power management register):       Power Management Configuration.
3719
                                                              (line  15)
3720
* DMMU configuration:                    Memory Management Configuration.
3721
                                                              (line   6)
3722
* doze mode (power management register): Power Management Configuration.
3723
                                                              (line  15)
3724
* dv (Interactive CLI):                  Interactive Command Line.
3725
                                                              (line 124)
3726
* dynamic clock gating (power management register): Power Management Configuration.
3727
                                                              (line  21)
3728
* dynamic model:                         Configuring the Build.
3729 104 jeremybenn
                                                              (line  37)
3730 19 jeremybenn
* dynamic ports, use of:                 Verification API Configuration.
3731
                                                              (line  23)
3732
* edge_trigger (interrupt controller):   Interrupt Configuration.
3733
                                                              (line  16)
3734
* enable_bursts (CUC configuration):     CUC Configuration.   (line  38)
3735
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
3736
                                                              (line  18)
3737
* enabled (branch prediction configuration): Branch Prediction Configuration.
3738
                                                              (line  15)
3739
* enabled (cache configuration):         Cache Configuration. (line  11)
3740
* enabled (debug interface configuration): Debug Interface Configuration.
3741
                                                              (line  11)
3742
* enabled (DMA configuration):           DMA Configuration.   (line  20)
3743
* enabled (Ethernet configuration):      Ethernet Configuration.
3744
                                                              (line  18)
3745
* enabled (frame buffer configuration):  Frame Buffer Configuration.
3746
                                                              (line  16)
3747
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
3748
                                                              (line  18)
3749
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
3750
* enabled (interrupt controller):        Interrupt Configuration.
3751
                                                              (line  12)
3752
* enabled (keyboard configuration):      Keyboard Configuration.
3753
                                                              (line  32)
3754
* enabled (memory controller configuration): Memory Controller Configuration.
3755 98 jeremybenn
                                                              (line  35)
3756 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
3757
                                                              (line  12)
3758
* enabled (power management configuration): Power Management Configuration.
3759
                                                              (line  35)
3760
* enabled (UART configuration):          UART Configuration.  (line  18)
3761
* enabled (verification API configuration): Verification API Configuration.
3762
                                                              (line  15)
3763
* enabled (VGA configuration):           Display Interface Configuration.
3764
                                                              (line  22)
3765
* enabling Ethernet via socket:          Configuring the Build.
3766 104 jeremybenn
                                                              (line  59)
3767 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
3768
                                                              (line  32)
3769
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
3770
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
3771
* Ethernet configuration:                Ethernet Configuration.
3772
                                                              (line   6)
3773
* Ethernet verification (VAPI):          Verification API.    (line  78)
3774
* Ethernet via socket, enabling:         Configuring the Build.
3775 104 jeremybenn
                                                              (line  59)
3776 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
3777
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
3778
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
3779 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
3780 82 jeremybenn
                                                              (line  97)
3781 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
3782 82 jeremybenn
                                                              (line  93)
3783 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
3784 82 jeremybenn
                                                              (line  86)
3785
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
3786 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
3787 82 jeremybenn
                                                              (line  58)
3788 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
3789 82 jeremybenn
                                                              (line  62)
3790 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
3791 82 jeremybenn
                                                              (line  69)
3792 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
3793 82 jeremybenn
                                                              (line  74)
3794 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
3795
                                                              (line  23)
3796
* execution history (Interactive CLI):   Interactive Command Line.
3797
                                                              (line  67)
3798
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
3799
                                                              (line 104)
3800
* file (keyboard configuration):         Keyboard Configuration.
3801
                                                              (line  51)
3802
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
3803 82 jeremybenn
                                                              (line  36)
3804 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
3805
                                                              (line  47)
3806
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
3807
                                                              (line 117)
3808
* flag setting by instructions:          Configuring the Build.
3809 104 jeremybenn
                                                              (line  98)
3810
* floating point multiply and add:       Known Issues.        (line  56)
3811
* floating point support:                Known Issues.        (line  42)
3812 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
3813
                                                              (line   6)
3814
* gdb_enabled (debug interface configuration): Debug Interface Configuration.
3815
                                                              (line  47)
3816
* generic peripheral configuration:      Generic Peripheral Configuration.
3817
                                                              (line   6)
3818
* GPIO configuration:                    GPIO Configuration.  (line   6)
3819
* GPIO verification (VAPI):              Verification API.    (line  88)
3820
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
3821
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
3822
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
3823
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
3824
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
3825
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
3826
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
3827 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
3828 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
3829 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
3830
                                                              (line 121)
3831
* help (Interactive CLI):                Interactive Command Line.
3832
                                                              (line 170)
3833
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
3834
                                                              (line 133)
3835
* hide_device_id (verification API configuration): Verification API Configuration.
3836
                                                              (line  36)
3837
* hist (Interactive CLI):                Interactive Command Line.
3838
                                                              (line  67)
3839 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
3840 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
3841
                                                              (line  67)
3842
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
3843
                                                              (line  33)
3844
* hitdelay (instruction cache configuration): Cache Configuration.
3845
                                                              (line  38)
3846
* hitdelay (MMU configuration):          Memory Management Configuration.
3847
                                                              (line  51)
3848 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
3849 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3850
                                                              (line  49)
3851
* IMMU configuration:                    Memory Management Configuration.
3852
                                                              (line   6)
3853
* index (memory controller configuration): Memory Controller Configuration.
3854 98 jeremybenn
                                                              (line  68)
3855 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
3856
                                                              (line 119)
3857
* installing Or1ksim:                    Installation.        (line   6)
3858
* instruction cache configuration:       Cache Configuration. (line   6)
3859
* instruction MMU configuration:         Memory Management Configuration.
3860
                                                              (line   6)
3861
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
3862
* instruction profiling utility (Interactive CLI): Interactive Command Line.
3863
                                                              (line 178)
3864
* internal debugging:                    Internal Debugging.  (line   6)
3865
* interrupt controller configuration:    Interrupt Configuration.
3866
                                                              (line   6)
3867
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
3868
                                                              (line  32)
3869
* irq (DMA configuration):               DMA Configuration.   (line  34)
3870
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
3871
* irq (keyboard configuration):          Keyboard Configuration.
3872
                                                              (line  47)
3873
* irq (UART configuration):              UART Configuration.  (line  70)
3874
* irq (VGA configuration):               Display Interface Configuration.
3875
                                                              (line  37)
3876
* jitter (UART configuration):           UART Configuration.  (line  78)
3877
* keyboard configuration:                Keyboard Configuration.
3878
                                                              (line   6)
3879 104 jeremybenn
* lf.madd.s:                             Known Issues.        (line  56)
3880 19 jeremybenn
* library version of Or1ksim:            Simulator Library.   (line   6)
3881
* license for Or1ksim:                   GNU Free Documentation License.
3882
                                                              (line   6)
3883
* list breakpoints (Interactive CLI):    Interactive Command Line.
3884
                                                              (line  60)
3885
* load_hitdelay (data cache configuration): Cache Configuration.
3886
                                                              (line  46)
3887
* load_missdelay (data cache configuration): Cache Configuration.
3888
                                                              (line  50)
3889
* log (memory configuration):            Memory Configuration.
3890 98 jeremybenn
                                                              (line 149)
3891 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
3892
                                                              (line  28)
3893 93 jeremybenn
* long:                                  Simulator Library.   (line  87)
3894 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
3895 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
3896 98 jeremybenn
                                                              (line 126)
3897 19 jeremybenn
* memory configuration:                  Memory Configuration.
3898
                                                              (line   6)
3899
* memory controller configuration:       Memory Controller Configuration.
3900
                                                              (line   6)
3901
* memory copying (Interactive CLI):      Interactive Command Line.
3902
                                                              (line  54)
3903
* memory display (Interactive CLI):      Interactive Command Line.
3904
                                                              (line  31)
3905
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
3906
                                                              (line 133)
3907
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
3908
                                                              (line 124)
3909
* memory patching (Interactive CLI):     Interactive Command Line.
3910
                                                              (line  48)
3911
* memory profiling end address:          Memory Profiling Utility.
3912
                                                              (line  56)
3913
* memory profiling start address:        Memory Profiling Utility.
3914
                                                              (line  56)
3915
* memory profiling utility (Interactive CLI): Interactive Command Line.
3916
                                                              (line 173)
3917
* memory profiling version of Or1ksim:   Memory Profiling Utility.
3918
                                                              (line   6)
3919
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
3920
* memory_order=exact (CUC configuration): CUC Configuration.  (line  27)
3921
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
3922
* memory_order=strong (CUC configuration): CUC Configuration. (line  25)
3923
* memory_order=weak (CUC configuration): CUC Configuration.   (line  21)
3924
* missdelay (branch prediction configuration): Branch Prediction Configuration.
3925
                                                              (line  37)
3926
* missdelay (instruction cache configuration): Cache Configuration.
3927
                                                              (line  42)
3928
* missdelay (MMU configuration):         Memory Management Configuration.
3929
                                                              (line  55)
3930
* MMU configuration:                     Memory Management Configuration.
3931
                                                              (line   6)
3932 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
3933 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
3934 82 jeremybenn
                                                              (line  34)
3935 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
3936
                                                              (line 173)
3937 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
3938 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
3939
                                                              (line 128)
3940
* name (generic peripheral configuration): Generic Peripheral Configuration.
3941
                                                              (line  42)
3942
* name (memory configuration):           Memory Configuration.
3943 98 jeremybenn
                                                              (line 108)
3944 19 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  42)
3945
* nsets (cache configuration):           Cache Configuration. (line  15)
3946
* nsets (MMU configuration):             Memory Management Configuration.
3947
                                                              (line  16)
3948
* nways (cache configuration):           Cache Configuration. (line  22)
3949
* nways (MMU configuration):             Memory Management Configuration.
3950
                                                              (line  22)
3951 93 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  77)
3952
* or1ksim_init:                          Simulator Library.   (line  14)
3953
* or1ksim_interrupt:                     Simulator Library.   (line  92)
3954
* or1ksim_interrupt_clear:               Simulator Library.   (line 110)
3955
* or1ksim_interrupt_set:                 Simulator Library.   (line 101)
3956
* or1ksim_is_le:                         Simulator Library.   (line  82)
3957 104 jeremybenn
* or1ksim_jtag_reset:                    Simulator Library.   (line 119)
3958
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 141)
3959
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 127)
3960 93 jeremybenn
* or1ksim_reset_duration:                Simulator Library.   (line  62)
3961
* or1ksim_run:                           Simulator Library.   (line  57)
3962
* or1ksim_set_time_point:                Simulator Library.   (line  73)
3963 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
3964
* overflow flag setting by instructions: Configuring the Build.
3965 104 jeremybenn
                                                              (line  75)
3966 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
3967
                                                              (line 113)
3968
* pagesize (MMU configuration):          Memory Management Configuration.
3969
                                                              (line  27)
3970
* patching memory (Interactive CLI):     Interactive Command Line.
3971
                                                              (line  48)
3972
* patching registers (Interactive CLI):  Interactive Command Line.
3973
                                                              (line  28)
3974
* patching the program counter (Interactive CLI): Interactive Command Line.
3975
                                                              (line  51)
3976
* pattern (memory configuration):        Memory Configuration.
3977 98 jeremybenn
                                                              (line  75)
3978 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
3979
                                                              (line  51)
3980
* PIC configuration:                     Interrupt Configuration.
3981
                                                              (line   6)
3982
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
3983
                                                              (line 132)
3984
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
3985
                                                              (line  51)
3986
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
3987
                                                              (line  52)
3988
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
3989
                                                              (line  53)
3990
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3991
                                                              (line  54)
3992
* pm (Interactive CLI):                  Interactive Command Line.
3993
                                                              (line  48)
3994
* PMR - DGCE:                            Power Management Configuration.
3995
                                                              (line  21)
3996
* PMR - DME:                             Power Management Configuration.
3997
                                                              (line  15)
3998
* PMR - SDF:                             Power Management Configuration.
3999
                                                              (line  12)
4000
* PMR - SME:                             Power Management Configuration.
4001
                                                              (line  16)
4002
* PMR - SUME:                            Power Management Configuration.
4003
                                                              (line  24)
4004
* PMU configuration:                     Power Management Configuration.
4005
                                                              (line   6)
4006
* poc (memory controller configuration): Memory Controller Configuration.
4007 98 jeremybenn
                                                              (line  55)
4008 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4009
                                                              (line  23)
4010
* power management configuration:        Power Management Configuration.
4011
                                                              (line   6)
4012
* power management register, DGCE:       Power Management Configuration.
4013
                                                              (line  21)
4014
* power management register, DME:        Power Management Configuration.
4015
                                                              (line  15)
4016
* power management register, SDF:        Power Management Configuration.
4017
                                                              (line  12)
4018
* power management register, SME:        Power Management Configuration.
4019
                                                              (line  16)
4020
* power management register, SUME:       Power Management Configuration.
4021
                                                              (line  24)
4022
* pr (Interactive CLI):                  Interactive Command Line.
4023
                                                              (line  28)
4024
* private ports, use of:                 Verification API Configuration.
4025
                                                              (line  23)
4026
* processor configuration:               CPU Configuration.   (line   6)
4027
* processor stall (Interactive CLI):     Interactive Command Line.
4028
                                                              (line  72)
4029
* processor unstall (Interactive CLI):   Interactive Command Line.
4030
                                                              (line  78)
4031
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4032
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4033
                                                              (line  23)
4034
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4035
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4036
* profiling utility (Interactive CLI):   Interactive Command Line.
4037
                                                              (line 178)
4038
* program counter patching (Interactive CLI): Interactive Command Line.
4039
                                                              (line  51)
4040
* programmable interrupt controller configuration: Interrupt Configuration.
4041
                                                              (line   6)
4042
* PS2 configuration:                     Keyboard Configuration.
4043
                                                              (line   6)
4044
* q (Interactive CLI):                   Interactive Command Line.
4045
                                                              (line  11)
4046
* quitting (Interactive CLI):            Interactive Command Line.
4047
                                                              (line  11)
4048
* r (Interactive CLI):                   Interactive Command Line.
4049
                                                              (line  14)
4050
* random_seed (memory configuration):    Memory Configuration.
4051 98 jeremybenn
                                                              (line  65)
4052 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4053 82 jeremybenn
                                                              (line  30)
4054 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4055
                                                              (line  41)
4056
* reg_sim_reset:                         Concepts.            (line  13)
4057
* register display (Interactive CLI):    Interactive Command Line.
4058
                                                              (line  14)
4059
* register over time statistics:         Configuring the Build.
4060 104 jeremybenn
                                                              (line  69)
4061 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4062
                                                              (line  28)
4063 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4064 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4065
                                                              (line  20)
4066
* reset (Interactive CLI):               Interactive Command Line.
4067
                                                              (line  63)
4068
* reset hooks:                           Concepts.            (line  13)
4069
* reset the simulator (Interactive CLI): Interactive Command Line.
4070
                                                              (line  63)
4071
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4072
                                                              (line  44)
4073
* rev (CPU configuration):               CPU Configuration.   (line  15)
4074
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4075
                                                              (line  20)
4076
* rsp_port (debug interface configuration): Debug Interface Configuration.
4077
                                                              (line  36)
4078
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4079
                                                              (line  46)
4080
* run (Interactive CLI):                 Interactive Command Line.
4081
                                                              (line  23)
4082
* running code (Interactive CLI):        Interactive Command Line.
4083
                                                              (line  23)
4084
* running Or1ksim:                       Usage.               (line   6)
4085
* runtime:                               Global Data Structures.
4086
                                                              (line  58)
4087
* runtime global structure:              Global Data Structures.
4088
                                                              (line  58)
4089
* runtime.cpu:                           Global Data Structures.
4090
                                                              (line  62)
4091
* runtime.cpu.fout:                      Concepts.            (line   7)
4092
* runtime.cuc:                           Global Data Structures.
4093
                                                              (line  62)
4094
* runtime.vapi:                          Global Data Structures.
4095
                                                              (line  62)
4096
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4097
                                                              (line  59)
4098
* rxfile (Ethernet configuration):       Ethernet Configuration.
4099
                                                              (line  68)
4100
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4101
                                                              (line  23)
4102
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4103
                                                              (line  28)
4104 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4105 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4106
                                                              (line  12)
4107
* section ata:                           Disc Interface Configuration.
4108
                                                              (line   6)
4109
* section bpb:                           Branch Prediction Configuration.
4110
                                                              (line   6)
4111
* section cpio:                          GPIO Configuration.  (line   6)
4112
* section cpu:                           CPU Configuration.   (line   6)
4113
* section cuc:                           CUC Configuration.   (line   6)
4114
* section dc:                            Cache Configuration. (line   6)
4115
* section debug:                         Debug Interface Configuration.
4116
                                                              (line   6)
4117
* section dma:                           DMA Configuration.   (line   6)
4118
* section dmmu:                          Memory Management Configuration.
4119
                                                              (line   6)
4120
* section ethernet:                      Ethernet Configuration.
4121
                                                              (line   6)
4122
* section fb:                            Frame Buffer Configuration.
4123
                                                              (line   6)
4124
* section generic:                       Generic Peripheral Configuration.
4125
                                                              (line   6)
4126
* section ic:                            Cache Configuration. (line   6)
4127
* section immu:                          Memory Management Configuration.
4128
                                                              (line   6)
4129
* section kb:                            Keyboard Configuration.
4130
                                                              (line   6)
4131
* section mc:                            Memory Controller Configuration.
4132
                                                              (line   6)
4133
* section memory:                        Memory Configuration.
4134
                                                              (line   6)
4135
* section pic:                           Interrupt Configuration.
4136
                                                              (line   6)
4137
* section pmu:                           Power Management Configuration.
4138
                                                              (line   6)
4139
* section sim:                           Simulator Behavior.  (line   6)
4140
* section uart:                          UART Configuration.  (line   6)
4141
* section vapi:                          Verification API Configuration.
4142
                                                              (line   6)
4143
* section vga:                           Display Interface Configuration.
4144
                                                              (line   6)
4145
* sections:                              Global Data Structures.
4146
                                                              (line  49)
4147
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4148
                                                              (line 125)
4149
* server_port (debug interface configuration): Debug Interface Configuration.
4150
                                                              (line  69)
4151
* server_port (verification API configuration): Verification API Configuration.
4152
                                                              (line  19)
4153
* set (Interactive CLI):                 Interactive Command Line.
4154
                                                              (line 146)
4155
* set breakpoint (Interactive CLI):      Interactive Command Line.
4156
                                                              (line  57)
4157
* setdbch (Interactive CLI):             Interactive Command Line.
4158
                                                              (line 141)
4159
* simple model:                          Configuring the Build.
4160 104 jeremybenn
                                                              (line  37)
4161 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4162
* simulator configuration info (Interactive CLI): Interactive Command Line.
4163
                                                              (line 119)
4164
* simulator reset (Interactive CLI):     Interactive Command Line.
4165
                                                              (line  63)
4166
* simulator statistics (Interactive CLI): Interactive Command Line.
4167
                                                              (line  83)
4168
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4169
                                                              (line 109)
4170
* size (generic peripheral configuration): Generic Peripheral Configuration.
4171
                                                              (line  30)
4172
* size (memory configuration):           Memory Configuration.
4173 98 jeremybenn
                                                              (line  92)
4174 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4175
                                                              (line  16)
4176
* slow down factor (power management register): Power Management Configuration.
4177
                                                              (line  12)
4178
* SME (power management register):       Power Management Configuration.
4179
                                                              (line  16)
4180
* sockif (Ethernet configuration):       Ethernet Configuration.
4181
                                                              (line  83)
4182
* sr (CPU configuration):                CPU Configuration.   (line  53)
4183
* stall (Interactive CLI):               Interactive Command Line.
4184
                                                              (line  72)
4185
* stall the processor (Interactive CLI): Interactive Command Line.
4186
                                                              (line  72)
4187
* statistics, register over time:        Configuring the Build.
4188 104 jeremybenn
                                                              (line  69)
4189 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4190
                                                              (line  83)
4191
* stats (Interactive CLI):               Interactive Command Line.
4192
                                                              (line  83)
4193
* stepping code (Interactive CLI):       Interactive Command Line.
4194
                                                              (line  19)
4195
* store_hitdelay (data cache configuration): Cache Configuration.
4196
                                                              (line  54)
4197
* store_missdelay (data cache configuration): Cache Configuration.
4198
                                                              (line  58)
4199
* SUME (power management register):      Power Management Configuration.
4200
                                                              (line  24)
4201 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4202 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4203
                                                              (line  24)
4204
* t (Interactive CLI):                   Interactive Command Line.
4205
                                                              (line  19)
4206 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4207 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4208
                                                              (line  23)
4209
* TCP/IP port range for or1ksim service: Debug Interface Configuration.
4210
                                                              (line  74)
4211
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4212
                                                              (line  41)
4213 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4214
* test code for target:                  Regression Testing.  (line  63)
4215
* test make file:                        Regression Testing.  (line  27)
4216
* test README:                           Regression Testing.  (line  32)
4217
* testing:                               Regression Testing.  (line   6)
4218 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4219 104 jeremybenn
                                                              (line 133)
4220 19 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  46)
4221
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4222
                                                              (line  46)
4223
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4224
                                                              (line  57)
4225
* toggle debug channels (Interactive CLI): Interactive Command Line.
4226
                                                              (line 141)
4227
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4228
                                                              (line 151)
4229
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4230
                                                              (line  60)
4231
* txfile (Ethernet configuration):       Ethernet Configuration.
4232
                                                              (line  69)
4233
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4234 82 jeremybenn
                                                              (line  36)
4235 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4236
                                                              (line  47)
4237
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4238
                                                              (line  99)
4239
* type (memory configuration):           Memory Configuration.
4240 98 jeremybenn
                                                              (line  36)
4241 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4242 98 jeremybenn
                                                              (line  46)
4243 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4244 98 jeremybenn
                                                              (line  40)
4245 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4246 98 jeremybenn
                                                              (line  50)
4247 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4248 98 jeremybenn
                                                              (line  54)
4249 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4250
* UART I/O from/to a physical serial port: UART Configuration.
4251
                                                              (line  62)
4252
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4253
* UART I/O from/to files:                UART Configuration.  (line  33)
4254
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4255
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4256
* UART verification (VAPI):              Verification API.    (line  41)
4257
* unstall (Interactive CLI):             Interactive Command Line.
4258
                                                              (line  78)
4259
* unstall the processor (Interactive CLI): Interactive Command Line.
4260
                                                              (line  78)
4261
* upr (CPU configuration):               CPU Configuration.   (line  21)
4262
* ustates (cache configuration):         Cache Configuration. (line  33)
4263
* ustates (MMU configuration):           Memory Management Configuration.
4264
                                                              (line  41)
4265
* VAPI configuration:                    Verification API Configuration.
4266
                                                              (line   6)
4267
* VAPI for Debug Unit:                   Verification API.    (line  34)
4268
* VAPI for DMA:                          Verification API.    (line  73)
4269
* VAPI for Ethernet:                     Verification API.    (line  78)
4270
* VAPI for GPIO:                         Verification API.    (line  88)
4271
* VAPI for UART:                         Verification API.    (line  41)
4272
* vapi_id (debug interface configuration): Debug Interface Configuration.
4273
                                                              (line  80)
4274
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4275
                                                              (line  88)
4276
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4277
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4278
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4279
* vapi_log_file (verification API configuration): Verification API Configuration.
4280
                                                              (line  41)
4281
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4282
                                                              (line  41)
4283
* ver (CPU configuration):               CPU Configuration.   (line  15)
4284
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4285
* Verification API configuration:        Verification API Configuration.
4286
                                                              (line   6)
4287
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4288
                                                              (line 124)
4289
* VGA configuration:                     Display Interface Configuration.
4290
 
4291
 
4292
                                                              (line  50)
4293
4294
4295

4296
Tag Table:
4297 104 jeremybenn
Node: Top814
4298
Node: Installation1224
4299
Node: Preparation1471
4300
Node: Configuring the Build1764
4301
Node: Build and Install7486
4302
Node: Known Issues8332
4303
Node: Usage11392
4304
Node: Standalone Simulator11606
4305
Node: Profiling Utility14509
4306
Node: Memory Profiling Utility15419
4307
Node: Simulator Library16784
4308
Node: Configuration24562
4309
Node: Configuration File Format25171
4310
Node: Configuration File Preprocessing25463
4311
Node: Configuration File Syntax25834
4312
Node: Simulator Configuration28619
4313
Node: Simulator Behavior28910
4314
Node: Verification API Configuration32954
4315
Node: CUC Configuration34894
4316
Node: Core OpenRISC Configuration36811
4317
Node: CPU Configuration37313
4318
Node: Memory Configuration41431
4319
Node: Memory Management Configuration47889
4320
Node: Cache Configuration50266
4321
Node: Interrupt Configuration52652
4322
Node: Power Management Configuration53388
4323
Node: Branch Prediction Configuration54665
4324
Node: Debug Interface Configuration56025
4325
Node: Peripheral Configuration60245
4326
Node: Memory Controller Configuration60871
4327
Node: UART Configuration64285
4328
Node: DMA Configuration67804
4329
Node: Ethernet Configuration69671
4330
Node: GPIO Configuration73647
4331
Node: Display Interface Configuration75280
4332
Node: Frame Buffer Configuration77589
4333
Node: Keyboard Configuration79453
4334
Node: Disc Interface Configuration81691
4335
Node: Generic Peripheral Configuration86634
4336
Node: Interactive Command Line88929
4337
Node: Verification API95903
4338
Node: Code Internals100333
4339
Node: Coding Conventions100916
4340
Node: Global Data Structures105343
4341
Node: Concepts108000
4342
Ref: Output Redirection108145
4343
Node: Internal Debugging108684
4344
Node: Regression Testing109208
4345
Node: GNU Free Documentation License113003

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.