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This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
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../../doc/or1ksim.texi.
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INFO-DIR-SECTION Embedded development
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START-INFO-DIR-ENTRY
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* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
7
                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 143 jeremybenn
     tar jxf or1ksim-2010-06-31.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
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default to OpenRISC 1000 32-bit with a warning
83
 
84 143 jeremybenn
     ../or1ksim-2010-06-31/configure --target=or32-uclinux ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 104 jeremybenn
For testing (using `make check'), the `--target' parameter _must_ be
92
specified, to allow the target tool chain to be selected. If the tools
93
have been installed using the standard OpenRISC script, then this
94
should be set to `or32-elf'.
95 19 jeremybenn
 
96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
101 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
`--enable-execution=dynamic'
108
     Or1ksim has developed to improve functionality and performance.
109
     This feature allows three versions of Or1ksim to be built
110
 
111
    `--enable-execution=simple'
112
          Build the original simple interpreting simulator
113
 
114
    `--enable-execution=complex'
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          Build a more complex interpreting simulator.  Experiments
116
          suggest this is 50% faster than the simple simulator.  This
117
          is the default.
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119
    `--enable-execution=dynamic'
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          Build a dynamically compiling simulator.  This is the way
121
          many modern ISS are built.  This represents a work in
122
          progress.  Currently Or1ksim will compile, but segfaults if
123
          configured with this option.
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125
 
126
     The default is `--enable-execution=complex'.
127
 
128
`--enable-ethphy'
129
`--disable-ethphy'
130
     If enabled, this option allows the Ethernet to be simulated by
131
     connecting via a socket (the alternative reads and writes, from
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     and to files).  This must then be configured using the relevant
133
     fields in the `ethernet' section of the configuration file.  *Note
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     Ethernet Configuration: Ethernet Configuration.
135
 
136
     The default is for this to be disabled.
137
 
138 127 jeremybenn
`--enable-unsigned-xori'
139
`--disable-unsigned-xori'
140
     Historically, `l.xori', has sign extended its operand. This is
141
     inconsistent with the other logical opcodes (`l.andi', `l.ori'),
142
     but in the absence of `l.not', it allows a register to be inverted
143
     in a single instruction using:
144
 
145
          `l.xori  rD,rA,-1'
146
 
147
     This flag causes Or1ksim to treat the immediate operand as
148
     unsigned (i.e to zero-extend rather than sign-extend).
149
 
150
     The default is to sign-extend, so that existing code will continue
151
     to work.
152
 
153
          Caution: The GNU compiler tool chain makes heavy use of this
154
          instruction.  Using unsigned behavior will require the
155
          compiler to be modified accordingly.
156
 
157
          This option is provided for experimentation.  A future
158
          version of OpenRISC may adopt this more consistent behavior
159
          and also provide a `l.not' opcode.
160
 
161 19 jeremybenn
`--enable-range-stats'
162
`--disable-range-stats'
163
     If enabled, this option allows statistics to be collected to
164 82 jeremybenn
     analyse register access over time.  The default is for this to be
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     disabled.
166
 
167
`--enable-debug'
168
`--disable-debug'
169
     This is a feature of the Argtable2 package used to process
170 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
171
     Argtable2.  It is provided for completeness, but there is no
172
     reason why this feature should ever be needed by any Or1ksim user.
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174 82 jeremybenn
`--enable-all-tests'
175
`--disable-all-tests'
176
     Some of the tests (at the time of writing just one) will not
177
     compile without error.  If enabled with this flag, all test
178
     programs will be compiled with `make check'.
179 19 jeremybenn
 
180 82 jeremybenn
     This flag is intended for those working on the test package, who
181
     wish to get the missing test(s) working.
182
 
183
 
184 112 jeremybenn
A number of configuration flags have been removed since version 0.3.0,
185 124 jeremybenn
because they led to invalid behavior of Or1ksim. Those removed are:
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187 124 jeremybenn
`--enable-arith-flag'
188
`--disable-arith-flag'
189
     If enabled, this option caused certain instructions to set the flag
190
     (`F' bit) in the supervision register if the result were zero.
191
     The instructions affected by this were `l.add', `l.addc',
192
     `l.addi', `l.and' and `l.andi'.
193
 
194
     If set, this caused incorrect behavior. Whether or not flags are
195
     set is part of the OpenRISC 1000 architectural specification.  The
196
     only flags which should set this are the "set flag" instructions:
197
     `l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
198
     `l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
199
     `l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
200
     `l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
201
 
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`--enable-ov-flag'
203
`--disable-ov-flag'
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     This flag caused certain instructions to set the overflow flag.
205
     If not, those instructions would not set the overflow flat.  The
206
     instructions affected by this were `l.add', `l.addc', `l.addi',
207
     `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
208
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
209
     `l.sub', `l.xor' and `l.xori'.
210 112 jeremybenn
 
211
     This guaranteed incorrect behavior.  The OpenRISC 1000 architecture
212
     specification defines which flags are set by which instructions.
213
 
214
     Within the above list, the arithmetic instructions (`l.add',
215
     `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
216
     `l.sub'), together with `l.addic' which is missed out, set the
217
     overflow flag.  All the others (`l.and', `l.andi', `l.or',
218
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
219
     `l.xor' and `l.xori') do not.
220
 
221
 
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223
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
224
 
225
1.3 Building and Installing
226
===========================
227
 
228 82 jeremybenn
Build the tool with:
229 19 jeremybenn
 
230
     make all
231 82 jeremybenn
 
232
If you have the OpenRISC tool chain and DejaGNU installed, you can
233
verify the tool as follows (otherwise omit this step):
234
 
235
     make check
236
 
237
Install the tool with:
238
 
239 19 jeremybenn
     make install
240
 
241
This will install the three variations of the Or1ksim tool,
242
`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the
243
Or1ksim library, `libsim', the header file, `or1ksim.h' and this
244
documentation in `info' format.
245
 
246
     Note: Testing Or1ksim with `make check' is not yet supported.
247
 
248
The documentation may be created and installed in alternative formats
249
(PDF, Postscript, DVI, HTML) with for example:
250
 
251
     make pdf
252
     make install-pdf
253
 
254

255
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
256
 
257
1.4 Known Problems and Issues
258
=============================
259
 
260 143 jeremybenn
The following problems and issues are known about with Or1ksim
261
2010-06-31.  The OpenRISC tracker may be used to see the current state
262
of these issues and to raise new problems and feature requests.  It may
263
be found at `http://www.opencores.org/ptracker.cgi/view/or1k/398'.
264 19 jeremybenn
 
265
   * The Supervision Register Little Endian Enable (LEE) bit is
266 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
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     endian use, but that behavior cannot be changed dynamically.
268
 
269
   * The NPC is a read/write register, but after being written it
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     clears the pipeline.  This means that if the processor is stalled,
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     the value should subsequently read back as 0, until the processor
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     is unstalled and able to refill its pipeline.  By default Or1ksim
273 19 jeremybenn
     always reports back the value of NPC, even when it has been
274
     written while stalled.
275
 
276
     There is now an option, `--strict-npc', which will enforce this
277 82 jeremybenn
     behavior.  At some stage in the future it will become the default
278 19 jeremybenn
     behavior, but for now it is an option, since its use will break
279
     GDB.
280
 
281
   * The memory components are given names in the configuration file.
282
     However there is currently no way for Or1ksim to report that name
283
     back to the user (for example to identify which memory block
284
     corresponds to a particular access).
285
 
286
   * Or1ksim allows the processor to be stalled (from the command
287 82 jeremybenn
     line), even if there is no debugger present.  This seems to be a
288 19 jeremybenn
     meaningless operation.
289
 
290
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
291 82 jeremybenn
     instances using the library.  This is clearly a problem when
292
     considering multi-core applications.  However it stems from the
293
     original design, and can only be fixed by a complete rewrite.  The
294 19 jeremybenn
     entire source code uses static global constants liberally!
295
 
296 104 jeremybenn
   * There is no support for single precision floating point
297
     instructions in Or1ksim if configured in the CPU (*note CPU
298
     Configuration: CPU Configuration.).  These are implemented using
299
     the floating point support in the host C library, which will
300
     usually be IEEE 745 compliant.  There is at present no support for
301
     double precision floating point instructions, since these are
302
     meaningless with 32-bit registers.
303 19 jeremybenn
 
304 104 jeremybenn
     Floating point support within OpenRISC is intended to follow IEEE
305
     745, which offers a degree of configurability. However at present
306
     the FPSCR register is not supported, so there is no mechanism for
307
     configuring floating point behavior. Thus the default
308
     functionality of the host C library will be used.
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310 104 jeremybenn
   * The single precision floating point multiply and add instruction,
311
     `lf.madd.s', is not clearly specified in the original architectural
312
     manual. User should consult the `OpenRISC 1200 version 2
313
     Supplementary Programmer's Reference Manual' for a specification
314
     of the functionality implemented.
315
 
316
 
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318
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
319
 
320
2 Usage
321
*******
322
 
323
* Menu:
324
 
325
* Standalone Simulator::
326
* Profiling Utility::
327
* Memory Profiling Utility::
328
* Simulator Library::
329
 
330

331
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
332
 
333
2.1 Standalone Simulator
334
========================
335
 
336
The general form the standalone command is:
337
 
338
     or32-uclinux-sim [-vhi] [-f FILE] [--nosrv] [--srv=[N]] [-d STR]
339
                      [--enable-profile] [--enable-mprofile] [FILE]
340
 
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Many of the options have both a short and a long form.  For example
342
`-h' or `--help'.
343 19 jeremybenn
 
344
`-v'
345
`--version'
346
     Print out the version and copyright notice for Or1ksim and exit.
347
 
348
`-h'
349
`--help'
350
     Print out help about the command line options and what they mean.
351
 
352
`-f FILE'
353
`--file FILE'
354
     Read configuration commands from the specified file, looking first
355
     in the current directory, and otherwise in the `$HOME/.or1k'
356 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
357
     in those two locations is used.  Failure to find the file is a
358
     fatal error.  *Note Configuration: Configuration, for detailed
359
     information on configuring Or1ksim.
360 19 jeremybenn
 
361
`--nosrv'
362 82 jeremybenn
     Do not start up the debug server.  This overrides any setting
363
     specified in the configuration file.  This option may not be
364
     specified with `--srv'.  If it is, a rude message is printed and
365
     the `--nosrv' option is ignored.
366 19 jeremybenn
 
367
`--srv'
368
 
369
`--srv=N'
370 82 jeremybenn
     Start up the debug server.  If the parameter, N, is specified, use
371 19 jeremybenn
     that as the TCP/IP port for the server, otherwise a random value
372 82 jeremybenn
     from the private port range (41920-65535) will be used.  This
373
     option may not be specified with `--nosrv'.  If it is, a rude
374
     message is printed and the `--nosrv' option is ignored.
375 19 jeremybenn
 
376
`-d=CONFIG_STRING'
377
`--debug-config=CONFIG_STRING'
378 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
379
     use by developers only, and is not covered further here.  See the
380 19 jeremybenn
     source code for more details.
381
 
382
`-i'
383
`--interactive'
384
     After starting, drop into the Or1ksim interactive command shell.
385
 
386
`--strict-npc'
387
     In real hardware, setting the next program counter (NPC, SPR 16),
388 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
389
     until the pipeline refills, reading the NPC will return zero.
390
     This is typically the case when debugging, since the processor is
391 19 jeremybenn
     stalled.
392
 
393
     Historically, Or1ksim has always returned the value of the NPC,
394 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
395
     is used, then Or1ksim will mirror real hardware more accurately.
396
     If the NPC is changed while the processor is stalled, subsequent
397 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
398
 
399
     This is not currently the default behavior, since tools such as
400
     GDB have been implemented assuming the historic Or1ksim behavior.
401
     However at some time in the future it will become the default.
402
 
403
`--enable-profile'
404
     Enable instruction profiling.
405
 
406
`--enable-mprofile'
407
     Enable memory profiling.
408
 
409
 
410

411
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
412
 
413
2.2 Profiling Utility
414
=====================
415
 
416 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
417
It may be invoked as a standalone command, or from the Or1ksim CLI.
418
The general form the standalone command is:
419 19 jeremybenn
 
420
     or32-uclinux-profile [-vhcq] [-g=FILE]
421
 
422 82 jeremybenn
Many of the options have both a short and a long form.  For example
423
`-h' or `--help'.
424 19 jeremybenn
 
425
`-v'
426
`--version'
427
     Print out the version and copyright notice for the Or1ksim
428
     profiling utility and exit.
429
 
430
`-h'
431
`--help'
432
     Print out help about the command line options and what they mean.
433
 
434
`-c'
435
`--cumulative'
436
     Show cumulative sum of cycles in functions
437
 
438
`-q'
439
`--quiet'
440
     Suppress messages
441
 
442
`-g=FILE'
443
`--generate=FILE'
444 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
445 19 jeremybenn
     `sim.profile' is used.
446
 
447
 
448

449
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Simulator Library,  Prev: Profiling Utility,  Up: Usage
450
 
451
2.3 Memory Profiling Utility
452
============================
453
 
454 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
455
be invoked as a standalone command, or from the Or1ksim CLI.  The
456 19 jeremybenn
general form the standalone command is:
457
 
458
     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
459
 
460 82 jeremybenn
Many of the options have both a short and a long form.  For example
461
`-h' or `--help'.
462 19 jeremybenn
 
463
`-v'
464
`--version'
465
     Print out the version and copyright notice for the Or1ksim memory
466
     profiling utility and exit.
467
 
468
`-h'
469
`--help'
470
     Print out help about the command line options and what they mean.
471
 
472
`-m=M'
473
`--mode=M'
474 82 jeremybenn
     Specify the mode out output.  Permitted options are
475 19 jeremybenn
 
476
    `detailed'
477
    `d'
478 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
479 19 jeremybenn
 
480
    `pretty'
481
    `p'
482
          Pretty printed output.
483
 
484
    `access'
485
    `a'
486
          Memory accesses only.
487
 
488
    `width'
489
    `w'
490
          Access width only.
491
 
492
 
493
`-g=N'
494
`--group=N'
495
     Group 2^n bits of successive addresses together.
496
 
497
`-f=FILE'
498
`--filename=FILE'
499 82 jeremybenn
     The data file to analyse.  If not specified, the default,
500 19 jeremybenn
     `sim.profile' is used.
501
 
502
`FROM'
503
`TO'
504
     FROM and TO are respectively the start and end address of the
505
     region of memory to be analysed.
506
 
507
 
508

509
File: or1ksim.info,  Node: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
510
 
511
2.4 Simulator Library
512
=====================
513
 
514
Or1ksim may be used as a static of dynamic library, `libsim.a' or
515 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
516 19 jeremybenn
should be added to the link command.
517
 
518
The header file `or1ksim.h' contains appropriate declarations of the
519 82 jeremybenn
functions exported by the Or1ksim library.  These are:
520 19 jeremybenn
 
521 93 jeremybenn
 -- `or1ksim.h': int or1ksim_init (const char
522
     *CONFIG_FILE, const char *IMAGE_FILE, void *CLASS_PTR, int
523
     (*UPR)(void *CLASS_PTR, unsigned long int ADDR, unsigned char
524
     MASK[], unsigned char RDATA[], int DATA_LEN), int (*UPW)(void
525
     *CLASS_PTR, unsigned long int ADDR, unsigned char MASK[], unsigned
526
     char WDATA[], int DATA_LEN))
527
 
528 19 jeremybenn
     The initialization function is supplied with the name of a
529
     configuration file, CONFIG_FILE, an executable image, IMAGE_FILE,
530
     a pointer to the calling class, CLASS_PTR (since the library may
531
     be used from C++) and two up-call functions, one for reads, UPR,
532
     and one for writes, UPW.
533
 
534
     *Note Configuration: Configuration, for detailed information on
535
     configuring Or1ksim and the format of the configuration file.
536
 
537
     UPW is called for any write to an address external to the model
538 82 jeremybenn
     (determined by a `generic' section in the configuration file).
539
     UPR is called for any reads to an external address.  The CLASS_PTR
540
     is passed back with these upcalls, allowing the function to
541
     associate the call with the class which originally initialized the
542 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
543
     non-zero otherwise.  At the present time the meaning of non-zero
544
     values is not defined but this may change in the future.
545 19 jeremybenn
 
546 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
547 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
548 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
549
     address, since the upcall function must handle all generic
550
     devices, using the full address for decoding.
551 19 jeremybenn
 
552 93 jeremybenn
     Endianness is not completely transparent, since Or1ksim is
553
     transferring byte vectors, not multi-byte values.
554 19 jeremybenn
 
555 93 jeremybenn
          Caution: This is a change from version 0.3.0. It simplifies
556
          the interface, and makes Or1ksim more consistent with payload
557
          representation in SystemC TLM 2.0.
558 19 jeremybenn
 
559 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
560
          single words (4 bytes), using masks if smaller values are
561
          required.  In this it mimcs the behavior of the WishBone bus.
562
 
563
 
564 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
565
     Run the simulator for the simulated duration specified (in
566
     seconds).
567
 
568
 
569
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
570
     Change the duration of a run specified in an earlier call to
571 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
572 19 jeremybenn
     realizes it needs to change the duration of the run specified in
573
     the call to `or1ksim_run' that has been interrupted by the upcall.
574
 
575
     The time specified is the amount of time that the run must continue
576
     for (i.e the duration from _now_, not the duration from the
577
     original call to `or1ksim_run').
578
 
579
 
580
 -- `or1ksim.h': void or1ksim_set_time_point ()
581 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
582 19 jeremybenn
 
583
 
584
 -- `or1ksim.h': double or1ksim_get_time_period ()
585
     Return the simulated time (in seconds) that has elapsed since the
586
     last call to `or1ksim_set_time_point'.
587
 
588
 
589
 -- `or1ksim.h': int or1ksim_is_le ()
590
     Return 1 (logical true) if the Or1ksim simulation is
591
     little-endian, 0 otherwise.
592
 
593
 
594
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
595 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
596
     specified in the configuration file.
597 19 jeremybenn
 
598
 
599
 -- `or1ksim.h': void or1ksim_interrupt (int I)
600 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
601
     interrupt is then immediately cleared automatically.  A warning
602 19 jeremybenn
     will be generated and the interrupt request ignored if level
603
     sensitive interrupts have been configured with the programmable
604
     interrupt controller (*note Interrupt Configuration: Interrupt
605
     Configuration.).
606
 
607
 
608
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
609 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
610 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
611 82 jeremybenn
     `or1ksim_interrupt_clear'.  A warning will be generated, and the
612 19 jeremybenn
     interrupt request ignored if edge sensitive interrupts have been
613
     configured with the programmable interrupt controller (*note
614
     Interrupt Configuration: Interrupt Configuration.).
615
 
616
 
617
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
618
     Clear a level-triggered interrupt on interrupt line I, which was
619 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
620 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
621
     edge sensitive interrupts have been configured with the
622
     programmable interrupt controller (*note Interrupt Configuration:
623
     Interrupt Configuration.).
624
 
625
 
626 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
627
     Drive a reset sequence through the JTAG interface. Return the
628
     (model) time taken for this action.  Remember that the JTAG has
629
     its own clock, which can be an order of magnitude slower than the
630
     main clock, so even a reset (5 JTAG cycles) could take 50
631
     processor clock cycles to complete.
632
 
633
 
634
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned
635
     char *JREG, int NUM_BITS)
636
 
637
     Shift the supplied register through the JTAG instruction register.
638
     Return the (model) time taken for this action. The register is
639
     supplied as a byte vector, with the least significant bits in the
640
     least significant byte.  If the total number of bits is not an
641
     exact number of bytes, then the odd bits are found in the least
642
     significant end of the highest numbered byte.
643
 
644
     For example a 12-bit register would have bits 0-7 in byte 0 and
645
     bits 11-8 in the least significant 4 bits of byte 1.
646
 
647
 
648
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned
649
     char *JREG, int NUM_BITS)
650
 
651
     Shift the supplied register through the JTAG data register.
652
     Return the (model) time taken for this action. The register is
653
     supplied as a byte vector, with the least significant bits in the
654
     least significant byte.  If the total number of bits is not an
655
     exact number of bytes, then the odd bits are found in the least
656
     significant end of the highest numbered byte.
657
 
658
     For example a 12-bit register would have bits 0-7 in byte 0 and
659
     bits 11-8 in the least significant 4 bits of byte 1.
660
 
661
 
662 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
663
installation directory (as specified with the `--prefix' option to the
664
`configure' script).
665
 
666
For example if the main installation directory is `/opt/or1ksim', the
667 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
668 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
669
(`libsim.so').
670
 
671
To link against the library add the `-lsim' flag when linking and do
672
one of the following:
673
 
674
   * Add the library directory to the `LD_LIBRARY_PATH' environment
675 82 jeremybenn
     variable during execution.  For example:
676 19 jeremybenn
 
677
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
678
 
679
   * Add the library directory to the `LD_RUN_PATH' environment
680 82 jeremybenn
     variable during linking.  For example:
681 19 jeremybenn
 
682
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
683
 
684
   * Use the linker `--rpath' option and specify the library directory
685 82 jeremybenn
     when linking your program.  For example
686 19 jeremybenn
 
687 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
688 19 jeremybenn
 
689
   * Add the library directory to `/etc/ld.so.conf'
690
 
691
 
692

693
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
694
 
695
3 Configuration
696
***************
697
 
698 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
699 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
700 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
701
the default `sim.cfg' is used.  The file is looked for first in the
702 19 jeremybenn
current directory, then in the `$HOME/.or1k' directory of the user.
703
 
704
* Menu:
705
 
706
* Configuration File Format::
707
* Simulator Configuration::
708
* Core OpenRISC Configuration::
709
* Peripheral Configuration::
710
 
711

712
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
713
 
714
3.1 Configuration File Format
715
=============================
716
 
717
The configuration file is a plain text file.
718
 
719
* Menu:
720
 
721
* Configuration File Preprocessing::
722
* Configuration File Syntax::
723
 
724

725
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
726
 
727
3.1.1 Configuration File Preprocessing
728
--------------------------------------
729
 
730 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
731 19 jeremybenn
`/*' and `*/').
732
 
733
Configure files may be included, using
734
 
735
     include FILENAME_TO_INCLUDE
736
 
737

738
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
739
 
740
3.1.2 Configuration File Syntax
741
-------------------------------
742
 
743
The configuration file is divided into a series of sections, with the
744
general form:
745
 
746
     section SECTION_NAME
747
 
748
       ...
749
 
750
     end
751
 
752
Sections may also have sub-sections within them (currently only the
753
ATA/ATAPI disc interface uses this).
754
 
755
Within a section, or sub-section are a series of parameter assignments,
756
one per line, withe the general form
757
 
758
       PARAMETER = VALUE
759
 
760
Depending on the parameter, the value may be a named value (an
761
enumeration), an integer (specified in any format acceptable in C) or a
762 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
763
mean "true" or "on" and the value "0" to mean "false" or "off".  An
764 19 jeremybenn
example from a memory section shows each of these
765
 
766
     section memory
767
       type    = random
768
       pattern = 0x00
769
       name    = "FLASH"
770
       ...
771
     end
772
 
773
Many parameters are optional and take reasonable default values if not
774 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
775 19 jeremybenn
parameter in `section memory') _must_ be specified.
776
 
777
Subsections are introduced by a keyword, with a parameter value (no `='
778 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
779 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
780
 
781
     section ata
782
       ...
783
       device 0
784
         type    = 1
785
         file = "FILENAME"
786
         ...
787
       enddevice
788
       ...
789
     end
790
 
791
Some sections (for example `section sim') should appear only once.
792
Others (for example `section memory' may appear multiple times.
793
 
794
Sections may be omitted, _unless they contain parameters which are
795 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
796 19 jeremybenn
is optional (for example whether it has a UART), then that
797 82 jeremybenn
functionality will not be provided.  If the section describes a part of
798 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
799
parameters of that section will take their default values.
800
 
801
All optional parts of the functionality are always described by
802
sections including a `enabled' parameter, which can be set to 0 to
803
ensure that functionality is explicitly omitted.
804
 
805
Even if a section is disabled, all its parameters will be read and
806 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
807
the Or1ksim command line (*note Interactive Command Line: Interactive
808 19 jeremybenn
Command Line.).
809
 
810
     Tip: It generally clearer to have sections describing _all_
811
     components, with omitted functionality explicitly indicated by
812
     setting the `enabled' parameter to 0
813
 
814
The following sections describe the various configuration sections and
815
the parameters which may be set in each.
816
 
817

818
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
819
 
820
3.2 Simulator Configuration
821
===========================
822
 
823
* Menu:
824
 
825
* Simulator Behavior::
826
* Verification API Configuration::
827
* CUC Configuration::
828
 
829

830
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
831
 
832
3.2.1 Simulator Behavior
833
------------------------
834
 
835 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
836
appear only once.  The following parameters may be specified.
837 19 jeremybenn
 
838
`verbose = 0|1'
839 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
840 19 jeremybenn
 
841
`debug = 0-9'
842 82 jeremybenn
 
843
     higher the value the greater the number of messages.  Default 0.
844
     Negative values will be treated as 0 (with a warning).  Values
845
     that are too large will be treated as 9 (with a warning).
846 19 jeremybenn
 
847
`profile = 0|1'
848
     If 1 (true) generate a profiling file using the file specified in
849 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
850 19 jeremybenn
 
851
`prof_file = ``FILENAME'''
852 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
853
     Default `sim.profile'.  For backwards compatibility, the
854
     alternative name `prof_fn' is supported for this parameter, but
855
     deprecated.
856 19 jeremybenn
 
857
`mprofile = 0|1'
858
     If 1 (true) generate a memory profiling file using the file
859
     specified in the `mprof_file' parameter or otherwise
860 82 jeremybenn
     `sim.mprofile'.  Default 0.
861 19 jeremybenn
 
862
`mprof_fn = ``FILENAME'''
863
     Specifies the file to be used with the `mprofile' parameter.
864 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
865 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
866
     deprecated.
867
 
868
`history = 0|1'
869 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
870 19 jeremybenn
 
871
          Note: Setting this parameter seriously degrades performance.
872
 
873
          Note: If this execution flow tracking is enabled, then
874
          `dependstats' must be enabled in the CPU configuration
875
          section (*note CPU Configuration: CPU Configuration.).
876
 
877
`exe_log = 0|1'
878 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
879
     file specified in parameter `exe_log_file'.  Default 0.
880 19 jeremybenn
 
881
          Note: Setting this parameter seriously degrades performance.
882
 
883
`exe_log_type = default|hardware|simple|software'
884
     Type of execution log to produce.
885
 
886
    `default'
887 82 jeremybenn
          Produce default output for the execution log.  In the current
888 19 jeremybenn
          implementation this is the equivalent of `hardware'.
889
 
890
    `hardware'
891
          After each instruction execution, log the number of
892
          instructions executed so far, the next instruction to execute
893
          (in hex), the general purpose registers (GPRs), status
894
          register, exception program counter, exception, effective
895
          address register and exception status register.
896
 
897
    `simple'
898
          After each instruction execution, log the number of
899
          instructions executed so far and the next instruction to
900
          execute, symbolically disassembled.
901
 
902
    `software'
903
          After each instruction execution, log the number of
904
          instructions executed so far and the next instruction to
905 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
906 19 jeremybenn
          each operand to the instruction.
907
 
908
 
909 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
910 19 jeremybenn
     insensitive) will be treated as the default with a warning.
911
 
912
          Note: Execution logs can be _very_ big.
913
 
914
`exe_log_start = VALUE'
915 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
916 19 jeremybenn
 
917
`exe_log_end = VALUE'
918 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
919
     once started logging will continue until the simulator exits).
920 19 jeremybenn
 
921
`exe_log_marker = VALUE'
922
     Specifies the number of instructions between printing horizontal
923 82 jeremybenn
     markers.  Default is to produce no markers.
924 19 jeremybenn
 
925
`exe_log_file = FILENAME'
926
     Filename for the execution log filename if `exe_log' is enabled.
927 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
928 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
929
     deprecated.
930
 
931
`clkcycle = VALUE[ps|ns|us|ms]'
932 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
933
     specified, `ps' is assumed.  Default 4000ps (250MHz).
934 19 jeremybenn
 
935
 
936

937
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
938
 
939
3.2.2 Verification API (VAPI) Configuration
940
-------------------------------------------
941
 
942
The Verification API (VAPI) provides a TCP/IP interface to allow
943 82 jeremybenn
components of the simulation to be controlled externally.  *Note
944 19 jeremybenn
Verification API: Verification API, for more details.
945
 
946 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
947
section may appear at most once.  The following parameters may be
948 19 jeremybenn
specified.
949
 
950
`enabled = 0|1'
951
     If 1 (true), verification API is enabled and its server started.
952
     If 0 (the default), it is disabled.
953
 
954
`server_port = VALUE'
955
     When VAPI is enabled, communication will be via TCP/IP on the port
956 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
957 19 jeremybenn
     The default value is 50000.
958
 
959 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
960 19 jeremybenn
          practice suggests users should adopt port values in the
961 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
962 19 jeremybenn
 
963
`log_enabled = 0|1'
964
     If 1 (true), all VAPI requests and sent commands will be logged.
965 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
966 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
967
 
968
          Caution: This can generate a substantial amount of file I/O
969
          and seriously degrade simulator performance.
970
 
971
`hide_device_id = 0|1'
972 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
973
     device ID.  This feature (when set to 1) is provided for backwards
974 19 jeremybenn
     compatibility with an old version of VAPI.
975
 
976
`vapi_log_file = "FILENAME"'
977
     Use `filename' as the file for logged data is logging is enabled
978 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
979 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
980
     supported for this parameter, but deprecated.
981
 
982
 
983

984
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
985
 
986
3.2.3 Custom Unit Compiler (CUC) Configuration
987
----------------------------------------------
988
 
989
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
990 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
991
beyond the initial prototype phase.  The configuration parameters are
992 19 jeremybenn
described here for the record.
993
 
994 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
995
appear at most once.  The following parameters may be specified.
996 19 jeremybenn
 
997
`memory_order = none|weak|strong|exact'
998
     This parameter specifies the memory ordering required:
999
 
1000
    `memory_order=none'
1001
          Different memory ordering, even if there are dependencies.
1002
          Bursts can be made, width can change.
1003
 
1004 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
1005 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
1006
          change.
1007
 
1008 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
1009 19 jeremybenn
 
1010
          Exactly the same memory ordering and widths.
1011
 
1012
 
1013 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1014 19 jeremybenn
     orderings are ignored with a warning.
1015
 
1016
`calling_convention = 0|1'
1017 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1018 19 jeremybenn
     (the default), they may use other convenitions.
1019
 
1020
`enable_bursts = 0 | 1'
1021 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1022 19 jeremybenn
     not detected.
1023
 
1024
`no_multicycle = 0 | 1'
1025 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1026
     (the default), multicycle logic paths will be generated.
1027 19 jeremybenn
 
1028
`timings_file = "FILENAME"'
1029 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1030
     default value is `"virtex.tim"'.  For backwards compatibility, the
1031 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1032
     deprecated.
1033
 
1034
 
1035

1036
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1037
 
1038
3.3 Configuring the OpenRISC Architectural Components
1039
=====================================================
1040
 
1041
* Menu:
1042
 
1043
* CPU Configuration::
1044
* Memory Configuration::
1045
* Memory Management Configuration::
1046
* Cache Configuration::
1047
* Interrupt Configuration::
1048
* Power Management Configuration::
1049
* Branch Prediction Configuration::
1050
* Debug Interface Configuration::
1051
 
1052

1053
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1054
 
1055
3.3.1 CPU Configuration
1056
-----------------------
1057
 
1058 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1059
appear only once.  At present Or1ksim does not model multi-CPU systems.
1060 19 jeremybenn
The following parameters may be specified.
1061
 
1062
`ver = VALUE'
1063
 
1064
`cfg = VALUE'
1065
 
1066
`rev = VALUE'
1067
     The values are used to form the corresponding fields in the `VR'
1068 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1069 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1070
     and `cfg', 6 bits for `rev').
1071
 
1072
`upr = VALUE'
1073
     Used as the value of the Unit Present Register (UPR) Special
1074 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1075 19 jeremybenn
     i.e.
1076
        * UPR present (0x00000001)
1077
 
1078
        * Data cache present (0x00000002)
1079
 
1080
        * Instruction cache present (0x00000004)
1081
 
1082
        * Data MMY present (0x00000008)
1083
 
1084
        * Instruction MMU present (0x00000010)
1085
 
1086
        * Debug unit present (0x00000040)
1087
 
1088
        * Power management unit present (0x00000100)
1089
 
1090
        * Programmable interrupt controller present (0x00000200)
1091
 
1092
        * Tick timer present (0x00000400)
1093
 
1094
     However, with the exection of the UPR present (0x00000001) and tick
1095
     timer present, the various fields will be modified with the values
1096
     specified in their corresponding configuration sections.
1097
 
1098
`cfgr = VALUE'
1099
     Sets the CPU configuration register (Special Purpose Register 2) to
1100 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1101
     instruction set.  Attempts to set any other value are accepted, but
1102 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1103
 
1104
`sr = VALUE'
1105
     Sets the supervision register Special Purpose Register (SPR 0x11)
1106 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1107 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1108
 
1109 98 jeremybenn
          Note: This is particularly useful when an image is held in
1110
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1111
          so that interrupt vectors are basedf at 0xf0000000, rather
1112
          than 0x0.
1113
 
1114 19 jeremybenn
`superscalar = 0|1'
1115 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1116 19 jeremybenn
     0.
1117
 
1118
     In the current simulator, the only functional effect of superscalar
1119
     mode is to affect the calculation of the number of cycles taken to
1120
     execute an instruction.
1121
 
1122
          Caution: The code for this does not appear to be complete or
1123
          well tested, so users are advised not to use this option.
1124
 
1125
`hazards = 0|1'
1126 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1127
     value is 0.
1128 19 jeremybenn
 
1129
     In the current simulator, the only functional effect is to cause
1130
     logging of hazard waiting information if the CPU is superscalar.
1131
     However nowhere in the simulator is this data actually computed,
1132
     so the net result is probably to have no effect.
1133
 
1134
     if harzards are tracked, current hazards can be displayed using the
1135
     simulator's `r' command.
1136
 
1137
          Caution: The code for this does not appear to be complete or
1138
          well tested, so users are advised not to use this option.
1139
 
1140
`dependstats = 0|1'
1141 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1142
     value 0.
1143 19 jeremybenn
 
1144
     If these values are calculated, the depencies can be displayed
1145
     using the simulator's `stat' command.
1146
 
1147
          Note: This field must be enabled, if execution execution flow
1148
          tracking (field `history') has been requested in the simulator
1149
          configuration section (*note Simulator Behavior: Simulator
1150
          Behavior.).
1151
 
1152
`sbuf_len = VALUE'
1153
     The length of the store buffer is set to VALUE, which must be no
1154 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1155
     warning.  Negative values will be treated as 0 with a warning.
1156
     Use 0 to disable the store buffer.
1157 19 jeremybenn
 
1158
     When the store buffer is active, stores are accumulated and
1159
     committed when I/O is idle.
1160
 
1161 100 julius
`hardfloat = 0|1'
1162
     If 1, hardfloat instructions are enabled. Default value 0.
1163 19 jeremybenn
 
1164 104 jeremybenn
 
1165 19 jeremybenn

1166
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1167
 
1168
3.3.2 Memory Configuration
1169
--------------------------
1170
 
1171 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1172 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1173 19 jeremybenn
 
1174 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1175
     controller. If a memory controller is enabled, then the standard
1176
     OpenRISC C libraries will initialize it to expect 64MB memory
1177
     blocks, and any memory declarations _must_ reflect this.  The
1178
     section describing memory controller configuration describes the
1179
     steps necessary for using smaller or larger memory sections (*note
1180
     Memory Controller Configuration: Memory Controller Configuration.).
1181
 
1182
     If a memory controller is _not_ enabled, then the standard C
1183
     library code will generate memory access errors.  The solution is
1184
     to declare an additional writable memory block, mimicing the memory
1185
     controller's register bank as follows.
1186
 
1187
          section memory
1188
            pattern = 0x00
1189
            type = unknown
1190
            name = "MC shadow"
1191
            baseaddr = 0x93000000
1192
            size     = 0x00000080
1193
            delayr = 2
1194
            delayw = 4
1195
          end
1196
 
1197
 
1198
The following parameters may be specified.
1199
 
1200 19 jeremybenn
`type=random|pattern|unknown|zero'
1201 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1202 19 jeremybenn
     default value is `unknown'.
1203
 
1204
    `random'
1205 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1206 19 jeremybenn
          random generator may be set using the `random_seed' field in
1207
          this section (see below), thus ensuring the same "random"
1208
          values are used each time.
1209
 
1210
    `pattern'
1211
          Set the memory values to be a pattern value, which is set
1212
          using the `pattern' field in this section (see below).
1213
 
1214
    `unknown'
1215 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1216 19 jeremybenn
          This option will yield faster initialization of the simulator.
1217
 
1218
    `zero'
1219 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1220 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1221
          such.
1222
 
1223
               Note: As a consequence, if the `pattern' field is
1224
               _subsequently_ specified in this section, the value in
1225
               that field will be used instead of zero to initialize
1226
               the memory.
1227
 
1228
 
1229
`random_seed = VALUE'
1230 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1231 19 jeremybenn
     has any effect for memory type `random'.
1232
 
1233
     The default value is -1, which means the seed will be set from a
1234
     call to the `time' function, thus ensuring different random values
1235 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1236 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1237
     values used in any particular run.
1238
 
1239
`pattern = VALUE'
1240 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1241
     default value is 0.  This only has any effect for memory type
1242
     `pattern'.  The least significant 8 bits of this value is used to
1243
     initialize each byte.  More than 8 bits can be specified, but will
1244 19 jeremybenn
     ignored with a warning.
1245
 
1246
          Tip: The default value, is equivalent to setting the memory
1247 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1248 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1249
          and not specifying a value for `pattern'.
1250
 
1251
`baseaddr = VALUE'
1252 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1253 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1254
     The default value is 0.
1255
 
1256
`size = VALUE'
1257 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1258
     be a multiple of 4 (i.e.  word aligned).  The default value is
1259
     1024.
1260 19 jeremybenn
 
1261
          Note: When allocating memory, the simulator will allocate the
1262
          nearest 2^n bytes greater than or equal to VALUE, and will not
1263
          notice memory misses in any part of the memory between VALUE
1264
          and the amount allocated.
1265
 
1266
          As a consequence users are strongly recommended to specify
1267 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1268 19 jeremybenn
          amount of memory is required, it should be specified as
1269
          separate, contiguous blocks, each of which is a power of 2 in
1270
          size.
1271
 
1272
`name = "TEXT"'
1273 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1274
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1275 19 jeremybenn
     `"anonymous memory block"'.
1276
 
1277
          Note: It is not clear that this information is currently ever
1278 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1279 19 jeremybenn
          command of the simulator ignores it.
1280
 
1281
`ce = VALUE'
1282 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1283 19 jeremybenn
     instance should have a unique chip enable index, which should be
1284 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1285 19 jeremybenn
     controller when identifying different memory instances.
1286
 
1287 98 jeremybenn
     There is no requirement to set  `ce' if a memory controller is not
1288
     enabled. The default value is -1 (invalid).
1289 19 jeremybenn
 
1290
`mc = VALUE'
1291 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1292 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1293
     for a memory controller (*note Memory Controller Configuration:
1294
     Memory Controller Configuration.).
1295
 
1296 98 jeremybenn
     There is no requirement to set  `mc' if a memory controller is not
1297
     enabled. Default value is 0, which is also the default value of a
1298
     memory controller `index' field.  This is suitable therefore for
1299
     designs with just one memory controller.
1300 19 jeremybenn
 
1301
`delayr = VALUE'
1302 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1303
     memory does not support reading.  Default value 1.  The simulator
1304 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1305
     count when reading from main memory.
1306
 
1307
`delayw = VALUE'
1308 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1309
     memory does not support writing.  Default value 1.  The simulator
1310 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1311
     count when writing to main memory.
1312
 
1313
`log = "FILE"'
1314
     If specified, `file' names a file for all memory accesses to be
1315 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1316 19 jeremybenn
     that the memory is not logged.
1317
 
1318
 
1319

1320
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1321
 
1322
3.3.3 Memory Management Configuration
1323
-------------------------------------
1324
 
1325
Memory Management Unit (MMU) configuration is described in `section
1326
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1327 82 jeremybenn
Each section should appear at most once.  The following parameters may
1328 19 jeremybenn
be specified.
1329
 
1330
`enabled = 0|1'
1331
     If 1 (true), the data or instruction (as appropriate) MMU is
1332 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1333 19 jeremybenn
 
1334
`nsets = VALUE'
1335
     Sets the number of data or instruction (as appropriate) TLB sets to
1336 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1337
     which do not fit these criteria are ignored with a warning.  The
1338 19 jeremybenn
     default value is 1.
1339
 
1340
`nways = VALUE'
1341
     Sets the number of data or instruction (as appropriate) TLB ways to
1342 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1343
     this range are ignored with a warning.  The default value is 1.
1344 19 jeremybenn
 
1345
`pagesize = VALUE'
1346
     The data or instruction (as appropriate) MMU page size is set to
1347 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1348
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1349 19 jeremybenn
 
1350
`entrysize = VALUE'
1351
     The data or instruction (as appropriate) MMU entry size is set to
1352 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1353
     of 2 are ignored with a warning.  The default value is 1.
1354 19 jeremybenn
 
1355
          Note: Or1ksim does not appear to use the `entrysize' parameter
1356 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1357 19 jeremybenn
          not seem to matter.
1358
 
1359
`ustates = VALUE'
1360
     The number of instruction usage states for the data or instruction
1361
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1362 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1363 19 jeremybenn
     value is 2.
1364
 
1365
          Note: Or1ksim does not appear to use the `ustates' parameter
1366 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1367 19 jeremybenn
          not seem to matter.
1368
 
1369
`hitdelay = VALUE'
1370
     Set the number of cycles a data or instruction (as appropriate) MMU
1371 82 jeremybenn
     hit costs.  Default value 1.
1372 19 jeremybenn
 
1373
`missdelay = VALUE'
1374
     Set the number of cycles a data or instruction (as appropriate) MMU
1375 82 jeremybenn
     miss costs.  Default value 1.
1376 19 jeremybenn
 
1377
 
1378

1379
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1380
 
1381
3.3.4 Cache Configuration
1382
-------------------------
1383
 
1384
Cache configuration is described in `section dc' (for the data cache)
1385 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1386
appear at most once.  The following parameters may be specified.
1387 19 jeremybenn
 
1388
`enabled = 0|1'
1389
     If 1 (true), the data or instruction (as appropriate) cache is
1390 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1391 19 jeremybenn
 
1392
`nsets = VALUE'
1393
     Sets the number of data or instruction (as appropriate) cache sets
1394
     to VALUE, which must be a power of two, not exceeding
1395
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1396 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1397
     both defined in the code to be 1024).  The default value is 1.
1398 19 jeremybenn
 
1399
`nways = VALUE'
1400
     Sets the number of data or instruction (as appropriate) cache ways
1401
     to VALUE, which must be a power of two, not exceeding
1402
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1403 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1404
     both defined in the code to be 32).  The default value is 1.
1405 19 jeremybenn
 
1406
`blocksize = VALUE'
1407
     The data or instruction (as appropriate) cache block size is set to
1408 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1409 19 jeremybenn
 
1410
`ustates = VALUE'
1411
     The number of instruction usage states for the data or instruction
1412
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1413
     The default value is 2.
1414
 
1415
`hitdelay = VALUE'
1416 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1417
     cache hit costs.  Default value 1.
1418 19 jeremybenn
 
1419
`missdelay = VALUE'
1420 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1421
     cache miss costs.  Default value 1.
1422 19 jeremybenn
 
1423
`load_hitdelay = VALUE'
1424 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1425
     costs.  Default value 2.
1426 19 jeremybenn
 
1427
`load_missdelay = VALUE'
1428 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1429
     miss costs.  Default value 2.
1430 19 jeremybenn
 
1431
`store_hitdelay = VALUE'
1432 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1433
     costs.  Default value 0.
1434 19 jeremybenn
 
1435
`store_missdelay = VALUE'
1436 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1437
     miss costs.  Default value 0.
1438 19 jeremybenn
 
1439
 
1440

1441
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1442
 
1443
3.3.5 Interrupt Configuration
1444
-----------------------------
1445
 
1446
Programmable Interrupt Controller (PIC) configuration is described in
1447 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1448
mechanism for handling multiple interrupt controllers.  The following
1449 19 jeremybenn
parameters may be specified.
1450
 
1451
`enabled = 0|1'
1452 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1453
 
1454 19 jeremybenn
 
1455
`edge_trigger = 0|1'
1456
     If 1 (true, the default), the programmable interrupt controller is
1457 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1458 19 jeremybenn
 
1459
 
1460

1461
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1462
 
1463
3.3.6 Power Management Configuration
1464
------------------------------------
1465
 
1466 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1467 19 jeremybenn
(which only happens when the power management unit is enabled) of
1468
setting the different bits in the power management Special Purpose
1469
Register (PMR, SPR 0x4000) is
1470
 
1471
`SDF (bit mask 0x0000000f)'
1472
     No effect - these bits are ignored
1473
 
1474
`DME (bit mask 0x00000010)'
1475
`SME (bit mask 0x00000020)'
1476
     Both these bits cause the processor to stop executing
1477 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1478 19 jeremybenn
     VAPI etc) carry on as normal.
1479
 
1480
`DCGE (bit mask 0x00000004)'
1481
     No effect - this bit is ignored
1482
 
1483
`SUME (bit mask 0x00000008)'
1484
     Enabling this bit causes a message to be printed, advising that the
1485
     processor is suspending and the simulator exits.
1486
 
1487
 
1488
On reset all bits are cleared.
1489
 
1490 82 jeremybenn
Power management configuration is described in `section pm'.  This
1491
section may appear at most once.  The following parameter may be
1492 19 jeremybenn
specified.
1493
 
1494
`enabled = 0|1'
1495 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1496
     is disabled.
1497 19 jeremybenn
 
1498
 
1499

1500
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1501
 
1502
3.3.7 Branch Prediction Configuration
1503
-------------------------------------
1504
 
1505
From examining the code base, it seems the branch prediction function
1506 82 jeremybenn
is not fully implemented.  At present the functionality seems
1507
restricted to collection of statistics.
1508 19 jeremybenn
 
1509 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1510
section may appear at most once.  The following parameters may be
1511 19 jeremybenn
specified.
1512
 
1513
`enabled = 0|1'
1514 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1515 19 jeremybenn
     is disabled.
1516
 
1517
`btic = 0|1'
1518
     If 1 (true), the branch target instruction cache model is enabled.
1519
     If 0 (the default), it is disabled.
1520
 
1521
`sbp_bf_fwd = 0|1'
1522 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1523 19 jeremybenn
 
1524
     instruction.
1525
 
1526
`sbp_bnf_fwd = 0|1'
1527 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1528
     If 0 (the default), do not use forward prediction for this
1529 19 jeremybenn
     instruction.
1530
 
1531
`hitdelay = VALUE'
1532 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1533 19 jeremybenn
     value 0.
1534
 
1535
`missdelay = VALUE'
1536 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1537 19 jeremybenn
     value 0.
1538
 
1539
 
1540

1541
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1542
 
1543
3.3.8 Debug Interface Configuration
1544
-----------------------------------
1545
 
1546
The debug unit and debug interface configuration is described in
1547 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1548 19 jeremybenn
parameters may be specified.
1549
 
1550
`enabled = 0|1'
1551 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1552 19 jeremybenn
     disabled.
1553
 
1554
          Note: This enables the functionality of the debug unit (its
1555 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1556
          external interface to the debug unit.  For that, see
1557 19 jeremybenn
          `gdb_enabled' and `rsp_enabled' below.
1558
 
1559
`rsp_enabled = 0|1'
1560
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1561
     provding an interface to an external GNU debugger, using the port
1562
     specified in the `rsp_port' field (see below), or the
1563 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1564 19 jeremybenn
     not started, and no external interface is provided.
1565
 
1566
     For more detailed information on the interface to the GNU Debugger
1567
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1568
     Practical Experience with the OpenRISC 1000 Architecture', by
1569
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1570
 
1571 82 jeremybenn
          Note: `rsp_enabled' may not be enabled with `gdb_enabled' (see
1572
          below).  If both are enabled, a warning is issued and only
1573
          the "Remote Serial Protocol" interface is enabled.
1574 19 jeremybenn
 
1575
`rsp_port = VALUE'
1576
     VALUE specifies the port to be used for the GDB "Remote Serial
1577 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1578
     51000.  If the value 0 is specified, Or1ksim will instead look for
1579 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1580
 
1581
          Tip: There is no registered port for Or1ksim "Remote Serial
1582 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1583
          users should adopt port values in the "Dynamic" or "Private"
1584
          port range, i.e.  49152-65535.
1585 19 jeremybenn
 
1586
`gdb_enabled = 0|1'
1587
     If 1 (true), the OpenRISC Remote JTAG protocol server is started,
1588
     provding an interface to an external GNU debugger, using the port
1589
     specified in the `server_port' field (see below), or the `or1ksim'
1590 82 jeremybenn
     TCP/IP service.  If 0 (the default), the server is not started,
1591
     and no external interface is provided.
1592 19 jeremybenn
 
1593
     For more detailed information on the interface to the GNU Debugger
1594
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1595
     Practical Experience with the OpenRISC 1000 Architecture', by
1596
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1597
 
1598
          Note: The OpenRISC Remote JTAG protocol is unique to
1599 82 jeremybenn
          OpenRISC, and remains only for backward compatibility.  New
1600 19 jeremybenn
          users should adopt the standard GDB "Remote Serial Protocol"
1601
          interface (see `rsp_enabled' above) providing access to a
1602
          wider range of GDB functionality.
1603
 
1604 82 jeremybenn
          Note: `gdb_enabled' may not be enabled with `rsp_enabled'.
1605
          If both are enabled, a warning is issued and only the "Remote
1606 19 jeremybenn
          Serial Protocol" interface is enabled.
1607
 
1608
`server_port = VALUE'
1609
     VALUE specifies the port to be used for the OpenRISC Rmote JTAG
1610 82 jeremybenn
     protocol interface to the GNU Debugger (GDB).  Default value
1611
     51000.  If the value 0 is specified, Or1ksim will instead look for
1612
     a TCP/IP service named `or1ksim'.
1613 19 jeremybenn
 
1614
          Tip: There is no registered port for Or1ksim Remote JTAG
1615 82 jeremybenn
          Interface or service `or1ksim'.  Good practice suggests users
1616 19 jeremybenn
          should adopt port values in the "Dynamic" or "Private" port
1617 82 jeremybenn
          range, i.e.  49152-65535.
1618 19 jeremybenn
 
1619
`vapi_id = VALUE'
1620
     VALUE specifies the value of the Verification API (VAPI) base
1621 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1622 19 jeremybenn
     Verification API, for more details.
1623
 
1624
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1625
     JTAG protocol transactions will be logged to the VAPI log file, if
1626 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
1627
     the debug unit.  No VAPI commands are sent, nor requests handled.
1628 19 jeremybenn
 
1629
 
1630

1631
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
1632
 
1633
3.4 Configuring Memory Mapped Peripherals
1634
=========================================
1635
 
1636 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1637 19 jeremybenn
(unlike other components) by default they are enabled.
1638
 
1639
* Menu:
1640
 
1641
* Memory Controller Configuration::
1642
* UART Configuration::
1643
* DMA Configuration::
1644
* Ethernet Configuration::
1645
* GPIO Configuration::
1646
* Display Interface Configuration::
1647
* Frame Buffer Configuration::
1648
* Keyboard Configuration::
1649
* Disc Interface Configuration::
1650
* Generic Peripheral Configuration::
1651
 
1652

1653
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
1654
 
1655
3.4.1 Memory Controller Configuration
1656
-------------------------------------
1657
 
1658
The memory controller used in Or1ksim is the component implemented at
1659 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
1660 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
1661 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1662
memory mapped component, which resides on the main OpenRISC Wishbone
1663
data bus.
1664 19 jeremybenn
 
1665 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
1666 19 jeremybenn
section may appear multiple times, specifying multiple memory
1667 98 jeremybenn
controllers.
1668 19 jeremybenn
 
1669 98 jeremybenn
     Caution: The standard OpenRISC C libraries will initialize the
1670
     memory controller to expect 64MB memory blocks, and any memory
1671
     declarations _must_ reflect this.
1672
 
1673
     If smaller memory blocks are declared with a memory controller,
1674
     then sufficient memory will not be allocated by Or1ksim, but out of
1675
     range memory accesses will not be trapped. For example declaring a
1676
     memory section from 0-4MB with a memory controller enabled would
1677
     mean that accesses between 4MB and 64MB would be permitted, but
1678
     having no allocated memory would likely cause a segmentation fault.
1679
 
1680
     If the user is determined to use smaller memories with the memory
1681
     controller, then custom initialization code must be provided, to
1682
     ensure the memory controller traps out-of-memory accesses.
1683
 
1684
The following parameters may be specified.
1685
 
1686 19 jeremybenn
`enabled = 0|1'
1687 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
1688
     0, it is disabled.
1689 19 jeremybenn
 
1690
          Note: The memory controller can effectively also be disabled
1691
          by setting an appropriate power on control register value
1692 82 jeremybenn
          (see below).  However this should only be used if it is
1693 19 jeremybenn
          desired to specifically model this behavior of the memory
1694
          controller, not as a way of disabling the memory controller
1695
          in general.
1696
 
1697
`baseaddr = VALUE'
1698
     Set the base address of the memory controller's memory mapped
1699 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
1700 19 jeremybenn
     sensible value.
1701
 
1702
     The memory controller has a 7 bit address bus, with a total of 19
1703
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1704
     addresses 0x50 through 0x7c are not used).
1705
 
1706
`poc = VALUE'
1707
     Specifies the value of the power on control register, The least
1708
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
1709
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
1710
     the type of memory connected (use 0 for a disabled interface, 1
1711
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
1712
     devices).
1713
 
1714
     If other bits are specified, they are ignored with a warning.
1715
 
1716
          Caution: The default value, 0, corresponds to a disabled
1717
          8-bit bus, and is likely not the most suitable value
1718
 
1719
`index = VALUE'
1720
     Specify the index of this memory controller amongst all the memory
1721 82 jeremybenn
     controllers.  This value should be unique for each memory
1722 19 jeremybenn
     controller, and is used to associate specific memories with the
1723
     controller, through the `mc' field in the `section memory'
1724
     configuration (*note Memory Configuration: Memory Configuration.).
1725
 
1726
     The default value, 0, is suitable when there is only one memory
1727
     controller.
1728
 
1729
 
1730

1731
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
1732
 
1733
3.4.2 UART Configuration
1734
------------------------
1735
 
1736
The UART implemented in Or1ksim follows the specification of the
1737 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
1738 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
1739
 
1740
The component provides a number of interfaces to emulate the behavior
1741
of an external terminal connected to the UART.
1742
 
1743 82 jeremybenn
UART configuration is described in `section uart'.  This section may
1744
appear multiple times, specifying multiple UARTs.  The following
1745 19 jeremybenn
parameters may be specified.
1746
 
1747
`enabled = 0|1'
1748 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
1749 19 jeremybenn
     disabled.
1750
 
1751
`baseaddr = VALUE'
1752
     Set the base address of the UART's memory mapped registers to
1753 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1754 19 jeremybenn
 
1755
     The UART has a 3 bit address bus, with a total of 8 8-bit
1756
     registers, at addresses 0x0 through 0x7.
1757
 
1758
`channel = "TYPE:ARGS"'
1759
     Specify the channel representing the terminal connected to the UART
1760
     Rx & Tx pins.
1761
 
1762
    `channel="file:`rxfile',`txfile'"'
1763
          Read input characters from the file `rxfile' and write output
1764
          characters to the file `txfile' (which will be created if
1765
          required).
1766
 
1767
    `channel="xterm:ARGS"'
1768
          Create an xterm on startup, write UART Tx traffic to the
1769
          xterm and take Rx traffic from the keyboard when the xterm
1770 82 jeremybenn
          window is selected.  Additional arguments to the xterm
1771
          command (for example specifying window size may be specified
1772
          in ARGS, or this may be left blank.
1773 19 jeremybenn
 
1774
    `channel="tcp:VALUE"'
1775
          Open the TCP/IP port specified by VALUE and read and write
1776
          UART traffic from and to it.
1777
 
1778
          Typically a telnet session is connected to the other end of
1779
          this port.
1780
 
1781
               Tip: There is no registered port for Or1ksim telnet UART
1782 82 jeremybenn
               connection.  Priviledged access is required to read
1783 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
1784
               Instead users should use port values in the "Dynamic" or
1785 82 jeremybenn
               "Private" port range, i.e.  49152-65535.
1786 19 jeremybenn
 
1787
    `channel="fd:`rxfd',`txfd'"'
1788
          Read and write characters from and to the existing open
1789
          numerical file descriptors, file `rxfd' and `txfd'.
1790
 
1791
    `channel="tty:device=/dev/ttyS0,baud=9600"'
1792
          Read and write characters from and to a physical serial port.
1793
          The precise device (shown here as `/dev/ttyS0') may vary from
1794
          machine to machine.
1795
 
1796
 
1797
     The default value for this field is `"xterm:"'.
1798
 
1799
`irq = VALUE'
1800 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
1801 19 jeremybenn
 
1802
`16550 = 0|1'
1803 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
1804
     default), it has the functionality of a 16450.  The principal
1805 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
1806
 
1807
`jitter = VALUE'
1808
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
1809 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
1810 19 jeremybenn
 
1811
          Note: This functionality has yet to be implemented, so this
1812
          parameter has no effect.
1813
 
1814
`vapi_id = VALUE'
1815
     VALUE specifies the value of the Verification API (VAPI) base
1816 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
1817 19 jeremybenn
     Verification API, for more details, which details the use of the
1818
     VAPI with the UART.
1819
 
1820
 
1821

1822
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
1823
 
1824
3.4.3 DMA Configuration
1825
-----------------------
1826
 
1827
The DMA controller used in Or1ksim is the component implemented at
1828 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
1829 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
1830 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1831
memory mapped component, which resides on the main OpenRISC Wishbone
1832
data bus.  The present implementation is incomplete, intended only to
1833
support the Ethernet interface (*note Ethernet Configuration::),
1834
although the Ethernet interface is not yet completed.
1835 19 jeremybenn
 
1836 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
1837
appear multiple times, specifying multiple DMA controllers.  The
1838 19 jeremybenn
following parameters may be specified.
1839
 
1840
`enabled = 0|1'
1841 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
1842
     it is disabled.
1843 19 jeremybenn
 
1844
`baseaddr = VALUE'
1845
     Set the base address of the DMA's memory mapped registers to
1846 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1847 19 jeremybenn
 
1848
     The DMA controller has a 10 bit address bus, with a total of 253
1849 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
1850
     0x010 control the overall behavior of the DMA controller.  There
1851
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
1852
     channels available.  Addresses 0x014 through 0x01c are not used.
1853 19 jeremybenn
 
1854
`irq = VALUE'
1855 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
1856 19 jeremybenn
     0.
1857
 
1858
`vapi_id = VALUE'
1859
     VALUE specifies the value of the Verification API (VAPI) base
1860 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
1861 19 jeremybenn
     API: Verification API, for more details, which details the use of
1862
     the VAPI with the DMA controller.
1863
 
1864
 
1865

1866
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
1867
 
1868
3.4.4 Ethernet Configuration
1869
----------------------------
1870
 
1871
The Ethernet MAC used in Or1ksim is the component implemented at
1872 98 jeremybenn
OpenCores, and found in the top level SVN directory, `ethmac'.  It also
1873
forms part of the OpenRISC SoC, ORPSoC.  It is described in the
1874 19 jeremybenn
document `Ethernet IP Core Specification' by Igor Mohor, which can be
1875 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1876
which resides on the main OpenRISC Wishbone data bus.
1877 19 jeremybenn
 
1878 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
1879
section may appear multiple times, specifying multiple Ethernet
1880
interfaces.  The following parameters may be specified.
1881 19 jeremybenn
 
1882
`enabled = 0|1'
1883 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
1884
     is disabled.
1885 19 jeremybenn
 
1886
`baseaddr = VALUE'
1887
     Set the base address of the MAC's memory mapped registers to
1888 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1889 19 jeremybenn
 
1890
     The Ethernet MAC has a 7-bit address bus, with a total of 21
1891 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
1892 19 jeremybenn
 
1893
          Note: The Ethernet specification describes a Tx control
1894 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
1895
          is not implemented in the Or1ksim model.
1896 19 jeremybenn
 
1897
`dma = VALUE'
1898
     VALUE specifies the DMA controller with which this Ethernet is
1899 82 jeremybenn
     associated.  The default value is 0.
1900 19 jeremybenn
 
1901
          Note: Support for external DMA is not provided in the current
1902 82 jeremybenn
          implementation, and this value is ignored.  In any case there
1903 19 jeremybenn
          is no equivalent field to which this can be matched in the
1904
          current DMA component implementation (*note DMA
1905
          Configuration: DMA Configuration.).
1906
 
1907
`irq = VALUE'
1908 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
1909 19 jeremybenn
 
1910
`rtx_type = 0|1'
1911
     If 1 (true) use a socket interface to the Ethernet (see parameter
1912 82 jeremybenn
     `sockif' below).  If 0 (the default), use a file interface,
1913
     reading and writing from and to the files specified in the
1914
     `rxfile' and `txfile' parameters (see below).
1915 19 jeremybenn
 
1916
          Note: By default the socket interface is not provided in
1917 82 jeremybenn
          Or1ksim.  If it is required, this must be requested when
1918 19 jeremybenn
          configuring, by use of the `--enable-ethphy' option to
1919
          `configure'.
1920
 
1921
               configure --target=or32-uclinux --enable-ethphy ...
1922
 
1923
`rx_channel = RXVALUE'
1924
`tx_channel = TXVALUE'
1925
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
1926 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
1927 19 jeremybenn
 
1928
          Note: As noted above, support for external DMA is not
1929
          provided in the current implementation, and so these values
1930
          are ignored.
1931
 
1932
`rxfile = "RXFILE"'
1933
`txfile = "TXFILE"'
1934
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
1935
     as input and TXFILE specifies the fie to use as output.
1936
 
1937 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
1938
     packet length (32 bits), followed by that many bytes of data.
1939
     Once the input file is empty, the Ethernet MAC behaves as though
1940
     there were no data on the Ethernet.  The default values of these
1941 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
1942
 
1943 82 jeremybenn
     The input file must exist and be readable.  The output file must be
1944
     writable and will be created if necessary.  If either of these
1945 19 jeremybenn
     conditions is not met, a warning will be given.
1946
 
1947
`sockif = "SERVICE"'
1948
     When `rtx_type' is 1 (see above), SERVICE specifies the service to
1949 82 jeremybenn
     use for communication.  This may be TCP/IP or UDP/IP.  The default
1950 19 jeremybenn
     value of this parameter is `"or1ksim_eth"'.
1951
 
1952
`vapi_id = VALUE'
1953
     VALUE specifies the value of the Verification API (VAPI) base
1954 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
1955 19 jeremybenn
     Verification API, for more details, which details the use of the
1956
     VAPI with the DMA controller.
1957
 
1958
 
1959

1960
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
1961
 
1962
3.4.5 GPIO Configuration
1963
------------------------
1964
 
1965
The GPIO used in Or1ksim is the component implemented at OpenCores, and
1966 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
1967 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
1968 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
1969 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
1970
 
1971 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
1972
appear multiple times, specifying multiple GPIO devices.  The following
1973 19 jeremybenn
parameters may be specified.
1974
 
1975
`enabled = 0|1'
1976 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
1977 19 jeremybenn
     disabled.
1978
 
1979
`baseaddr = VALUE'
1980
     Set the base address of the GPIO's memory mapped registers to
1981 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1982 19 jeremybenn
 
1983
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
1984
     registers, although the number of bits that are actively used
1985 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
1986 19 jeremybenn
 
1987
`irq = VALUE'
1988 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
1989 19 jeremybenn
 
1990
`vapi_id = VALUE'
1991
     VALUE specifies the value of the Verification API (VAPI) base
1992 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
1993 19 jeremybenn
     Verification API, for more details, which details the use of the
1994 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
1995 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
1996
     but deprecated.
1997
 
1998
 
1999

2000
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
2001
 
2002
3.4.6 Display Interface Configuration
2003
-------------------------------------
2004
 
2005
Or1ksim models a VGA interface to an external monitor.  The VGA
2006
controller used in Or1ksim is the component implemented at OpenCores,
2007 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
2008 82 jeremybenn
for the optional hardware cursors.  It is described in the document
2009 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
2010 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2011
which resides on the main OpenRISC Wishbone data bus.
2012 19 jeremybenn
 
2013
The current implementation provides only functionality to dump the
2014
screen to a file at intervals.
2015
 
2016 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
2017 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
2018
The following parameters may be specified.
2019
 
2020
`enabled = 0|1'
2021 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
2022 19 jeremybenn
     disabled.
2023
 
2024
`baseaddr = VALUE'
2025
     Set the base address of the VGA controller's memory mapped
2026 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2027 19 jeremybenn
     sensible value.
2028
 
2029
     The VGA controller has a 12-bit address bus, with 7 32-bit
2030
     registers, at addresses 0x000 through 0x018, and two color lookup
2031 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2032 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2033
     are not used.
2034
 
2035
`irq = VALUE'
2036 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2037 19 jeremybenn
     0.
2038
 
2039
`refresh_rate = VALUE'
2040 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2041 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2042
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2043
     50 times per simulated second.
2044
 
2045
`txfile = "FILE"'
2046
     FILE specifies the base of the filename for screen dumps.
2047
     Successive screen dumps will be in BMP format, in files with the
2048
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2049 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2050 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2051
     supported for this parameter, but deprecated.
2052
 
2053
 
2054

2055
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2056
 
2057
3.4.7 Frame Buffer Configuration
2058
--------------------------------
2059
 
2060 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2061 19 jeremybenn
     configuration fields are described here, but the component should
2062 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2063 19 jeremybenn
     to make screen dumps to file.
2064
 
2065 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2066
may appear multiple times, specifying multiple frame buffers.  The
2067 19 jeremybenn
following parameters may be specified.
2068
 
2069
`enabled = 0|1'
2070 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2071 19 jeremybenn
     is disabled.
2072
 
2073
`baseaddr = VALUE'
2074
     Set the base address of the frame buffer's memory mapped registers
2075 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2076
     value.
2077 19 jeremybenn
 
2078
     The frame buffer has an 121-bit address bus, with 4 32-bit
2079
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2080 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2081 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2082
 
2083
`refresh_rate = VALUE'
2084 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2085 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2086
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2087
     50 times per simulated second.
2088
 
2089
`txfile = "FILE"'
2090
     FILE specifies the base of the filename for screen dumps.
2091
     Successive screen dumps will be in BMP format, in files with the
2092
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2093 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2094 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2095
     supported for this parameter, but deprecated.
2096
 
2097
 
2098

2099
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2100
 
2101
3.4.8 Keyboard Configuration (PS2)
2102
----------------------------------
2103
 
2104 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2105 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2106 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2107
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2108 19 jeremybenn
standard, this is presumably what is expected with this device.
2109
 
2110
The implementation only provides for keyboard support, which is
2111 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2112 19 jeremybenn
 
2113
     Caution: A standard i8042 device has two registers at addresses
2114 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2115
     suggests that the Or1ksim component places these registers at
2116
     addresses 0x00 and 0x04.
2117 19 jeremybenn
 
2118
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2119
     implements the i8042 device driver, anticipating these registers
2120 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2121 19 jeremybenn
     code will work.
2122
 
2123
     This component should be used with caution.
2124
 
2125 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2126
appear multiple times, specifying multiple keyboard interfaces.  The
2127 19 jeremybenn
following parameters may be specified.
2128
 
2129
`enabled = 0|1'
2130 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2131 19 jeremybenn
     disabled.
2132
 
2133
`baseaddr = VALUE'
2134
     Set the base address of the keyboard's memory mapped registers to
2135 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2136 19 jeremybenn
 
2137
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2138
     registers, at addresses 0x000 and 0x004.
2139
 
2140
          Caution: As noted above, a standard Intel 8042 interface
2141
          would expect to find these registers at locations 0x60 and
2142
          0x64, thus requiring at least a 7-bit bus.
2143
 
2144
`irq = VALUE'
2145 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2146 19 jeremybenn
     value 0.
2147
 
2148
`rxfile = "FILE"'
2149
     `file' specifies a file containing raw key stroke data, which
2150 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2151 19 jeremybenn
     `"kbd_in"'.
2152
 
2153
 
2154

2155
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2156
 
2157
3.4.9 Disc Interface Configuration
2158
----------------------------------
2159
 
2160
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2161
IDE Controller) component implemented at OpenCores, and found in the
2162 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2163 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2164 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2165
which resides on the main OpenRISC Wishbone data bus.
2166 19 jeremybenn
 
2167 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2168
may appear multiple times, specifying multiple disc controllers.  The
2169 19 jeremybenn
following parameters may be specified.
2170
 
2171
`enabled = 0|1'
2172 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2173 19 jeremybenn
     0, it is disabled.
2174
 
2175
`baseaddr = VALUE'
2176
     Set the base address of the ATA/ATAPI interface's memory mapped
2177 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2178 19 jeremybenn
     sensible value.
2179
 
2180
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2181 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2182
     ATA/ATAPI interface selected (see `dev_id' below), not all
2183
     registers will be available.
2184 19 jeremybenn
 
2185
`irq = VALUE'
2186 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2187 19 jeremybenn
     value 0.
2188
 
2189
`dev_id = 1|2|3'
2190
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2191 82 jeremybenn
     interface to model.  The default value is 1.
2192 19 jeremybenn
 
2193
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2194
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2195
     registers and the `RXD'/`TXD' registers.
2196
 
2197
`rev = VALUE'
2198
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2199 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2200
     be in the range 0-15.  Larger values are truncated with a warning.
2201 19 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2202
     forms bits 24-27.
2203
 
2204
`pio_mode0_t1 = VALUE'
2205
`pio_mode0_t2 = VALUE'
2206
`pio_mode0_t4 = VALUE'
2207
`pio_mode0_teoc = VALUE'
2208
     These parameters specify the timings for use with Programmed
2209 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2210 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2211 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2212 19 jeremybenn
     they do, they will be ignored with a warning.
2213
 
2214
     See the ATA/ATAPI-5 specification for explanations of each of these
2215 82 jeremybenn
     timing parameters.  The default values are:
2216 19 jeremybenn
 
2217
          pio_mode0_t1   =  6
2218
          pio_mode0_t2   = 28
2219
          pio_mode0_t4   =  2
2220
          pio_mode0_teoc = 23
2221
 
2222
`dma_mode0_tm = VALUE'
2223
`dma_mode0_td = VALUE'
2224
`dma_mode0_teoc = VALUE'
2225
     These parameters specify the timings for use with DMA transfers.
2226
     They are specified as the number of clock cycles - 2, rounded up
2227
     to the next highest integer, or zero if that would be negative.
2228 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2229
     ignored with a warning.
2230 19 jeremybenn
 
2231
     See the ATA/ATAPI-5 specification for explanations of each of these
2232 82 jeremybenn
     timing parameters.  The default values are:
2233 19 jeremybenn
 
2234
          dma_mode0_tm   =  4
2235
          dma_mode0_td   = 21
2236
          dma_mode0_teoc = 21
2237
 
2238
 
2239
3.4.9.1 ATA/ATAPI Device Configuration
2240
......................................
2241
 
2242 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2243 19 jeremybenn
device subsection is introduced by
2244
 
2245
     device VALUE
2246
 
2247 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2248
ends with `enddevice'.  Note that if the same device number is
2249
specified more than once, the previous values will be overwritten.
2250
Within the `device' subsection, the following parameters may appear:
2251 19 jeremybenn
 
2252
`type = VALUE'
2253
     VALUEspecifies the type of device: 0 (the default) for "not
2254
     connected", 1 for hard disk simulated in a file and 2 for local
2255
     system hard disk.
2256
 
2257
`file = "FILENAME"'
2258
     `filename' specifies the file to be used for a simulated ATA
2259 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2260 19 jeremybenn
     `"ata-FileN"', where N is the device number.
2261
 
2262
`size = VALUE'
2263
     VALUE specifies the size of a simulated ATA device if the file
2264 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2265 19 jeremybenn
 
2266
`packet = 0|1'
2267 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2268 19 jeremybenn
     default), do not implement the PACKET command feature set.
2269
 
2270
`firmware = "STR"'
2271
     Firmware to report in response to the "Identify Device" command.
2272
     Default `"02207031"'.
2273
 
2274
`heads = VALUE'
2275 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2276 19 jeremybenn
     heads.
2277
 
2278
`sectors = VALUE'
2279 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2280 19 jeremybenn
 
2281
`mwdma = 0|1|2|-1'
2282 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2283 19 jeremybenn
     disable.
2284
 
2285
`pio = 0|1|2|3|4'
2286 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2287 19 jeremybenn
 
2288
 
2289

2290
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2291
 
2292
3.4.10 Generic Peripheral Configuration
2293
---------------------------------------
2294
 
2295
When used as a library (*note Simulator Library: Simulator Library.),
2296
Or1ksim makes provision for any additional peripheral to be implemented
2297 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2298
generates "upcall"s to an external handler.  This interface can support
2299 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2300
for OSCI SystemC (see `http://www.systemc.org').
2301
 
2302
Generic peripheral configuration is described in `section generic'.
2303
This section may appear multiple times, specifying multiple external
2304 82 jeremybenn
peripherals.  The following parameters may be specified.
2305 19 jeremybenn
 
2306
`enabled = 0|1'
2307 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2308 19 jeremybenn
     0, it is disabled.
2309
 
2310
`baseaddr = VALUE'
2311
     Set the base address of the generic peripheral's memory mapped
2312 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2313 19 jeremybenn
     sensible value.
2314
 
2315
     The size of the memory mapped register space is controlled by the
2316
     `size' paramter, described below.
2317
 
2318
`size = VALUE'
2319
     Set the size of the generic peripheral's memory mapped register
2320 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2321 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2322
     parameter `baseaddr' (see above) will be directed to the external
2323
     interface.
2324
 
2325 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2326
     value is zero.  If VALUE is not an exact power of two, accesses to
2327 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2328
     generate a warning, and have no effect (reads will return zero).
2329
 
2330
`name = "STR"'
2331 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2332 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2333 82 jeremybenn
     reporting its status.  The default value is
2334 19 jeremybenn
     `"anonymous external peripheral"'.
2335
 
2336
`byte_enabled = 0|1'
2337
`hw_enabled = 0|1'
2338
`word_enabled = 0|1'
2339
     If 1 (true, the default), these parameters respectively enable the
2340 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2341 19 jeremybenn
     accesses of that width will fail.
2342
 
2343
 
2344

2345
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2346
 
2347
4 Interactive Command Line
2348
**************************
2349
 
2350
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2351 82 jeremybenn
provides the user with an interactive command line.  The commands
2352 19 jeremybenn
available, which may not be abbreviated, are:
2353
 
2354
`q'
2355
     Exit the simulator
2356
 
2357
`r'
2358 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2359 19 jeremybenn
     just executed and next to be executed instructions symbolically
2360
     and the state of the flag in the Supervision Register.
2361
 
2362
`t'
2363
     Execute the next instruction and then display register/instruction
2364
     information as with the `r' command (see above).
2365
 
2366
`run NUM [ hush ]'
2367 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2368 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2369
     above) _unless_ `hush' is specified.
2370
 
2371
`pr REG VALUE'
2372
     Patch register REG with VALUE.
2373
 
2374
`dm FROMADDR [ TOADDR ]'
2375 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2376
     not given, 64 bytes are displayed, starting at FROMADDR.
2377 19 jeremybenn
 
2378
          Caution: The output from this command is broken (a bug).
2379 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2380 19 jeremybenn
          instead of printing out the address at the start of each row,
2381
          it prints the address (of the first of the 16 bytes) before
2382
          _each_ byte.
2383
 
2384
`de FROMADDR [ TOADDR ]'
2385 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2386 19 jeremybenn
     given, 16 instructions are disassembled.
2387
 
2388
     The disassembly is entirely numerical, and gives no symbolic
2389
     information.
2390
 
2391
`pm ADDR VALUE'
2392
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2393
 
2394
`pc VALUE'
2395
     Patch the program counter with VALUE.
2396
 
2397
`cm FROMADDR TOADDR SIZE'
2398
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2399
 
2400
`break ADDR'
2401
     Toggle the breakpoint set at ADDR.
2402
 
2403
`breaks'
2404
     List all set breakpoints
2405
 
2406
`reset'
2407 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2408
     so execution will restart from the reset vector location, 0x100.
2409 19 jeremybenn
 
2410
`hist'
2411
     If saving the execution history has been configured (*note
2412
     Simulator Behavior: Simulator Behavior.), display the execution
2413
     history.
2414
 
2415
`stall'
2416
     Stall the processor, so that control is passed to the debug unit.
2417 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2418 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2419
     debuggers such as GDB.
2420
 
2421
`unstall'
2422 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2423
     This command is useful when debugging the JTAG interface, used by
2424 19 jeremybenn
     debuggers such as GDB.
2425
 
2426
`stats CATEGORY | clear'
2427
     Print the statistics for the given CATEGORY, if available, or
2428 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2429 19 jeremybenn
 
2430
    1
2431
          Miscellaneous statistics: branch predictions (if branch
2432
          predictions are enabled), branch target cache model (if
2433
          enabled), cache (if enbaled), MMU (if enabled) and number of
2434
          addtional load & store cycles.
2435
 
2436
          *Note Configuring the OpenRisc Achitectural Components: Core
2437
          OpenRISC Configuration, for details of how to enable these
2438
          various features.
2439
 
2440
    2
2441 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2442 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2443
 
2444
    3
2445 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2446 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2447
 
2448
    4
2449 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2450 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2451
          Configuration.).
2452
 
2453
    5
2454 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2455 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2456
 
2457
    6
2458 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2459 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2460
 
2461
 
2462
`info'
2463
     Display detailed information about the simulator configuration.
2464
     This is quite a lengthy about, because all MMU TLB information is
2465
     displayed.
2466
 
2467
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2468
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2469 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2470 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2471 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2472 19 jeremybenn
 
2473
     To save to a file, use the redirection function (described after
2474
     this table, below).
2475
 
2476
`dh FROMADDR [ TOADDR ]'
2477
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2478 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2479 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2480
 
2481
     To save to a file, use the redirection function (described after
2482
     this table, below).
2483
 
2484
`setdbch'
2485 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2486 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2487
     channels on the command line.
2488
 
2489
`set SECTION PARAM = VALUE'
2490
     Set the configuration parameter PARA in section SECTION to VALUE.
2491
     *Note Configuration: Configuration, for details of configuration
2492
     parameters and their settings.
2493
 
2494
`debug'
2495 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2496 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2497
     this parameter.
2498
 
2499
          Caution: This is effectively enabling or disabling the debug
2500 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2501 19 jeremybenn
          However using the remote debug interface while the debug unit
2502
          is disabled will lead to undefined behavior and likely crash
2503
          Or1ksim
2504
 
2505
`cuc'
2506
     Enter the the Custom Unit Compiler command prompt (*note CUC
2507
     Configuration: CUC Configuration.).
2508
 
2509
          Caution: The CUC must be properly configured, for this to
2510 82 jeremybenn
          succeed.  In particular a timing file must be available and
2511
          readable.  Otherwise Or1ksim will crash.
2512 19 jeremybenn
 
2513
`help'
2514
     Print out brief information about each command available.
2515
 
2516
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2517 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2518 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2519
     Profiling Utility.).
2520
 
2521
`profile [-vhcq] [-g FILE]'
2522 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2523
     usage as the standalone command (*note Profiling Utility:
2524
     Profiling Utility.).
2525 19 jeremybenn
 
2526
 
2527
For all commands, it is possible to redirect the output to a file, by
2528
using the redirection operator, `>'.
2529
 
2530
     COMMAND > FILENAME
2531
 
2532
This is particularly useful for commands dumping a large amount of
2533
output, such as `dv'.
2534
 
2535
     Caution: Unfortunately there is a serious bug with the redirection
2536 82 jeremybenn
     operator.  It does not return output to standard output after the
2537
     command completes.  Until this bug is fixed, file redirection
2538 19 jeremybenn
     should not be used.
2539
 
2540

2541
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2542
 
2543
5 Verification API (VAPI)
2544
*************************
2545
 
2546
The Verification API (VAPI) provides a TCP/IP interface to allow
2547 82 jeremybenn
components of the simulation to be controlled externally.  The
2548
interface is polled for new requests on each simulated clock cycle.
2549
Components within the simulator may send responses to such requests.
2550 19 jeremybenn
 
2551 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2552
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2553
with a single piece of data (also a 32 bit integer).  On the send side,
2554
it provides for sending a single VAPI ID and data.  However there is no
2555
explicit command-response structure.  Some components just accept
2556
requests (e.g.  to set values), some just generate sends (to report
2557 19 jeremybenn
values), and some do both.
2558
 
2559
Each component has a base ID (32 bit) and its commands will start from
2560 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2561
amongst components.  Request commands will be directed to the component
2562 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2563
 
2564
Thus if there are two components with base IDs of 0x200 and 0x300, and
2565
a request with VAPI ID of 0x203 is received, it will be directed to the
2566
first component as its command #3.
2567
 
2568
The results of VAPI interactions are logged (by default in `vapi.log'
2569
unless an alternative is specified in `section vapi').
2570
 
2571
Currently the following components support VAPI:
2572
 
2573
Debug Unit
2574
     Although the Debug Unit can specify a base VAPI ID, it is not used
2575
     to send commands or receive requests.
2576
 
2577
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2578
     exchanges are logged in the VAPI log file.
2579
 
2580
UART
2581
     If a base VAPI ID is specified, the UART sends details of any
2582
     chars or break characters sent, with dteails of the line control
2583
     register etc encoded in the data packet sent.
2584
 
2585
     This supports a single VAPI command request, but encodes a
2586
     sub-command in the top 8 bits of the associated data.
2587
 
2588
    `0x00'
2589
          This stuffs the least significant 8 bits of the data into the
2590
          serial register of the UART and the next 8 bits into the line
2591
          control register, effectively providing control of the next
2592
          character to be sent or received.
2593
 
2594
    `0x01'
2595
          The divisor latch bytes are set from the least significant 16
2596
          bits of the data.
2597
 
2598
    `0x02'
2599
          The line control register is set from bits 15-8 of the data.
2600
 
2601
    `0x03'
2602
          The UART skew is set from the least significant 16 bits of
2603
          the data
2604
 
2605
    `0x04'
2606
          If the 16th most significant bit of the data is 1, start
2607 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
2608
          are sent or cleared after the number of UART clock divider
2609
          ticks specified by the data (immediately if the data is zero).
2610 19 jeremybenn
 
2611
 
2612
DMA
2613
     Although the DMA unit supports a base VAPI ID in its configuration
2614
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
2615
     implemented.
2616
 
2617
Ethernet
2618 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
2619 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
2620 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
2621 19 jeremybenn
     VAPI requests.
2622
 
2623
    `ETH_VAPI_DATA (0)'
2624
 
2625
    `ETH_VAPI_CTRL (0)'
2626
 
2627
GPIO
2628
     If a base VAPI ID is specified, the GPIO sends out on its base
2629
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
2630
     VAPI ID) any changes in outputs.
2631
 
2632 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
2633 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
2634
     GPIO.
2635
 
2636
    `GPIO_VAPI_DATA (0)'
2637
          Set the next input to the commands data field
2638
 
2639
    `GPIO_VAPI_AUX (1)'
2640
          Set the GPIO auxiliary inputs to the data field
2641
 
2642
    `GPIO_VAPI_CLOCK (2)'
2643
          Add an external GPIO clock trigger of period specified in the
2644
          data field.
2645
 
2646
    `GPIO_VAPI_RGPIO_OE (3)'
2647
          Set the GPIO output enable to the data field
2648
 
2649
    `GPIO_VAPI_RGPIO_INTE (4)'
2650
          Set the next interrupt to the data field
2651
 
2652
    `GPIO_VAPI_RGPIO_PTRIG (5)'
2653
          Set the next trigger to the data field
2654
 
2655
    `GPIO_VAPI_RGPIO_AUX (6)'
2656
          Set the next auxiliary input to the data field
2657
 
2658
    `GPIO_VAPI_RGPIO_CTRL (7)'
2659
          Set th next control input to the data field
2660
 
2661
 
2662
 
2663

2664
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
2665
 
2666
6 A Guide to Or1ksim Internals
2667
******************************
2668
 
2669 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
2670 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
2671 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
2672
Linux manual page for `etags'.  A tag file can be created with:
2673 19 jeremybenn
 
2674
     make tags
2675
 
2676
* Menu:
2677
 
2678
* Coding Conventions::
2679
* Global Data Structures::
2680
* Concepts::
2681
* Internal Debugging::
2682 104 jeremybenn
* Regression Testing::
2683 19 jeremybenn
 
2684

2685
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
2686
 
2687
6.1 Coding Conventions for Or1ksim
2688
==================================
2689
 
2690
This chapter provides some guidelines for coding, to facilitate
2691
extensions to Or1ksim
2692
 
2693
_GNU Coding Standard_
2694
     Code should follow the GNU coding standard for C
2695 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
2696 19 jeremybenn
     through the `indent' program.
2697
 
2698
_`#include' headers_
2699
     All C source code files should include `config.h' before any other
2700
     file.
2701
 
2702
     This should be followed by inclusion of any system headers (but see
2703
     the comments about portability and `port.h' below) and then by any
2704
     Or1ksim package headers.
2705
 
2706
     If `port.h' is required, it should be the first package header to
2707
     be included after the system headers.
2708
 
2709
     All C source code and header files should directly include any
2710 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
2711
     other header having already included it.  The two exceptions are
2712 19 jeremybenn
 
2713
       1. All header files may assume that `config.h' has already been
2714
          included.
2715
 
2716
       2. System headers which impose portability problems should be
2717
          included by using the package header `port.h', rather than
2718 82 jeremybenn
          the system headers themselves.  This is the case for code
2719 19 jeremybenn
          requiring
2720
 
2721
             * `strndup' (from `string.h')
2722
 
2723
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
2724
 
2725
             * `isblank' (from `ctype.h')
2726
 
2727
 
2728
 
2729
_`#include' files once only_
2730
     All include files should be protected by `#ifndef' to ensure their
2731 82 jeremybenn
     definitions are only included once.  For instance a header file
2732 19 jeremybenn
     `X-Y.H' should surround its contents with:
2733
 
2734
          #ifndef X_Y__H
2735
          #define X_Y__H
2736
 
2737
          
2738
 
2739
          #endif  /* X_Y__H */
2740
 
2741
_Avoid `typedef'_
2742
     The GNU coding style for C does not have a clear way to distinguish
2743 82 jeremybenn
     between user type name and user variables.  For this reason
2744 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
2745 82 jeremybenn
     defined types.  This makes the code much easier to read.
2746 19 jeremybenn
 
2747
     There are some `typedef' declarations in the `argtable2' library
2748
     and the ELF and COFF headers, because this code is taken from
2749
     other places.
2750
 
2751
     Within Or1ksim legacy uses of `typedef' have largely been purged,
2752
     except in the Custom Unit Compiler (*note Custom Unit Compiler
2753
     (CUC) Configuration: CUC Configuration.).
2754
 
2755
     The remaining uses of `typedef' occur in two places:
2756
 
2757
        * `port/port.h' defines types to replace those in header files
2758
          that are not available (character functions, string
2759
          duplication, integer types).
2760
 
2761
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
2762
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
2763
          and signed register (`orreg_t') values.
2764
 
2765
 
2766
     Where new types are defined, they should appear in one of these two
2767 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
2768
     `arch.h' should always have the suffix `_h'.
2769 19 jeremybenn
 
2770
_Don't begin names with underscore_
2771
     Names beginning with `_' are intended to be part of the C
2772 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
2773 19 jeremybenn
 
2774
_Keep Non-global top level entities static_
2775
     All top level entities (functions, variables), which are not
2776
     explicitly part of a global interface should be declared static.
2777
     This ensures that unwanted connections are not inadvertently built
2778
     across the program.
2779
 
2780
_Use of `inline'_
2781 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
2782 19 jeremybenn
     out for themselves what is best in this respect.
2783
 
2784
_Initialization_
2785 82 jeremybenn
     All data structures should be explicitly initialized.  In
2786
     particular code should not rely on static data structures being
2787
     initialized to zero.
2788 19 jeremybenn
 
2789
     The rationale is that in future static data structures may become
2790 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
2791 19 jeremybenn
     historically.
2792
 
2793
     A specific case is with new peripherals, which should always
2794
     include a `start' function to pre-initialize all configuration
2795
     parameters to sensible defaults
2796
 
2797
_Configuration Validation_
2798
     All configuration values should be validated, preferably when
2799
     encountered, if not when the `section' is closed, or otherwise at
2800
     run time when the parameter is first used.
2801
 
2802
 
2803

2804
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
2805
 
2806
6.2 Global Data Structures
2807
==========================
2808
 
2809
`config'
2810
     The global variable `config' of type `struct config' holds the
2811
     configuration data for some of the Or1ksim components which are
2812 82 jeremybenn
     always present.  At present the components are:
2813 19 jeremybenn
 
2814
        * The simulator defined in `section sim' (*note Simulator
2815
          Configuration: Simulator Configuration.).
2816
 
2817
        * The Verification API (VAPI) defined  in `section vapi' (*note
2818
          Verification API (VAPI) Configuration: Verification API
2819
          Configuration.).
2820
 
2821
        * The Custom Unit Compiler (CUC), defined in `section cuc'
2822
          (*note Custom Unit Compiler (CUC) Configuration: CUC
2823
          Configuration.).
2824
 
2825
        * The CPU, defined in `section cpu' (*note CPU Configuration:
2826
          CPU Configuration.).
2827
 
2828
        * The data cache (but not the instruction cache), defined in
2829
          `section dc' (*note Cache Configuration: Cache
2830
          Configuration.).
2831
 
2832
        * The power management unit, defined in `section pm' (*note
2833
          Power Management Configuration: Power Management
2834
          Configuration.).
2835
 
2836
        * The programmable interrupt controller, defined in
2837
          `section pic' (*note Interrupt Configuration: Interrupt
2838
          Configuration.).
2839
 
2840
        * Branch prediciton, defined in `section bpb' (*note Branch
2841
          Prediction Configuration: Branch Prediction Configuration.).
2842
 
2843
        * The debug unit, defined in `section debug' (*note Debug
2844
          Interface Configuration: Debug Interface Configuration.).
2845
 
2846
 
2847
     This struct is made of a collection of structs, one for each
2848 82 jeremybenn
     component.  For example the simulator configuration is held in
2849 19 jeremybenn
     `config.sim'.
2850
 
2851
`config'
2852
     This is a linked list of data structures holding configuration data
2853
     for all sections which are not held in the main `config' data
2854 82 jeremybenn
     structure.  In general these are components (such as peripherals
2855
     and memory) which may occur multiple times.  However it also
2856
     handles some architectural components which may occur only once,
2857
     such as the memory management units, the instruction cache, the
2858
     interrupt controller and branch prediction.
2859 19 jeremybenn
 
2860
`runtime'
2861
     The global variable `runtime' of type `struct runtime' holds all
2862 82 jeremybenn
     the runtime information about the simulation.  To access this
2863 19 jeremybenn
     variable, `sim-config.h' must be included.
2864
 
2865
     This struct is itself made of 3 other structs, `cpu' (for CPU run
2866
     time state), `vapi' (for Verification API state) and `cuc' (for
2867
     Custom Unit Compiler state).
2868
 
2869
 
2870

2871
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
2872
 
2873
6.3 Concepts
2874
============
2875
 
2876
_Output Redirection_
2877 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
2878 19 jeremybenn
     should be explicitly written to this stream, or may use the
2879
     `PRINTF' macro, which will write its arguments to this output
2880
     stream.
2881
 
2882
_Reset Hooks_
2883
     Any peripheral may register a routine to be called when the the
2884
     processor is reset by calling `reg_sim_reset', providing a
2885 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
2886 19 jeremybenn
     that function will be called with the data stucture pointer as
2887
     argument.
2888
 
2889
 
2890

2891 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
2892 19 jeremybenn
 
2893
6.4 Internal Debugging
2894
======================
2895
 
2896
The function `debug' is like `printf', but with an extra first
2897 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
2898
the simulator configuration (*note Simulator Behavior: Simulator
2899
Behavior.) is greater than or equal to this value, the remaining
2900
arguments are printed to the current output stream (*note Output
2901
Redirection: Output Redirection.).
2902 19 jeremybenn
 
2903

2904 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
2905
 
2906
6.5 Regression Testing
2907
======================
2908
 
2909
Or1ksim now includes a regression test suite for both standalone and
2910
library usage as described earlier (*note Building and Installing:
2911
Build and Install.).  Running the tests requires that the OpenRISC
2912
toolchain and DejaGNU are both installed.
2913
 
2914
Tests are written using `expect', a derivative of TCL.  Documentation
2915
of DejaGnu, `expect' and TCL are freely available on the Web.  The
2916
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
2917
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
2918
provides a concise introduction.
2919
 
2920
All test code is found in the `testsuite' directory.  The key files and
2921
directories used are as follows.
2922
 
2923
`global-conf.exp'
2924
     This is the global DejaGNU configuration file used to set up
2925
     parameters common to all tests.  If the user has the environment
2926
     varialbe `DEJAGNU' defined, it will be used instead, but this is
2927
     not recommended.
2928
 
2929
`Makefile.am'
2930
     This is the top level `automake' file for the testsuite.  The only
2931
     changes likely to be needed here is additional local cleanup of
2932
     files created by new tests.
2933
 
2934
`README'
2935
     This contains details of all the tests
2936
 
2937
`config'
2938
     This contains DejaGnu board configurations.  Since the tests are
2939
     generally run on a Unix host, this should just contain `Unix.exp'.
2940
 
2941
`lib'
2942
     This contains DejaGnu tool specific configurations.  "Tool" has a
2943
     specific meaning in DejaGNU, referring just to a grouping of
2944
     tests.  In this case there are two such "tools", "or1ksim" and
2945
     "libsim" for tests of the standalone tool and tests of the library.
2946
 
2947
     Corresponding to this, there are two tool specific configuration
2948
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
2949
     procedures for common use among the tests.
2950
 
2951
`libsim.tests'
2952
`or1ksim.tests'
2953
     These are the directories of tests of the Or1ksim library.  They
2954
     also include Or1ksim configuration files and each has a
2955
     `Makefile.am' file.  `Makefile.am' should be updated whenever
2956
     files are added to this directory, to ensure they are included in
2957
     the distribution.
2958
 
2959
`test-code'
2960
     These are all the test programs to be compiled on the host (each
2961
     in its own directory).  In general these are programs to support
2962
     testing of the library, and build various programs linking in the
2963
     library.
2964
 
2965
`test-code'
2966
     These are all the test programs to be compiled with the OpenRISC
2967
     tool chain to run with either standalone Or1ksim or the library.
2968
     This directory includes its own `configure.ac', since it must set
2969
     up a separate tool chain based on the target, not the host.
2970
 
2971
 
2972
To add a new test needs the following steps.
2973
 
2974
   * Put new host C code in its own directory within `test-code'. Add
2975
     the directory to the existing `Makefile.am' in the `test-code'
2976
     directory and create a `Makefile.am' in the new directory to drive
2977
     building the test program(s). Don't forget to add the new
2978
     `Makefile' to the top level `configure.ac' so it gets generated.
2979
     Not all tests require code here.
2980
 
2981
   * Put new target C code in its own directory within
2982
     `test-code-or1k'. Once again modify & create `Makefile.am'. this
2983
     time though modify the `configure.ac' in the `test-code-or1k' so
2984
     the `Makefile' gets generated. The existing programs provide
2985
     examples to start from, including custom linker scripts where
2986
     needed.
2987
 
2988
   * Add one or more tests and configuration files to the relevant
2989
     "tool" test directory. Use the existing tests as templates. They
2990
     make heavy use of the `expect'/TCL procedures in the `config'
2991
     directory to facilitate driving the tests.
2992
 
2993
 
2994

2995 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
2996
 
2997
7 GNU Free Documentation License
2998
********************************
2999
 
3000
                      Version 1.2, November 2002
3001
 
3002
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
3003
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
3004
 
3005
     Everyone is permitted to copy and distribute verbatim copies
3006
     of this license document, but changing it is not allowed.
3007
 
3008
  0. PREAMBLE
3009
 
3010
     The purpose of this License is to make a manual, textbook, or other
3011
     functional and useful document "free" in the sense of freedom: to
3012
     assure everyone the effective freedom to copy and redistribute it,
3013
     with or without modifying it, either commercially or
3014
     noncommercially.  Secondarily, this License preserves for the
3015
     author and publisher a way to get credit for their work, while not
3016
     being considered responsible for modifications made by others.
3017
 
3018
     This License is a kind of "copyleft", which means that derivative
3019
     works of the document must themselves be free in the same sense.
3020
     It complements the GNU General Public License, which is a copyleft
3021
     license designed for free software.
3022
 
3023
     We have designed this License in order to use it for manuals for
3024
     free software, because free software needs free documentation: a
3025
     free program should come with manuals providing the same freedoms
3026
     that the software does.  But this License is not limited to
3027
     software manuals; it can be used for any textual work, regardless
3028
     of subject matter or whether it is published as a printed book.
3029
     We recommend this License principally for works whose purpose is
3030
     instruction or reference.
3031
 
3032
  1. APPLICABILITY AND DEFINITIONS
3033
 
3034
     This License applies to any manual or other work, in any medium,
3035
     that contains a notice placed by the copyright holder saying it
3036
     can be distributed under the terms of this License.  Such a notice
3037
     grants a world-wide, royalty-free license, unlimited in duration,
3038
     to use that work under the conditions stated herein.  The
3039
     "Document", below, refers to any such manual or work.  Any member
3040
     of the public is a licensee, and is addressed as "you".  You
3041
     accept the license if you copy, modify or distribute the work in a
3042
     way requiring permission under copyright law.
3043
 
3044
     A "Modified Version" of the Document means any work containing the
3045
     Document or a portion of it, either copied verbatim, or with
3046
     modifications and/or translated into another language.
3047
 
3048
     A "Secondary Section" is a named appendix or a front-matter section
3049
     of the Document that deals exclusively with the relationship of the
3050
     publishers or authors of the Document to the Document's overall
3051
     subject (or to related matters) and contains nothing that could
3052
     fall directly within that overall subject.  (Thus, if the Document
3053
     is in part a textbook of mathematics, a Secondary Section may not
3054
     explain any mathematics.)  The relationship could be a matter of
3055
     historical connection with the subject or with related matters, or
3056
     of legal, commercial, philosophical, ethical or political position
3057
     regarding them.
3058
 
3059
     The "Invariant Sections" are certain Secondary Sections whose
3060
     titles are designated, as being those of Invariant Sections, in
3061
     the notice that says that the Document is released under this
3062
     License.  If a section does not fit the above definition of
3063
     Secondary then it is not allowed to be designated as Invariant.
3064
     The Document may contain zero Invariant Sections.  If the Document
3065
     does not identify any Invariant Sections then there are none.
3066
 
3067
     The "Cover Texts" are certain short passages of text that are
3068
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3069
     that says that the Document is released under this License.  A
3070
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3071
     be at most 25 words.
3072
 
3073
     A "Transparent" copy of the Document means a machine-readable copy,
3074
     represented in a format whose specification is available to the
3075
     general public, that is suitable for revising the document
3076
     straightforwardly with generic text editors or (for images
3077
     composed of pixels) generic paint programs or (for drawings) some
3078
     widely available drawing editor, and that is suitable for input to
3079
     text formatters or for automatic translation to a variety of
3080
     formats suitable for input to text formatters.  A copy made in an
3081
     otherwise Transparent file format whose markup, or absence of
3082
     markup, has been arranged to thwart or discourage subsequent
3083
     modification by readers is not Transparent.  An image format is
3084
     not Transparent if used for any substantial amount of text.  A
3085
     copy that is not "Transparent" is called "Opaque".
3086
 
3087
     Examples of suitable formats for Transparent copies include plain
3088
     ASCII without markup, Texinfo input format, LaTeX input format,
3089
     SGML or XML using a publicly available DTD, and
3090
     standard-conforming simple HTML, PostScript or PDF designed for
3091
     human modification.  Examples of transparent image formats include
3092
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3093
     can be read and edited only by proprietary word processors, SGML or
3094
     XML for which the DTD and/or processing tools are not generally
3095
     available, and the machine-generated HTML, PostScript or PDF
3096
     produced by some word processors for output purposes only.
3097
 
3098
     The "Title Page" means, for a printed book, the title page itself,
3099
     plus such following pages as are needed to hold, legibly, the
3100
     material this License requires to appear in the title page.  For
3101
     works in formats which do not have any title page as such, "Title
3102
     Page" means the text near the most prominent appearance of the
3103
     work's title, preceding the beginning of the body of the text.
3104
 
3105
     A section "Entitled XYZ" means a named subunit of the Document
3106
     whose title either is precisely XYZ or contains XYZ in parentheses
3107
     following text that translates XYZ in another language.  (Here XYZ
3108
     stands for a specific section name mentioned below, such as
3109
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3110
     To "Preserve the Title" of such a section when you modify the
3111
     Document means that it remains a section "Entitled XYZ" according
3112
     to this definition.
3113
 
3114
     The Document may include Warranty Disclaimers next to the notice
3115
     which states that this License applies to the Document.  These
3116
     Warranty Disclaimers are considered to be included by reference in
3117
     this License, but only as regards disclaiming warranties: any other
3118
     implication that these Warranty Disclaimers may have is void and
3119
     has no effect on the meaning of this License.
3120
 
3121
  2. VERBATIM COPYING
3122
 
3123
     You may copy and distribute the Document in any medium, either
3124
     commercially or noncommercially, provided that this License, the
3125
     copyright notices, and the license notice saying this License
3126
     applies to the Document are reproduced in all copies, and that you
3127
     add no other conditions whatsoever to those of this License.  You
3128
     may not use technical measures to obstruct or control the reading
3129
     or further copying of the copies you make or distribute.  However,
3130
     you may accept compensation in exchange for copies.  If you
3131
     distribute a large enough number of copies you must also follow
3132
     the conditions in section 3.
3133
 
3134
     You may also lend copies, under the same conditions stated above,
3135
     and you may publicly display copies.
3136
 
3137
  3. COPYING IN QUANTITY
3138
 
3139
     If you publish printed copies (or copies in media that commonly
3140
     have printed covers) of the Document, numbering more than 100, and
3141
     the Document's license notice requires Cover Texts, you must
3142
     enclose the copies in covers that carry, clearly and legibly, all
3143
     these Cover Texts: Front-Cover Texts on the front cover, and
3144
     Back-Cover Texts on the back cover.  Both covers must also clearly
3145
     and legibly identify you as the publisher of these copies.  The
3146
     front cover must present the full title with all words of the
3147
     title equally prominent and visible.  You may add other material
3148
     on the covers in addition.  Copying with changes limited to the
3149
     covers, as long as they preserve the title of the Document and
3150
     satisfy these conditions, can be treated as verbatim copying in
3151
     other respects.
3152
 
3153
     If the required texts for either cover are too voluminous to fit
3154
     legibly, you should put the first ones listed (as many as fit
3155
     reasonably) on the actual cover, and continue the rest onto
3156
     adjacent pages.
3157
 
3158
     If you publish or distribute Opaque copies of the Document
3159
     numbering more than 100, you must either include a
3160
     machine-readable Transparent copy along with each Opaque copy, or
3161
     state in or with each Opaque copy a computer-network location from
3162
     which the general network-using public has access to download
3163
     using public-standard network protocols a complete Transparent
3164
     copy of the Document, free of added material.  If you use the
3165
     latter option, you must take reasonably prudent steps, when you
3166
     begin distribution of Opaque copies in quantity, to ensure that
3167
     this Transparent copy will remain thus accessible at the stated
3168
     location until at least one year after the last time you
3169
     distribute an Opaque copy (directly or through your agents or
3170
     retailers) of that edition to the public.
3171
 
3172
     It is requested, but not required, that you contact the authors of
3173
     the Document well before redistributing any large number of
3174
     copies, to give them a chance to provide you with an updated
3175
     version of the Document.
3176
 
3177
  4. MODIFICATIONS
3178
 
3179
     You may copy and distribute a Modified Version of the Document
3180
     under the conditions of sections 2 and 3 above, provided that you
3181
     release the Modified Version under precisely this License, with
3182
     the Modified Version filling the role of the Document, thus
3183
     licensing distribution and modification of the Modified Version to
3184
     whoever possesses a copy of it.  In addition, you must do these
3185
     things in the Modified Version:
3186
 
3187
       A. Use in the Title Page (and on the covers, if any) a title
3188
          distinct from that of the Document, and from those of
3189
          previous versions (which should, if there were any, be listed
3190
          in the History section of the Document).  You may use the
3191
          same title as a previous version if the original publisher of
3192
          that version gives permission.
3193
 
3194
       B. List on the Title Page, as authors, one or more persons or
3195
          entities responsible for authorship of the modifications in
3196
          the Modified Version, together with at least five of the
3197
          principal authors of the Document (all of its principal
3198
          authors, if it has fewer than five), unless they release you
3199
          from this requirement.
3200
 
3201
       C. State on the Title page the name of the publisher of the
3202
          Modified Version, as the publisher.
3203
 
3204
       D. Preserve all the copyright notices of the Document.
3205
 
3206
       E. Add an appropriate copyright notice for your modifications
3207
          adjacent to the other copyright notices.
3208
 
3209
       F. Include, immediately after the copyright notices, a license
3210
          notice giving the public permission to use the Modified
3211
          Version under the terms of this License, in the form shown in
3212
          the Addendum below.
3213
 
3214
       G. Preserve in that license notice the full lists of Invariant
3215
          Sections and required Cover Texts given in the Document's
3216
          license notice.
3217
 
3218
       H. Include an unaltered copy of this License.
3219
 
3220
       I. Preserve the section Entitled "History", Preserve its Title,
3221
          and add to it an item stating at least the title, year, new
3222
          authors, and publisher of the Modified Version as given on
3223
          the Title Page.  If there is no section Entitled "History" in
3224
          the Document, create one stating the title, year, authors,
3225
          and publisher of the Document as given on its Title Page,
3226
          then add an item describing the Modified Version as stated in
3227
          the previous sentence.
3228
 
3229
       J. Preserve the network location, if any, given in the Document
3230
          for public access to a Transparent copy of the Document, and
3231
          likewise the network locations given in the Document for
3232
          previous versions it was based on.  These may be placed in
3233
          the "History" section.  You may omit a network location for a
3234
          work that was published at least four years before the
3235
          Document itself, or if the original publisher of the version
3236
          it refers to gives permission.
3237
 
3238
       K. For any section Entitled "Acknowledgements" or "Dedications",
3239
          Preserve the Title of the section, and preserve in the
3240
          section all the substance and tone of each of the contributor
3241
          acknowledgements and/or dedications given therein.
3242
 
3243
       L. Preserve all the Invariant Sections of the Document,
3244
          unaltered in their text and in their titles.  Section numbers
3245
          or the equivalent are not considered part of the section
3246
          titles.
3247
 
3248
       M. Delete any section Entitled "Endorsements".  Such a section
3249
          may not be included in the Modified Version.
3250
 
3251
       N. Do not retitle any existing section to be Entitled
3252
          "Endorsements" or to conflict in title with any Invariant
3253
          Section.
3254
 
3255
       O. Preserve any Warranty Disclaimers.
3256
 
3257
     If the Modified Version includes new front-matter sections or
3258
     appendices that qualify as Secondary Sections and contain no
3259
     material copied from the Document, you may at your option
3260
     designate some or all of these sections as invariant.  To do this,
3261
     add their titles to the list of Invariant Sections in the Modified
3262
     Version's license notice.  These titles must be distinct from any
3263
     other section titles.
3264
 
3265
     You may add a section Entitled "Endorsements", provided it contains
3266
     nothing but endorsements of your Modified Version by various
3267
     parties--for example, statements of peer review or that the text
3268
     has been approved by an organization as the authoritative
3269
     definition of a standard.
3270
 
3271
     You may add a passage of up to five words as a Front-Cover Text,
3272
     and a passage of up to 25 words as a Back-Cover Text, to the end
3273
     of the list of Cover Texts in the Modified Version.  Only one
3274
     passage of Front-Cover Text and one of Back-Cover Text may be
3275
     added by (or through arrangements made by) any one entity.  If the
3276
     Document already includes a cover text for the same cover,
3277
     previously added by you or by arrangement made by the same entity
3278
     you are acting on behalf of, you may not add another; but you may
3279
     replace the old one, on explicit permission from the previous
3280
     publisher that added the old one.
3281
 
3282
     The author(s) and publisher(s) of the Document do not by this
3283
     License give permission to use their names for publicity for or to
3284
     assert or imply endorsement of any Modified Version.
3285
 
3286
  5. COMBINING DOCUMENTS
3287
 
3288
     You may combine the Document with other documents released under
3289
     this License, under the terms defined in section 4 above for
3290
     modified versions, provided that you include in the combination
3291
     all of the Invariant Sections of all of the original documents,
3292
     unmodified, and list them all as Invariant Sections of your
3293
     combined work in its license notice, and that you preserve all
3294
     their Warranty Disclaimers.
3295
 
3296
     The combined work need only contain one copy of this License, and
3297
     multiple identical Invariant Sections may be replaced with a single
3298
     copy.  If there are multiple Invariant Sections with the same name
3299
     but different contents, make the title of each such section unique
3300
     by adding at the end of it, in parentheses, the name of the
3301
     original author or publisher of that section if known, or else a
3302
     unique number.  Make the same adjustment to the section titles in
3303
     the list of Invariant Sections in the license notice of the
3304
     combined work.
3305
 
3306
     In the combination, you must combine any sections Entitled
3307
     "History" in the various original documents, forming one section
3308
     Entitled "History"; likewise combine any sections Entitled
3309
     "Acknowledgements", and any sections Entitled "Dedications".  You
3310
     must delete all sections Entitled "Endorsements."
3311
 
3312
  6. COLLECTIONS OF DOCUMENTS
3313
 
3314
     You may make a collection consisting of the Document and other
3315
     documents released under this License, and replace the individual
3316
     copies of this License in the various documents with a single copy
3317
     that is included in the collection, provided that you follow the
3318
     rules of this License for verbatim copying of each of the
3319
     documents in all other respects.
3320
 
3321
     You may extract a single document from such a collection, and
3322
     distribute it individually under this License, provided you insert
3323
     a copy of this License into the extracted document, and follow
3324
     this License in all other respects regarding verbatim copying of
3325
     that document.
3326
 
3327
  7. AGGREGATION WITH INDEPENDENT WORKS
3328
 
3329
     A compilation of the Document or its derivatives with other
3330
     separate and independent documents or works, in or on a volume of
3331
     a storage or distribution medium, is called an "aggregate" if the
3332
     copyright resulting from the compilation is not used to limit the
3333
     legal rights of the compilation's users beyond what the individual
3334
     works permit.  When the Document is included in an aggregate, this
3335
     License does not apply to the other works in the aggregate which
3336
     are not themselves derivative works of the Document.
3337
 
3338
     If the Cover Text requirement of section 3 is applicable to these
3339
     copies of the Document, then if the Document is less than one half
3340
     of the entire aggregate, the Document's Cover Texts may be placed
3341
     on covers that bracket the Document within the aggregate, or the
3342
     electronic equivalent of covers if the Document is in electronic
3343
     form.  Otherwise they must appear on printed covers that bracket
3344
     the whole aggregate.
3345
 
3346
  8. TRANSLATION
3347
 
3348
     Translation is considered a kind of modification, so you may
3349
     distribute translations of the Document under the terms of section
3350
     4.  Replacing Invariant Sections with translations requires special
3351
     permission from their copyright holders, but you may include
3352
     translations of some or all Invariant Sections in addition to the
3353
     original versions of these Invariant Sections.  You may include a
3354
     translation of this License, and all the license notices in the
3355
     Document, and any Warranty Disclaimers, provided that you also
3356
     include the original English version of this License and the
3357
     original versions of those notices and disclaimers.  In case of a
3358
     disagreement between the translation and the original version of
3359
     this License or a notice or disclaimer, the original version will
3360
     prevail.
3361
 
3362
     If a section in the Document is Entitled "Acknowledgements",
3363
     "Dedications", or "History", the requirement (section 4) to
3364
     Preserve its Title (section 1) will typically require changing the
3365
     actual title.
3366
 
3367
  9. TERMINATION
3368
 
3369
     You may not copy, modify, sublicense, or distribute the Document
3370
     except as expressly provided for under this License.  Any other
3371
     attempt to copy, modify, sublicense or distribute the Document is
3372
     void, and will automatically terminate your rights under this
3373
     License.  However, parties who have received copies, or rights,
3374
     from you under this License will not have their licenses
3375
     terminated so long as such parties remain in full compliance.
3376
 
3377
 10. FUTURE REVISIONS OF THIS LICENSE
3378
 
3379
     The Free Software Foundation may publish new, revised versions of
3380
     the GNU Free Documentation License from time to time.  Such new
3381
     versions will be similar in spirit to the present version, but may
3382
     differ in detail to address new problems or concerns.  See
3383
     `http://www.gnu.org/copyleft/'.
3384
 
3385
     Each version of the License is given a distinguishing version
3386
     number.  If the Document specifies that a particular numbered
3387
     version of this License "or any later version" applies to it, you
3388
     have the option of following the terms and conditions either of
3389
     that specified version or of any later version that has been
3390
     published (not as a draft) by the Free Software Foundation.  If
3391
     the Document does not specify a version number of this License,
3392
     you may choose any version ever published (not as a draft) by the
3393
     Free Software Foundation.
3394
 
3395
ADDENDUM: How to use this License for your documents
3396
====================================================
3397
 
3398
To use this License in a document you have written, include a copy of
3399
the License in the document and put the following copyright and license
3400
notices just after the title page:
3401
 
3402
       Copyright (C)  YEAR  YOUR NAME.
3403
       Permission is granted to copy, distribute and/or modify this document
3404
       under the terms of the GNU Free Documentation License, Version 1.2
3405
       or any later version published by the Free Software Foundation;
3406
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3407
       Texts.  A copy of the license is included in the section entitled ``GNU
3408
       Free Documentation License''.
3409
 
3410
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3411
replace the "with...Texts." line with this:
3412
 
3413
         with the Invariant Sections being LIST THEIR TITLES, with
3414
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3415
         being LIST.
3416
 
3417
If you have Invariant Sections without Cover Texts, or some other
3418
combination of the three, merge those two alternatives to suit the
3419
situation.
3420
 
3421
If your document contains nontrivial examples of program code, we
3422
recommend releasing these examples in parallel under your choice of
3423
free software license, such as the GNU General Public License, to
3424
permit their use in free software.
3425
 
3426

3427
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3428
 
3429
Index
3430
*****
3431
 
3432
 
3433
* Menu:
3434
3435
* --cumulative:                          Profiling Utility.   (line  26)
3436
* --debug-config:                        Standalone Simulator.
3437
                                                              (line  48)
3438 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3439 127 jeremybenn
                                                              (line 105)
3440 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3441 127 jeremybenn
                                                              (line 118)
3442 124 jeremybenn
* --disable-debug:                       Configuring the Build.
3443 127 jeremybenn
                                                              (line  98)
3444 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3445 104 jeremybenn
                                                              (line  59)
3446 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3447 127 jeremybenn
                                                              (line 133)
3448 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3449 104 jeremybenn
                                                              (line  30)
3450 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3451 127 jeremybenn
                                                              (line  92)
3452
* --disable-unsigned-xori:               Configuring the Build.
3453 104 jeremybenn
                                                              (line  69)
3454 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3455 127 jeremybenn
                                                              (line 104)
3456 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3457 127 jeremybenn
                                                              (line 117)
3458 124 jeremybenn
* --enable-debug:                        Configuring the Build.
3459 127 jeremybenn
                                                              (line  97)
3460 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3461 104 jeremybenn
                                                              (line  58)
3462 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3463 104 jeremybenn
                                                              (line  37)
3464 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3465
                                                              (line  77)
3466
* --enable-ov-flag:                      Configuring the Build.
3467 127 jeremybenn
                                                              (line 132)
3468 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3469
                                                              (line  74)
3470
* --enable-profiling:                    Configuring the Build.
3471 104 jeremybenn
                                                              (line  29)
3472 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3473 127 jeremybenn
                                                              (line  91)
3474
* --enable-unsigned-xori:                Configuring the Build.
3475 104 jeremybenn
                                                              (line  68)
3476 19 jeremybenn
* --file:                                Standalone Simulator.
3477
                                                              (line  24)
3478
* --filename:                            Memory Profiling Utility.
3479
                                                              (line  51)
3480
* --generate:                            Profiling Utility.   (line  34)
3481
* --group:                               Memory Profiling Utility.
3482
                                                              (line  47)
3483
* --help:                                Standalone Simulator.
3484
                                                              (line  20)
3485
* --help (memory profiling utility):     Memory Profiling Utility.
3486
                                                              (line  22)
3487
* --help (profiling utility):            Profiling Utility.   (line  22)
3488
* --interactive:                         Standalone Simulator.
3489
                                                              (line  54)
3490
* --mode:                                Memory Profiling Utility.
3491
                                                              (line  26)
3492
* --nosrv:                               Standalone Simulator.
3493
                                                              (line  32)
3494
* --quiet:                               Profiling Utility.   (line  30)
3495
* --srv:                                 Standalone Simulator.
3496
                                                              (line  40)
3497
* --strict-npc:                          Standalone Simulator.
3498
                                                              (line  57)
3499
* --version:                             Standalone Simulator.
3500
                                                              (line  16)
3501
* --version (memory profiling utility):  Memory Profiling Utility.
3502
                                                              (line  17)
3503
* --version (profiling utility):         Profiling Utility.   (line  17)
3504
* -c:                                    Profiling Utility.   (line  26)
3505
* -d:                                    Standalone Simulator.
3506
                                                              (line  48)
3507
* -f <1>:                                Memory Profiling Utility.
3508
                                                              (line  51)
3509
* -f:                                    Standalone Simulator.
3510
                                                              (line  24)
3511
* -g <1>:                                Memory Profiling Utility.
3512
                                                              (line  47)
3513
* -g:                                    Profiling Utility.   (line  34)
3514
* -h:                                    Standalone Simulator.
3515
                                                              (line  20)
3516
* -h (memory profiling utility):         Memory Profiling Utility.
3517
                                                              (line  22)
3518
* -h (profiling utility):                Profiling Utility.   (line  22)
3519
* -i:                                    Standalone Simulator.
3520
                                                              (line  54)
3521
* -m:                                    Memory Profiling Utility.
3522
                                                              (line  26)
3523
* -q:                                    Profiling Utility.   (line  30)
3524
* -v:                                    Standalone Simulator.
3525
                                                              (line  16)
3526
* -v (memory profiling utility):         Memory Profiling Utility.
3527
                                                              (line  17)
3528
* -v (profiling utility):                Profiling Utility.   (line  17)
3529
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3530
                                                              (line  49)
3531
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3532
                                                              (line  55)
3533
* 0x02 UART VAPI sub-command (UART verification): Verification API.
3534
                                                              (line  59)
3535
* 0x03 UART VAPI sub-command (UART verification): Verification API.
3536
                                                              (line  62)
3537
* 0x04 UART VAPI sub-command (UART verification): Verification API.
3538
                                                              (line  66)
3539
* 16550 (UART configuration):            UART Configuration.  (line  73)
3540 82 jeremybenn
* all tests enabled:                     Configuring the Build.
3541 127 jeremybenn
                                                              (line 105)
3542 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
3543 127 jeremybenn
                                                              (line  98)
3544 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
3545
                                                              (line   6)
3546
* ATA/ATAPI device configuration:        Disc Interface Configuration.
3547
                                                              (line  88)
3548
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
3549
                                                              (line  32)
3550
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
3551
                                                              (line  22)
3552
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
3553
* baseaddr (Ethernet configuration):     Ethernet Configuration.
3554
                                                              (line  22)
3555
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
3556
                                                              (line  20)
3557
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
3558
                                                              (line  22)
3559
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
3560
* baseaddr (keyboard configuration):     Keyboard Configuration.
3561
                                                              (line  36)
3562
* baseaddr (memory configuration):       Memory Configuration.
3563 98 jeremybenn
                                                              (line  87)
3564 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
3565 98 jeremybenn
                                                              (line  46)
3566 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
3567
* baseaddr (VGA configuration):          Display Interface Configuration.
3568
                                                              (line  26)
3569
* blocksize (cache configuration):       Cache Configuration. (line  29)
3570
* BPB configuration:                     Branch Prediction Configuration.
3571
                                                              (line   6)
3572
* branch prediction configuration:       Branch Prediction Configuration.
3573
                                                              (line   6)
3574
* break (Interactive CLI):               Interactive Command Line.
3575
                                                              (line  57)
3576
* breakpoint list (Interactive CLI):     Interactive Command Line.
3577
                                                              (line  60)
3578
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
3579
                                                              (line  57)
3580
* breaks (Interactive CLI):              Interactive Command Line.
3581
                                                              (line  60)
3582
* btic (branch prediction configuration): Branch Prediction Configuration.
3583
                                                              (line  19)
3584
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3585
                                                              (line  48)
3586
* cache configuration:                   Cache Configuration. (line   6)
3587
* calling_convention (CUC configuration): CUC Configuration.  (line  34)
3588
* ce (memory configuration):             Memory Configuration.
3589 98 jeremybenn
                                                              (line 117)
3590 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
3591
* channel (UART configuration):          UART Configuration.  (line  29)
3592
* clear breakpoint (Interactive CLI):    Interactive Command Line.
3593
                                                              (line  57)
3594 82 jeremybenn
* clkcycle (simulator configuration):    Simulator Behavior.  (line 103)
3595 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
3596
                                                              (line  54)
3597
* command line for Or1ksim standalone use: Standalone Simulator.
3598
                                                              (line   6)
3599
* complex model:                         Configuring the Build.
3600 104 jeremybenn
                                                              (line  37)
3601 19 jeremybenn
* config:                                Global Data Structures.
3602
                                                              (line   7)
3603
* config.bpb:                            Global Data Structures.
3604
                                                              (line  37)
3605
* config.cpu:                            Global Data Structures.
3606
                                                              (line  22)
3607
* config.cuc:                            Global Data Structures.
3608
                                                              (line  18)
3609
* config.dc:                             Global Data Structures.
3610
                                                              (line  25)
3611
* config.debug:                          Global Data Structures.
3612
                                                              (line  40)
3613
* config.pic:                            Global Data Structures.
3614
                                                              (line  33)
3615
* config.pm:                             Global Data Structures.
3616
                                                              (line  29)
3617
* config.sim:                            Global Data Structures.
3618
                                                              (line  11)
3619
* config.vapi:                           Global Data Structures.
3620
                                                              (line  14)
3621
* configuration dynamic structure:       Global Data Structures.
3622
                                                              (line  49)
3623
* configuration file structure:          Configuration File Format.
3624
                                                              (line   6)
3625
* configuration global structure:        Global Data Structures.
3626
                                                              (line   7)
3627
* configuration info (Interactive CLI):  Interactive Command Line.
3628
                                                              (line 119)
3629
* configuration of generic peripherals:  Generic Peripheral Configuration.
3630
                                                              (line   6)
3631
* configuration parameter setting (Interactive CLI): Interactive Command Line.
3632
                                                              (line 146)
3633
* configuring branch prediction:         Branch Prediction Configuration.
3634
                                                              (line   6)
3635
* configuring data & instruction caches: Cache Configuration. (line   6)
3636
* configuring data & instruction MMUs:   Memory Management Configuration.
3637
                                                              (line   6)
3638
* configuring DMA:                       DMA Configuration.   (line   6)
3639
* configuring memory:                    Memory Configuration.
3640
                                                              (line   6)
3641
* configuring Or1ksim:                   Configuration.       (line   6)
3642
* configuring power management:          Power Management Configuration.
3643
                                                              (line   6)
3644
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
3645
                                                              (line   6)
3646
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
3647
* configuring the CPU:                   CPU Configuration.   (line   6)
3648
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
3649
                                                              (line   6)
3650
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
3651
                                                              (line   6)
3652
* configuring the Ethernet interface:    Ethernet Configuration.
3653
                                                              (line   6)
3654
* configuring the frame buffer:          Frame Buffer Configuration.
3655
                                                              (line   6)
3656
* configuring the GPIO:                  GPIO Configuration.  (line   6)
3657
* configuring the interrupt controller:  Interrupt Configuration.
3658
                                                              (line   6)
3659
* configuring the keyboard interface:    Keyboard Configuration.
3660
                                                              (line   6)
3661
* configuring the memory controller:     Memory Controller Configuration.
3662
                                                              (line   6)
3663
* configuring the processor:             CPU Configuration.   (line   6)
3664
* configuring the PS2 interface:         Keyboard Configuration.
3665
                                                              (line   6)
3666
* configuring the UART:                  UART Configuration.  (line   6)
3667
* configuring the Verification API (VAPI): Verification API Configuration.
3668
                                                              (line   6)
3669
* configuring the VGA interface:         Display Interface Configuration.
3670
                                                              (line   6)
3671
* copying memory (Interactive CLI):      Interactive Command Line.
3672
                                                              (line  54)
3673
* CPU configuration:                     CPU Configuration.   (line   6)
3674
* CUC configuration:                     CUC Configuration.   (line   6)
3675
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
3676
                                                              (line 162)
3677
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
3678
* data cache configuration:              Cache Configuration. (line   6)
3679
* data MMU configuration:                Memory Management Configuration.
3680
                                                              (line   6)
3681
* DCGE (power management register):      Power Management Configuration.
3682
                                                              (line  21)
3683
* debug (Interactive CLI):               Interactive Command Line.
3684
                                                              (line 151)
3685
* debug (simulator configuration):       Simulator Behavior.  (line  13)
3686
* debug channel toggle (Interactive CLI): Interactive Command Line.
3687
                                                              (line 141)
3688
* debug interface configuration:         Debug Interface Configuration.
3689
                                                              (line   6)
3690
* debug mode toggle (Interactive CLI):   Interactive Command Line.
3691
                                                              (line 151)
3692
* debug unit configuration:              Debug Interface Configuration.
3693
                                                              (line   6)
3694
* Debug Unit verification (VAPI):        Verification API.    (line  34)
3695
* debugging enabled (Argtable2):         Configuring the Build.
3696 127 jeremybenn
                                                              (line  98)
3697 104 jeremybenn
* DejaGnu board configurations:          Regression Testing.  (line  35)
3698
* DejaGnu configuration:                 Regression Testing.  (line  21)
3699
* DejaGNU tests directories:             Regression Testing.  (line  50)
3700
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
3701 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
3702 98 jeremybenn
                                                              (line 137)
3703 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
3704 98 jeremybenn
                                                              (line 143)
3705
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
3706 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
3707
                                                              (line  36)
3708
* disassemble (Interactive CLI):         Interactive Command Line.
3709
                                                              (line  41)
3710
* disc interface configuration:          Disc Interface Configuration.
3711
                                                              (line   6)
3712
* disc interface device configuration:   Disc Interface Configuration.
3713
                                                              (line  88)
3714
* display interface configuration:       Display Interface Configuration.
3715
                                                              (line   6)
3716
* displaying memory (Interactive CLI):   Interactive Command Line.
3717
                                                              (line  31)
3718
* displaying registers (Interactive CLI): Interactive Command Line.
3719
                                                              (line  14)
3720
* dm (Interactive CLI):                  Interactive Command Line.
3721
                                                              (line  31)
3722
* dma (Ethernet configuration):          Ethernet Configuration.
3723
                                                              (line  33)
3724
* DMA configuration:                     DMA Configuration.   (line   6)
3725
* DMA verification (VAPI):               Verification API.    (line  73)
3726
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
3727
                                                              (line  70)
3728
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3729
                                                              (line  71)
3730
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
3731
                                                              (line  69)
3732
* DME (power management register):       Power Management Configuration.
3733
                                                              (line  15)
3734
* DMMU configuration:                    Memory Management Configuration.
3735
                                                              (line   6)
3736
* doze mode (power management register): Power Management Configuration.
3737
                                                              (line  15)
3738
* dv (Interactive CLI):                  Interactive Command Line.
3739
                                                              (line 124)
3740
* dynamic clock gating (power management register): Power Management Configuration.
3741
                                                              (line  21)
3742
* dynamic model:                         Configuring the Build.
3743 104 jeremybenn
                                                              (line  37)
3744 19 jeremybenn
* dynamic ports, use of:                 Verification API Configuration.
3745
                                                              (line  23)
3746
* edge_trigger (interrupt controller):   Interrupt Configuration.
3747
                                                              (line  16)
3748
* enable_bursts (CUC configuration):     CUC Configuration.   (line  38)
3749
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
3750
                                                              (line  18)
3751
* enabled (branch prediction configuration): Branch Prediction Configuration.
3752
                                                              (line  15)
3753
* enabled (cache configuration):         Cache Configuration. (line  11)
3754
* enabled (debug interface configuration): Debug Interface Configuration.
3755
                                                              (line  11)
3756
* enabled (DMA configuration):           DMA Configuration.   (line  20)
3757
* enabled (Ethernet configuration):      Ethernet Configuration.
3758
                                                              (line  18)
3759
* enabled (frame buffer configuration):  Frame Buffer Configuration.
3760
                                                              (line  16)
3761
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
3762
                                                              (line  18)
3763
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
3764
* enabled (interrupt controller):        Interrupt Configuration.
3765
                                                              (line  12)
3766
* enabled (keyboard configuration):      Keyboard Configuration.
3767
                                                              (line  32)
3768
* enabled (memory controller configuration): Memory Controller Configuration.
3769 98 jeremybenn
                                                              (line  35)
3770 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
3771
                                                              (line  12)
3772
* enabled (power management configuration): Power Management Configuration.
3773
                                                              (line  35)
3774
* enabled (UART configuration):          UART Configuration.  (line  18)
3775
* enabled (verification API configuration): Verification API Configuration.
3776
                                                              (line  15)
3777
* enabled (VGA configuration):           Display Interface Configuration.
3778
                                                              (line  22)
3779
* enabling Ethernet via socket:          Configuring the Build.
3780 104 jeremybenn
                                                              (line  59)
3781 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
3782
                                                              (line  32)
3783
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
3784
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
3785
* Ethernet configuration:                Ethernet Configuration.
3786
                                                              (line   6)
3787
* Ethernet verification (VAPI):          Verification API.    (line  78)
3788
* Ethernet via socket, enabling:         Configuring the Build.
3789 104 jeremybenn
                                                              (line  59)
3790 127 jeremybenn
* exclusive-OR immediate operand:        Configuring the Build.
3791
                                                              (line  69)
3792 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
3793
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
3794
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
3795 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
3796 82 jeremybenn
                                                              (line  97)
3797 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
3798 82 jeremybenn
                                                              (line  93)
3799 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
3800 82 jeremybenn
                                                              (line  86)
3801
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
3802 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
3803 82 jeremybenn
                                                              (line  58)
3804 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
3805 82 jeremybenn
                                                              (line  62)
3806 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
3807 82 jeremybenn
                                                              (line  69)
3808 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
3809 82 jeremybenn
                                                              (line  74)
3810 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
3811
                                                              (line  23)
3812
* execution history (Interactive CLI):   Interactive Command Line.
3813
                                                              (line  67)
3814
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
3815
                                                              (line 104)
3816
* file (keyboard configuration):         Keyboard Configuration.
3817
                                                              (line  51)
3818
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
3819 82 jeremybenn
                                                              (line  36)
3820 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
3821
                                                              (line  47)
3822
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
3823
                                                              (line 117)
3824
* flag setting by instructions:          Configuring the Build.
3825 127 jeremybenn
                                                              (line 118)
3826 104 jeremybenn
* floating point multiply and add:       Known Issues.        (line  56)
3827
* floating point support:                Known Issues.        (line  42)
3828 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
3829
                                                              (line   6)
3830
* gdb_enabled (debug interface configuration): Debug Interface Configuration.
3831
                                                              (line  47)
3832
* generic peripheral configuration:      Generic Peripheral Configuration.
3833
                                                              (line   6)
3834
* GPIO configuration:                    GPIO Configuration.  (line   6)
3835
* GPIO verification (VAPI):              Verification API.    (line  88)
3836
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
3837
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
3838
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
3839
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
3840
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
3841
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
3842
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
3843 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
3844 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
3845 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
3846
                                                              (line 121)
3847
* help (Interactive CLI):                Interactive Command Line.
3848
                                                              (line 170)
3849
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
3850
                                                              (line 133)
3851
* hide_device_id (verification API configuration): Verification API Configuration.
3852
                                                              (line  36)
3853
* hist (Interactive CLI):                Interactive Command Line.
3854
                                                              (line  67)
3855 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
3856 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
3857
                                                              (line  67)
3858
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
3859
                                                              (line  33)
3860
* hitdelay (instruction cache configuration): Cache Configuration.
3861
                                                              (line  38)
3862
* hitdelay (MMU configuration):          Memory Management Configuration.
3863
                                                              (line  51)
3864 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
3865 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3866
                                                              (line  49)
3867
* IMMU configuration:                    Memory Management Configuration.
3868
                                                              (line   6)
3869
* index (memory controller configuration): Memory Controller Configuration.
3870 98 jeremybenn
                                                              (line  68)
3871 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
3872
                                                              (line 119)
3873
* installing Or1ksim:                    Installation.        (line   6)
3874
* instruction cache configuration:       Cache Configuration. (line   6)
3875
* instruction MMU configuration:         Memory Management Configuration.
3876
                                                              (line   6)
3877
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
3878
* instruction profiling utility (Interactive CLI): Interactive Command Line.
3879
                                                              (line 178)
3880
* internal debugging:                    Internal Debugging.  (line   6)
3881
* interrupt controller configuration:    Interrupt Configuration.
3882
                                                              (line   6)
3883
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
3884
                                                              (line  32)
3885
* irq (DMA configuration):               DMA Configuration.   (line  34)
3886
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
3887
* irq (keyboard configuration):          Keyboard Configuration.
3888
                                                              (line  47)
3889
* irq (UART configuration):              UART Configuration.  (line  70)
3890
* irq (VGA configuration):               Display Interface Configuration.
3891
                                                              (line  37)
3892
* jitter (UART configuration):           UART Configuration.  (line  78)
3893
* keyboard configuration:                Keyboard Configuration.
3894
                                                              (line   6)
3895 104 jeremybenn
* lf.madd.s:                             Known Issues.        (line  56)
3896 19 jeremybenn
* library version of Or1ksim:            Simulator Library.   (line   6)
3897
* license for Or1ksim:                   GNU Free Documentation License.
3898
                                                              (line   6)
3899
* list breakpoints (Interactive CLI):    Interactive Command Line.
3900
                                                              (line  60)
3901
* load_hitdelay (data cache configuration): Cache Configuration.
3902
                                                              (line  46)
3903
* load_missdelay (data cache configuration): Cache Configuration.
3904
                                                              (line  50)
3905
* log (memory configuration):            Memory Configuration.
3906 98 jeremybenn
                                                              (line 149)
3907 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
3908
                                                              (line  28)
3909 93 jeremybenn
* long:                                  Simulator Library.   (line  87)
3910 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
3911 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
3912 98 jeremybenn
                                                              (line 126)
3913 19 jeremybenn
* memory configuration:                  Memory Configuration.
3914
                                                              (line   6)
3915
* memory controller configuration:       Memory Controller Configuration.
3916
                                                              (line   6)
3917
* memory copying (Interactive CLI):      Interactive Command Line.
3918
                                                              (line  54)
3919
* memory display (Interactive CLI):      Interactive Command Line.
3920
                                                              (line  31)
3921
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
3922
                                                              (line 133)
3923
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
3924
                                                              (line 124)
3925
* memory patching (Interactive CLI):     Interactive Command Line.
3926
                                                              (line  48)
3927
* memory profiling end address:          Memory Profiling Utility.
3928
                                                              (line  56)
3929
* memory profiling start address:        Memory Profiling Utility.
3930
                                                              (line  56)
3931
* memory profiling utility (Interactive CLI): Interactive Command Line.
3932
                                                              (line 173)
3933
* memory profiling version of Or1ksim:   Memory Profiling Utility.
3934
                                                              (line   6)
3935
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
3936
* memory_order=exact (CUC configuration): CUC Configuration.  (line  27)
3937
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
3938
* memory_order=strong (CUC configuration): CUC Configuration. (line  25)
3939
* memory_order=weak (CUC configuration): CUC Configuration.   (line  21)
3940
* missdelay (branch prediction configuration): Branch Prediction Configuration.
3941
                                                              (line  37)
3942
* missdelay (instruction cache configuration): Cache Configuration.
3943
                                                              (line  42)
3944
* missdelay (MMU configuration):         Memory Management Configuration.
3945
                                                              (line  55)
3946
* MMU configuration:                     Memory Management Configuration.
3947
                                                              (line   6)
3948 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
3949 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
3950 82 jeremybenn
                                                              (line  34)
3951 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
3952
                                                              (line 173)
3953 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
3954 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
3955
                                                              (line 128)
3956
* name (generic peripheral configuration): Generic Peripheral Configuration.
3957
                                                              (line  42)
3958
* name (memory configuration):           Memory Configuration.
3959 98 jeremybenn
                                                              (line 108)
3960 19 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  42)
3961
* nsets (cache configuration):           Cache Configuration. (line  15)
3962
* nsets (MMU configuration):             Memory Management Configuration.
3963
                                                              (line  16)
3964
* nways (cache configuration):           Cache Configuration. (line  22)
3965
* nways (MMU configuration):             Memory Management Configuration.
3966
                                                              (line  22)
3967 93 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  77)
3968
* or1ksim_init:                          Simulator Library.   (line  14)
3969
* or1ksim_interrupt:                     Simulator Library.   (line  92)
3970
* or1ksim_interrupt_clear:               Simulator Library.   (line 110)
3971
* or1ksim_interrupt_set:                 Simulator Library.   (line 101)
3972
* or1ksim_is_le:                         Simulator Library.   (line  82)
3973 104 jeremybenn
* or1ksim_jtag_reset:                    Simulator Library.   (line 119)
3974
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 141)
3975
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 127)
3976 93 jeremybenn
* or1ksim_reset_duration:                Simulator Library.   (line  62)
3977
* or1ksim_run:                           Simulator Library.   (line  57)
3978
* or1ksim_set_time_point:                Simulator Library.   (line  73)
3979 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
3980
* overflow flag setting by instructions: Configuring the Build.
3981 127 jeremybenn
                                                              (line 133)
3982 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
3983
                                                              (line 113)
3984
* pagesize (MMU configuration):          Memory Management Configuration.
3985
                                                              (line  27)
3986
* patching memory (Interactive CLI):     Interactive Command Line.
3987
                                                              (line  48)
3988
* patching registers (Interactive CLI):  Interactive Command Line.
3989
                                                              (line  28)
3990
* patching the program counter (Interactive CLI): Interactive Command Line.
3991
                                                              (line  51)
3992
* pattern (memory configuration):        Memory Configuration.
3993 98 jeremybenn
                                                              (line  75)
3994 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
3995
                                                              (line  51)
3996
* PIC configuration:                     Interrupt Configuration.
3997
                                                              (line   6)
3998
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
3999
                                                              (line 132)
4000
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
4001
                                                              (line  51)
4002
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
4003
                                                              (line  52)
4004
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
4005
                                                              (line  53)
4006
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4007
                                                              (line  54)
4008
* pm (Interactive CLI):                  Interactive Command Line.
4009
                                                              (line  48)
4010
* PMR - DGCE:                            Power Management Configuration.
4011
                                                              (line  21)
4012
* PMR - DME:                             Power Management Configuration.
4013
                                                              (line  15)
4014
* PMR - SDF:                             Power Management Configuration.
4015
                                                              (line  12)
4016
* PMR - SME:                             Power Management Configuration.
4017
                                                              (line  16)
4018
* PMR - SUME:                            Power Management Configuration.
4019
                                                              (line  24)
4020
* PMU configuration:                     Power Management Configuration.
4021
                                                              (line   6)
4022
* poc (memory controller configuration): Memory Controller Configuration.
4023 98 jeremybenn
                                                              (line  55)
4024 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4025
                                                              (line  23)
4026
* power management configuration:        Power Management Configuration.
4027
                                                              (line   6)
4028
* power management register, DGCE:       Power Management Configuration.
4029
                                                              (line  21)
4030
* power management register, DME:        Power Management Configuration.
4031
                                                              (line  15)
4032
* power management register, SDF:        Power Management Configuration.
4033
                                                              (line  12)
4034
* power management register, SME:        Power Management Configuration.
4035
                                                              (line  16)
4036
* power management register, SUME:       Power Management Configuration.
4037
                                                              (line  24)
4038
* pr (Interactive CLI):                  Interactive Command Line.
4039
                                                              (line  28)
4040
* private ports, use of:                 Verification API Configuration.
4041
                                                              (line  23)
4042
* processor configuration:               CPU Configuration.   (line   6)
4043
* processor stall (Interactive CLI):     Interactive Command Line.
4044
                                                              (line  72)
4045
* processor unstall (Interactive CLI):   Interactive Command Line.
4046
                                                              (line  78)
4047
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4048
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4049
                                                              (line  23)
4050
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4051
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4052
* profiling utility (Interactive CLI):   Interactive Command Line.
4053
                                                              (line 178)
4054
* program counter patching (Interactive CLI): Interactive Command Line.
4055
                                                              (line  51)
4056
* programmable interrupt controller configuration: Interrupt Configuration.
4057
                                                              (line   6)
4058
* PS2 configuration:                     Keyboard Configuration.
4059
                                                              (line   6)
4060
* q (Interactive CLI):                   Interactive Command Line.
4061
                                                              (line  11)
4062
* quitting (Interactive CLI):            Interactive Command Line.
4063
                                                              (line  11)
4064
* r (Interactive CLI):                   Interactive Command Line.
4065
                                                              (line  14)
4066
* random_seed (memory configuration):    Memory Configuration.
4067 98 jeremybenn
                                                              (line  65)
4068 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4069 82 jeremybenn
                                                              (line  30)
4070 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4071
                                                              (line  41)
4072
* reg_sim_reset:                         Concepts.            (line  13)
4073
* register display (Interactive CLI):    Interactive Command Line.
4074
                                                              (line  14)
4075
* register over time statistics:         Configuring the Build.
4076 127 jeremybenn
                                                              (line  92)
4077 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4078
                                                              (line  28)
4079 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4080 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4081
                                                              (line  20)
4082
* reset (Interactive CLI):               Interactive Command Line.
4083
                                                              (line  63)
4084
* reset hooks:                           Concepts.            (line  13)
4085
* reset the simulator (Interactive CLI): Interactive Command Line.
4086
                                                              (line  63)
4087
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4088
                                                              (line  44)
4089
* rev (CPU configuration):               CPU Configuration.   (line  15)
4090
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4091
                                                              (line  20)
4092
* rsp_port (debug interface configuration): Debug Interface Configuration.
4093
                                                              (line  36)
4094
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4095
                                                              (line  46)
4096
* run (Interactive CLI):                 Interactive Command Line.
4097
                                                              (line  23)
4098
* running code (Interactive CLI):        Interactive Command Line.
4099
                                                              (line  23)
4100
* running Or1ksim:                       Usage.               (line   6)
4101
* runtime:                               Global Data Structures.
4102
                                                              (line  58)
4103
* runtime global structure:              Global Data Structures.
4104
                                                              (line  58)
4105
* runtime.cpu:                           Global Data Structures.
4106
                                                              (line  62)
4107
* runtime.cpu.fout:                      Concepts.            (line   7)
4108
* runtime.cuc:                           Global Data Structures.
4109
                                                              (line  62)
4110
* runtime.vapi:                          Global Data Structures.
4111
                                                              (line  62)
4112
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4113
                                                              (line  59)
4114
* rxfile (Ethernet configuration):       Ethernet Configuration.
4115
                                                              (line  68)
4116
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4117
                                                              (line  23)
4118
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4119
                                                              (line  28)
4120 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4121 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4122
                                                              (line  12)
4123
* section ata:                           Disc Interface Configuration.
4124
                                                              (line   6)
4125
* section bpb:                           Branch Prediction Configuration.
4126
                                                              (line   6)
4127
* section cpio:                          GPIO Configuration.  (line   6)
4128
* section cpu:                           CPU Configuration.   (line   6)
4129
* section cuc:                           CUC Configuration.   (line   6)
4130
* section dc:                            Cache Configuration. (line   6)
4131
* section debug:                         Debug Interface Configuration.
4132
                                                              (line   6)
4133
* section dma:                           DMA Configuration.   (line   6)
4134
* section dmmu:                          Memory Management Configuration.
4135
                                                              (line   6)
4136
* section ethernet:                      Ethernet Configuration.
4137
                                                              (line   6)
4138
* section fb:                            Frame Buffer Configuration.
4139
                                                              (line   6)
4140
* section generic:                       Generic Peripheral Configuration.
4141
                                                              (line   6)
4142
* section ic:                            Cache Configuration. (line   6)
4143
* section immu:                          Memory Management Configuration.
4144
                                                              (line   6)
4145
* section kb:                            Keyboard Configuration.
4146
                                                              (line   6)
4147
* section mc:                            Memory Controller Configuration.
4148
                                                              (line   6)
4149
* section memory:                        Memory Configuration.
4150
                                                              (line   6)
4151
* section pic:                           Interrupt Configuration.
4152
                                                              (line   6)
4153
* section pmu:                           Power Management Configuration.
4154
                                                              (line   6)
4155
* section sim:                           Simulator Behavior.  (line   6)
4156
* section uart:                          UART Configuration.  (line   6)
4157
* section vapi:                          Verification API Configuration.
4158
                                                              (line   6)
4159
* section vga:                           Display Interface Configuration.
4160
                                                              (line   6)
4161
* sections:                              Global Data Structures.
4162
                                                              (line  49)
4163
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4164
                                                              (line 125)
4165
* server_port (debug interface configuration): Debug Interface Configuration.
4166
                                                              (line  69)
4167
* server_port (verification API configuration): Verification API Configuration.
4168
                                                              (line  19)
4169
* set (Interactive CLI):                 Interactive Command Line.
4170
                                                              (line 146)
4171
* set breakpoint (Interactive CLI):      Interactive Command Line.
4172
                                                              (line  57)
4173
* setdbch (Interactive CLI):             Interactive Command Line.
4174
                                                              (line 141)
4175
* simple model:                          Configuring the Build.
4176 104 jeremybenn
                                                              (line  37)
4177 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4178
* simulator configuration info (Interactive CLI): Interactive Command Line.
4179
                                                              (line 119)
4180
* simulator reset (Interactive CLI):     Interactive Command Line.
4181
                                                              (line  63)
4182
* simulator statistics (Interactive CLI): Interactive Command Line.
4183
                                                              (line  83)
4184
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4185
                                                              (line 109)
4186
* size (generic peripheral configuration): Generic Peripheral Configuration.
4187
                                                              (line  30)
4188
* size (memory configuration):           Memory Configuration.
4189 98 jeremybenn
                                                              (line  92)
4190 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4191
                                                              (line  16)
4192
* slow down factor (power management register): Power Management Configuration.
4193
                                                              (line  12)
4194
* SME (power management register):       Power Management Configuration.
4195
                                                              (line  16)
4196
* sockif (Ethernet configuration):       Ethernet Configuration.
4197
                                                              (line  83)
4198
* sr (CPU configuration):                CPU Configuration.   (line  53)
4199
* stall (Interactive CLI):               Interactive Command Line.
4200
                                                              (line  72)
4201
* stall the processor (Interactive CLI): Interactive Command Line.
4202
                                                              (line  72)
4203
* statistics, register over time:        Configuring the Build.
4204 127 jeremybenn
                                                              (line  92)
4205 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4206
                                                              (line  83)
4207
* stats (Interactive CLI):               Interactive Command Line.
4208
                                                              (line  83)
4209
* stepping code (Interactive CLI):       Interactive Command Line.
4210
                                                              (line  19)
4211
* store_hitdelay (data cache configuration): Cache Configuration.
4212
                                                              (line  54)
4213
* store_missdelay (data cache configuration): Cache Configuration.
4214
                                                              (line  58)
4215
* SUME (power management register):      Power Management Configuration.
4216
                                                              (line  24)
4217 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4218 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4219
                                                              (line  24)
4220
* t (Interactive CLI):                   Interactive Command Line.
4221
                                                              (line  19)
4222 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4223 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4224
                                                              (line  23)
4225
* TCP/IP port range for or1ksim service: Debug Interface Configuration.
4226
                                                              (line  74)
4227
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4228
                                                              (line  41)
4229 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4230
* test code for target:                  Regression Testing.  (line  63)
4231
* test make file:                        Regression Testing.  (line  27)
4232
* test README:                           Regression Testing.  (line  32)
4233
* testing:                               Regression Testing.  (line   6)
4234 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4235 127 jeremybenn
                                                              (line 105)
4236 19 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  46)
4237
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4238
                                                              (line  46)
4239
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4240
                                                              (line  57)
4241
* toggle debug channels (Interactive CLI): Interactive Command Line.
4242
                                                              (line 141)
4243
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4244
                                                              (line 151)
4245
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4246
                                                              (line  60)
4247
* txfile (Ethernet configuration):       Ethernet Configuration.
4248
                                                              (line  69)
4249
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4250 82 jeremybenn
                                                              (line  36)
4251 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4252
                                                              (line  47)
4253
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4254
                                                              (line  99)
4255
* type (memory configuration):           Memory Configuration.
4256 98 jeremybenn
                                                              (line  36)
4257 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4258 98 jeremybenn
                                                              (line  46)
4259 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4260 98 jeremybenn
                                                              (line  40)
4261 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4262 98 jeremybenn
                                                              (line  50)
4263 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4264 98 jeremybenn
                                                              (line  54)
4265 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4266
* UART I/O from/to a physical serial port: UART Configuration.
4267
                                                              (line  62)
4268
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4269
* UART I/O from/to files:                UART Configuration.  (line  33)
4270
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4271
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4272
* UART verification (VAPI):              Verification API.    (line  41)
4273
* unstall (Interactive CLI):             Interactive Command Line.
4274
                                                              (line  78)
4275
* unstall the processor (Interactive CLI): Interactive Command Line.
4276
                                                              (line  78)
4277
* upr (CPU configuration):               CPU Configuration.   (line  21)
4278
* ustates (cache configuration):         Cache Configuration. (line  33)
4279
* ustates (MMU configuration):           Memory Management Configuration.
4280
                                                              (line  41)
4281
* VAPI configuration:                    Verification API Configuration.
4282
                                                              (line   6)
4283
* VAPI for Debug Unit:                   Verification API.    (line  34)
4284
* VAPI for DMA:                          Verification API.    (line  73)
4285
* VAPI for Ethernet:                     Verification API.    (line  78)
4286
* VAPI for GPIO:                         Verification API.    (line  88)
4287
* VAPI for UART:                         Verification API.    (line  41)
4288
* vapi_id (debug interface configuration): Debug Interface Configuration.
4289
                                                              (line  80)
4290
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4291
                                                              (line  88)
4292
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4293
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4294
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4295
* vapi_log_file (verification API configuration): Verification API Configuration.
4296
                                                              (line  41)
4297
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4298
                                                              (line  41)
4299
* ver (CPU configuration):               CPU Configuration.   (line  15)
4300
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4301
* Verification API configuration:        Verification API Configuration.
4302
                                                              (line   6)
4303
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4304
                                                              (line 124)
4305
* VGA configuration:                     Display Interface Configuration.
4306
 
4307
 
4308
                                                              (line  50)
4309
4310
4311

4312
Tag Table:
4313 112 jeremybenn
Node: Top814
4314
Node: Installation1224
4315
Node: Preparation1471
4316 143 jeremybenn
Node: Configuring the Build1766
4317
Node: Build and Install7880
4318
Node: Known Issues8726
4319
Node: Usage11788
4320
Node: Standalone Simulator12002
4321
Node: Profiling Utility14905
4322
Node: Memory Profiling Utility15815
4323
Node: Simulator Library17180
4324
Node: Configuration24958
4325
Node: Configuration File Format25567
4326
Node: Configuration File Preprocessing25859
4327
Node: Configuration File Syntax26230
4328
Node: Simulator Configuration29015
4329
Node: Simulator Behavior29306
4330
Node: Verification API Configuration33350
4331
Node: CUC Configuration35290
4332
Node: Core OpenRISC Configuration37207
4333
Node: CPU Configuration37709
4334
Node: Memory Configuration41827
4335
Node: Memory Management Configuration48285
4336
Node: Cache Configuration50662
4337
Node: Interrupt Configuration53048
4338
Node: Power Management Configuration53784
4339
Node: Branch Prediction Configuration55061
4340
Node: Debug Interface Configuration56421
4341
Node: Peripheral Configuration60641
4342
Node: Memory Controller Configuration61267
4343
Node: UART Configuration64681
4344
Node: DMA Configuration68200
4345
Node: Ethernet Configuration70067
4346
Node: GPIO Configuration74043
4347
Node: Display Interface Configuration75676
4348
Node: Frame Buffer Configuration77985
4349
Node: Keyboard Configuration79849
4350
Node: Disc Interface Configuration82087
4351
Node: Generic Peripheral Configuration87030
4352
Node: Interactive Command Line89325
4353
Node: Verification API96299
4354
Node: Code Internals100729
4355
Node: Coding Conventions101312
4356
Node: Global Data Structures105739
4357
Node: Concepts108396
4358
Ref: Output Redirection108541
4359
Node: Internal Debugging109080
4360
Node: Regression Testing109604
4361
Node: GNU Free Documentation License113399

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