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This is ../../or1ksim/doc/or1ksim.info, produced by makeinfo version
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4.8 from ../../or1ksim/doc/or1ksim.texi.
3 19 jeremybenn
 
4
INFO-DIR-SECTION Embedded development
5
START-INFO-DIR-ENTRY
6
* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
7
                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 236 jeremybenn
     tar jxf or1ksim-2010-08-04.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
82 19 jeremybenn
default to OpenRISC 1000 32-bit with a warning
83
 
84 236 jeremybenn
     ../or1ksim-2010-08-04/configure --target=or32-uclinux ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 104 jeremybenn
For testing (using `make check'), the `--target' parameter _must_ be
92
specified, to allow the target tool chain to be selected. If the tools
93
have been installed using the standard OpenRISC script, then this
94
should be set to `or32-elf'.
95 19 jeremybenn
 
96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
101 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
`--enable-execution=dynamic'
108
     Or1ksim has developed to improve functionality and performance.
109
     This feature allows three versions of Or1ksim to be built
110
 
111
    `--enable-execution=simple'
112
          Build the original simple interpreting simulator
113
 
114
    `--enable-execution=complex'
115 82 jeremybenn
          Build a more complex interpreting simulator.  Experiments
116
          suggest this is 50% faster than the simple simulator.  This
117
          is the default.
118 19 jeremybenn
 
119
    `--enable-execution=dynamic'
120 82 jeremybenn
          Build a dynamically compiling simulator.  This is the way
121
          many modern ISS are built.  This represents a work in
122
          progress.  Currently Or1ksim will compile, but segfaults if
123
          configured with this option.
124 19 jeremybenn
 
125
 
126
     The default is `--enable-execution=complex'.
127
 
128
`--enable-ethphy'
129
`--disable-ethphy'
130
     If enabled, this option allows the Ethernet to be simulated by
131
     connecting via a socket (the alternative reads and writes, from
132 82 jeremybenn
     and to files).  This must then be configured using the relevant
133
     fields in the `ethernet' section of the configuration file.  *Note
134 19 jeremybenn
     Ethernet Configuration: Ethernet Configuration.
135
 
136
     The default is for this to be disabled.
137
 
138 127 jeremybenn
`--enable-unsigned-xori'
139
`--disable-unsigned-xori'
140
     Historically, `l.xori', has sign extended its operand. This is
141
     inconsistent with the other logical opcodes (`l.andi', `l.ori'),
142
     but in the absence of `l.not', it allows a register to be inverted
143
     in a single instruction using:
144
 
145
          `l.xori  rD,rA,-1'
146
 
147
     This flag causes Or1ksim to treat the immediate operand as
148
     unsigned (i.e to zero-extend rather than sign-extend).
149
 
150
     The default is to sign-extend, so that existing code will continue
151
     to work.
152
 
153
          Caution: The GNU compiler tool chain makes heavy use of this
154
          instruction.  Using unsigned behavior will require the
155
          compiler to be modified accordingly.
156
 
157
          This option is provided for experimentation.  A future
158
          version of OpenRISC may adopt this more consistent behavior
159
          and also provide a `l.not' opcode.
160
 
161 19 jeremybenn
`--enable-range-stats'
162
`--disable-range-stats'
163
     If enabled, this option allows statistics to be collected to
164 82 jeremybenn
     analyse register access over time.  The default is for this to be
165 19 jeremybenn
     disabled.
166
 
167
`--enable-debug'
168
`--disable-debug'
169
     This is a feature of the Argtable2 package used to process
170 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
171
     Argtable2.  It is provided for completeness, but there is no
172
     reason why this feature should ever be needed by any Or1ksim user.
173 19 jeremybenn
 
174 82 jeremybenn
`--enable-all-tests'
175
`--disable-all-tests'
176
     Some of the tests (at the time of writing just one) will not
177
     compile without error.  If enabled with this flag, all test
178
     programs will be compiled with `make check'.
179 19 jeremybenn
 
180 82 jeremybenn
     This flag is intended for those working on the test package, who
181
     wish to get the missing test(s) working.
182
 
183
 
184 112 jeremybenn
A number of configuration flags have been removed since version 0.3.0,
185 124 jeremybenn
because they led to invalid behavior of Or1ksim. Those removed are:
186 112 jeremybenn
 
187 124 jeremybenn
`--enable-arith-flag'
188
`--disable-arith-flag'
189
     If enabled, this option caused certain instructions to set the flag
190
     (`F' bit) in the supervision register if the result were zero.
191
     The instructions affected by this were `l.add', `l.addc',
192
     `l.addi', `l.and' and `l.andi'.
193
 
194
     If set, this caused incorrect behavior. Whether or not flags are
195
     set is part of the OpenRISC 1000 architectural specification.  The
196
     only flags which should set this are the "set flag" instructions:
197
     `l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
198
     `l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
199
     `l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
200
     `l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
201
 
202 112 jeremybenn
`--enable-ov-flag'
203
`--disable-ov-flag'
204 124 jeremybenn
     This flag caused certain instructions to set the overflow flag.
205
     If not, those instructions would not set the overflow flat.  The
206
     instructions affected by this were `l.add', `l.addc', `l.addi',
207
     `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
208
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
209
     `l.sub', `l.xor' and `l.xori'.
210 112 jeremybenn
 
211
     This guaranteed incorrect behavior.  The OpenRISC 1000 architecture
212
     specification defines which flags are set by which instructions.
213
 
214
     Within the above list, the arithmetic instructions (`l.add',
215
     `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
216
     `l.sub'), together with `l.addic' which is missed out, set the
217
     overflow flag.  All the others (`l.and', `l.andi', `l.or',
218
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
219
     `l.xor' and `l.xori') do not.
220
 
221
 
222 19 jeremybenn

223
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
224
 
225
1.3 Building and Installing
226
===========================
227
 
228 82 jeremybenn
Build the tool with:
229 19 jeremybenn
 
230
     make all
231 82 jeremybenn
 
232
If you have the OpenRISC tool chain and DejaGNU installed, you can
233
verify the tool as follows (otherwise omit this step):
234
 
235
     make check
236
 
237
Install the tool with:
238
 
239 19 jeremybenn
     make install
240
 
241
This will install the three variations of the Or1ksim tool,
242
`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the
243
Or1ksim library, `libsim', the header file, `or1ksim.h' and this
244
documentation in `info' format.
245
 
246
     Note: Testing Or1ksim with `make check' is not yet supported.
247
 
248
The documentation may be created and installed in alternative formats
249
(PDF, Postscript, DVI, HTML) with for example:
250
 
251
     make pdf
252
     make install-pdf
253
 
254

255
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
256
 
257
1.4 Known Problems and Issues
258
=============================
259
 
260 143 jeremybenn
The following problems and issues are known about with Or1ksim
261 236 jeremybenn
2010-08-04.  The OpenRISC tracker may be used to see the current state
262 143 jeremybenn
of these issues and to raise new problems and feature requests.  It may
263
be found at `http://www.opencores.org/ptracker.cgi/view/or1k/398'.
264 19 jeremybenn
 
265
   * The Supervision Register Little Endian Enable (LEE) bit is
266 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
267 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
268
 
269
   * The NPC is a read/write register, but after being written it
270 82 jeremybenn
     clears the pipeline.  This means that if the processor is stalled,
271 19 jeremybenn
     the value should subsequently read back as 0, until the processor
272 82 jeremybenn
     is unstalled and able to refill its pipeline.  By default Or1ksim
273 19 jeremybenn
     always reports back the value of NPC, even when it has been
274
     written while stalled.
275
 
276
     There is now an option, `--strict-npc', which will enforce this
277 82 jeremybenn
     behavior.  At some stage in the future it will become the default
278 19 jeremybenn
     behavior, but for now it is an option, since its use will break
279
     GDB.
280
 
281
   * The memory components are given names in the configuration file.
282
     However there is currently no way for Or1ksim to report that name
283
     back to the user (for example to identify which memory block
284
     corresponds to a particular access).
285
 
286
   * Or1ksim allows the processor to be stalled (from the command
287 82 jeremybenn
     line), even if there is no debugger present.  This seems to be a
288 19 jeremybenn
     meaningless operation.
289
 
290
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
291 82 jeremybenn
     instances using the library.  This is clearly a problem when
292
     considering multi-core applications.  However it stems from the
293
     original design, and can only be fixed by a complete rewrite.  The
294 19 jeremybenn
     entire source code uses static global constants liberally!
295
 
296 104 jeremybenn
   * There is no support for single precision floating point
297
     instructions in Or1ksim if configured in the CPU (*note CPU
298
     Configuration: CPU Configuration.).  These are implemented using
299
     the floating point support in the host C library, which will
300
     usually be IEEE 745 compliant.  There is at present no support for
301
     double precision floating point instructions, since these are
302
     meaningless with 32-bit registers.
303 19 jeremybenn
 
304 104 jeremybenn
     Floating point support within OpenRISC is intended to follow IEEE
305
     745, which offers a degree of configurability. However at present
306
     the FPSCR register is not supported, so there is no mechanism for
307
     configuring floating point behavior. Thus the default
308
     functionality of the host C library will be used.
309 19 jeremybenn
 
310 104 jeremybenn
   * The single precision floating point multiply and add instruction,
311
     `lf.madd.s', is not clearly specified in the original architectural
312
     manual. User should consult the `OpenRISC 1200 version 2
313
     Supplementary Programmer's Reference Manual' for a specification
314
     of the functionality implemented.
315
 
316
 
317 19 jeremybenn

318
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
319
 
320
2 Usage
321
*******
322
 
323
* Menu:
324
 
325
* Standalone Simulator::
326
* Profiling Utility::
327
* Memory Profiling Utility::
328
* Simulator Library::
329
 
330

331
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
332
 
333
2.1 Standalone Simulator
334
========================
335
 
336
The general form the standalone command is:
337
 
338
     or32-uclinux-sim [-vhi] [-f FILE] [--nosrv] [--srv=[N]] [-d STR]
339
                      [--enable-profile] [--enable-mprofile] [FILE]
340
 
341 82 jeremybenn
Many of the options have both a short and a long form.  For example
342
`-h' or `--help'.
343 19 jeremybenn
 
344
`-v'
345
`--version'
346
     Print out the version and copyright notice for Or1ksim and exit.
347
 
348
`-h'
349
`--help'
350
     Print out help about the command line options and what they mean.
351
 
352
`-f FILE'
353
`--file FILE'
354
     Read configuration commands from the specified file, looking first
355
     in the current directory, and otherwise in the `$HOME/.or1k'
356 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
357
     in those two locations is used.  Failure to find the file is a
358
     fatal error.  *Note Configuration: Configuration, for detailed
359
     information on configuring Or1ksim.
360 19 jeremybenn
 
361
`--nosrv'
362 235 jeremybenn
     Do not start up the "Remote Serial Protocol" debug server.  This
363
     overrides any setting specified in the configuration file.  This
364
     option may not be specified with `--srv'.  If it is, a rude
365
     message is printed and the `--nosrv' option is ignored.
366 19 jeremybenn
 
367
`--srv'
368
 
369
`--srv=N'
370 235 jeremybenn
     Start up the "Remote Serial Protocol" debug server.  This
371
     overrides any setting specified in the configuration file.  If the
372
     parameter, N, is specified, use that as the TCP/IP port for the
373
     server, otherwise a random value from the private port range
374
     (41920-65535) will be used.  This option may not be specified with
375
     `--nosrv'.  If it is, a rude message is printed and the `--nosrv'
376
     option is ignored.
377 19 jeremybenn
 
378
`-d=CONFIG_STRING'
379
`--debug-config=CONFIG_STRING'
380 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
381
     use by developers only, and is not covered further here.  See the
382 19 jeremybenn
     source code for more details.
383
 
384
`-i'
385
`--interactive'
386
     After starting, drop into the Or1ksim interactive command shell.
387
 
388
`--strict-npc'
389
     In real hardware, setting the next program counter (NPC, SPR 16),
390 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
391
     until the pipeline refills, reading the NPC will return zero.
392
     This is typically the case when debugging, since the processor is
393 19 jeremybenn
     stalled.
394
 
395
     Historically, Or1ksim has always returned the value of the NPC,
396 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
397
     is used, then Or1ksim will mirror real hardware more accurately.
398
     If the NPC is changed while the processor is stalled, subsequent
399 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
400
 
401
     This is not currently the default behavior, since tools such as
402
     GDB have been implemented assuming the historic Or1ksim behavior.
403
     However at some time in the future it will become the default.
404
 
405
`--enable-profile'
406
     Enable instruction profiling.
407
 
408
`--enable-mprofile'
409
     Enable memory profiling.
410
 
411
 
412

413
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
414
 
415
2.2 Profiling Utility
416
=====================
417
 
418 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
419
It may be invoked as a standalone command, or from the Or1ksim CLI.
420
The general form the standalone command is:
421 19 jeremybenn
 
422
     or32-uclinux-profile [-vhcq] [-g=FILE]
423
 
424 82 jeremybenn
Many of the options have both a short and a long form.  For example
425
`-h' or `--help'.
426 19 jeremybenn
 
427
`-v'
428
`--version'
429
     Print out the version and copyright notice for the Or1ksim
430
     profiling utility and exit.
431
 
432
`-h'
433
`--help'
434
     Print out help about the command line options and what they mean.
435
 
436
`-c'
437
`--cumulative'
438
     Show cumulative sum of cycles in functions
439
 
440
`-q'
441
`--quiet'
442
     Suppress messages
443
 
444
`-g=FILE'
445
`--generate=FILE'
446 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
447 19 jeremybenn
     `sim.profile' is used.
448
 
449
 
450

451
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Simulator Library,  Prev: Profiling Utility,  Up: Usage
452
 
453
2.3 Memory Profiling Utility
454
============================
455
 
456 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
457
be invoked as a standalone command, or from the Or1ksim CLI.  The
458 19 jeremybenn
general form the standalone command is:
459
 
460
     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
461
 
462 82 jeremybenn
Many of the options have both a short and a long form.  For example
463
`-h' or `--help'.
464 19 jeremybenn
 
465
`-v'
466
`--version'
467
     Print out the version and copyright notice for the Or1ksim memory
468
     profiling utility and exit.
469
 
470
`-h'
471
`--help'
472
     Print out help about the command line options and what they mean.
473
 
474
`-m=M'
475
`--mode=M'
476 82 jeremybenn
     Specify the mode out output.  Permitted options are
477 19 jeremybenn
 
478
    `detailed'
479
    `d'
480 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
481 19 jeremybenn
 
482
    `pretty'
483
    `p'
484
          Pretty printed output.
485
 
486
    `access'
487
    `a'
488
          Memory accesses only.
489
 
490
    `width'
491
    `w'
492
          Access width only.
493
 
494
 
495
`-g=N'
496
`--group=N'
497
     Group 2^n bits of successive addresses together.
498
 
499
`-f=FILE'
500
`--filename=FILE'
501 82 jeremybenn
     The data file to analyse.  If not specified, the default,
502 19 jeremybenn
     `sim.profile' is used.
503
 
504
`FROM'
505
`TO'
506
     FROM and TO are respectively the start and end address of the
507
     region of memory to be analysed.
508
 
509
 
510

511
File: or1ksim.info,  Node: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
512
 
513
2.4 Simulator Library
514
=====================
515
 
516
Or1ksim may be used as a static of dynamic library, `libsim.a' or
517 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
518 19 jeremybenn
should be added to the link command.
519
 
520
The header file `or1ksim.h' contains appropriate declarations of the
521 82 jeremybenn
functions exported by the Or1ksim library.  These are:
522 19 jeremybenn
 
523 93 jeremybenn
 -- `or1ksim.h': int or1ksim_init (const char
524
     *CONFIG_FILE, const char *IMAGE_FILE, void *CLASS_PTR, int
525
     (*UPR)(void *CLASS_PTR, unsigned long int ADDR, unsigned char
526
     MASK[], unsigned char RDATA[], int DATA_LEN), int (*UPW)(void
527
     *CLASS_PTR, unsigned long int ADDR, unsigned char MASK[], unsigned
528
     char WDATA[], int DATA_LEN))
529
 
530 19 jeremybenn
     The initialization function is supplied with the name of a
531
     configuration file, CONFIG_FILE, an executable image, IMAGE_FILE,
532
     a pointer to the calling class, CLASS_PTR (since the library may
533
     be used from C++) and two up-call functions, one for reads, UPR,
534
     and one for writes, UPW.
535
 
536
     *Note Configuration: Configuration, for detailed information on
537
     configuring Or1ksim and the format of the configuration file.
538
 
539
     UPW is called for any write to an address external to the model
540 82 jeremybenn
     (determined by a `generic' section in the configuration file).
541
     UPR is called for any reads to an external address.  The CLASS_PTR
542
     is passed back with these upcalls, allowing the function to
543
     associate the call with the class which originally initialized the
544 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
545
     non-zero otherwise.  At the present time the meaning of non-zero
546
     values is not defined but this may change in the future.
547 19 jeremybenn
 
548 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
549 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
550 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
551
     address, since the upcall function must handle all generic
552
     devices, using the full address for decoding.
553 19 jeremybenn
 
554 93 jeremybenn
     Endianness is not completely transparent, since Or1ksim is
555
     transferring byte vectors, not multi-byte values.
556 19 jeremybenn
 
557 93 jeremybenn
          Caution: This is a change from version 0.3.0. It simplifies
558
          the interface, and makes Or1ksim more consistent with payload
559
          representation in SystemC TLM 2.0.
560 19 jeremybenn
 
561 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
562
          single words (4 bytes), using masks if smaller values are
563
          required.  In this it mimcs the behavior of the WishBone bus.
564
 
565
 
566 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
567
     Run the simulator for the simulated duration specified (in
568
     seconds).
569
 
570
 
571
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
572
     Change the duration of a run specified in an earlier call to
573 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
574 19 jeremybenn
     realizes it needs to change the duration of the run specified in
575
     the call to `or1ksim_run' that has been interrupted by the upcall.
576
 
577
     The time specified is the amount of time that the run must continue
578
     for (i.e the duration from _now_, not the duration from the
579
     original call to `or1ksim_run').
580
 
581
 
582
 -- `or1ksim.h': void or1ksim_set_time_point ()
583 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
584 19 jeremybenn
 
585
 
586
 -- `or1ksim.h': double or1ksim_get_time_period ()
587
     Return the simulated time (in seconds) that has elapsed since the
588
     last call to `or1ksim_set_time_point'.
589
 
590
 
591
 -- `or1ksim.h': int or1ksim_is_le ()
592
     Return 1 (logical true) if the Or1ksim simulation is
593
     little-endian, 0 otherwise.
594
 
595
 
596
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
597 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
598
     specified in the configuration file.
599 19 jeremybenn
 
600
 
601
 -- `or1ksim.h': void or1ksim_interrupt (int I)
602 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
603
     interrupt is then immediately cleared automatically.  A warning
604 19 jeremybenn
     will be generated and the interrupt request ignored if level
605
     sensitive interrupts have been configured with the programmable
606
     interrupt controller (*note Interrupt Configuration: Interrupt
607
     Configuration.).
608
 
609
 
610
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
611 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
612 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
613 82 jeremybenn
     `or1ksim_interrupt_clear'.  A warning will be generated, and the
614 19 jeremybenn
     interrupt request ignored if edge sensitive interrupts have been
615
     configured with the programmable interrupt controller (*note
616
     Interrupt Configuration: Interrupt Configuration.).
617
 
618
 
619
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
620
     Clear a level-triggered interrupt on interrupt line I, which was
621 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
622 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
623
     edge sensitive interrupts have been configured with the
624
     programmable interrupt controller (*note Interrupt Configuration:
625
     Interrupt Configuration.).
626
 
627
 
628 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
629
     Drive a reset sequence through the JTAG interface. Return the
630
     (model) time taken for this action.  Remember that the JTAG has
631
     its own clock, which can be an order of magnitude slower than the
632
     main clock, so even a reset (5 JTAG cycles) could take 50
633
     processor clock cycles to complete.
634
 
635
 
636
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned
637
     char *JREG, int NUM_BITS)
638
 
639
     Shift the supplied register through the JTAG instruction register.
640
     Return the (model) time taken for this action. The register is
641
     supplied as a byte vector, with the least significant bits in the
642
     least significant byte.  If the total number of bits is not an
643
     exact number of bytes, then the odd bits are found in the least
644
     significant end of the highest numbered byte.
645
 
646
     For example a 12-bit register would have bits 0-7 in byte 0 and
647
     bits 11-8 in the least significant 4 bits of byte 1.
648
 
649
 
650
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned
651
     char *JREG, int NUM_BITS)
652
 
653
     Shift the supplied register through the JTAG data register.
654
     Return the (model) time taken for this action. The register is
655
     supplied as a byte vector, with the least significant bits in the
656
     least significant byte.  If the total number of bits is not an
657
     exact number of bytes, then the odd bits are found in the least
658
     significant end of the highest numbered byte.
659
 
660
     For example a 12-bit register would have bits 0-7 in byte 0 and
661
     bits 11-8 in the least significant 4 bits of byte 1.
662
 
663
 
664 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
665
installation directory (as specified with the `--prefix' option to the
666
`configure' script).
667
 
668
For example if the main installation directory is `/opt/or1ksim', the
669 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
670 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
671
(`libsim.so').
672
 
673
To link against the library add the `-lsim' flag when linking and do
674
one of the following:
675
 
676
   * Add the library directory to the `LD_LIBRARY_PATH' environment
677 82 jeremybenn
     variable during execution.  For example:
678 19 jeremybenn
 
679
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
680
 
681
   * Add the library directory to the `LD_RUN_PATH' environment
682 82 jeremybenn
     variable during linking.  For example:
683 19 jeremybenn
 
684
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
685
 
686
   * Use the linker `--rpath' option and specify the library directory
687 82 jeremybenn
     when linking your program.  For example
688 19 jeremybenn
 
689 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
690 19 jeremybenn
 
691
   * Add the library directory to `/etc/ld.so.conf'
692
 
693
 
694

695
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
696
 
697
3 Configuration
698
***************
699
 
700 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
701 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
702 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
703
the default `sim.cfg' is used.  The file is looked for first in the
704 224 jeremybenn
current directory, then in the `$HOME/.or1ksim' directory of the user.
705 19 jeremybenn
 
706
* Menu:
707
 
708
* Configuration File Format::
709
* Simulator Configuration::
710
* Core OpenRISC Configuration::
711
* Peripheral Configuration::
712
 
713

714
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
715
 
716
3.1 Configuration File Format
717
=============================
718
 
719
The configuration file is a plain text file.
720
 
721
* Menu:
722
 
723
* Configuration File Preprocessing::
724
* Configuration File Syntax::
725
 
726

727
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
728
 
729
3.1.1 Configuration File Preprocessing
730
--------------------------------------
731
 
732 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
733 19 jeremybenn
`/*' and `*/').
734
 
735

736
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
737
 
738
3.1.2 Configuration File Syntax
739
-------------------------------
740
 
741
The configuration file is divided into a series of sections, with the
742
general form:
743
 
744
     section SECTION_NAME
745
 
746
       ...
747
 
748
     end
749
 
750
Sections may also have sub-sections within them (currently only the
751
ATA/ATAPI disc interface uses this).
752
 
753
Within a section, or sub-section are a series of parameter assignments,
754
one per line, withe the general form
755
 
756
       PARAMETER = VALUE
757
 
758
Depending on the parameter, the value may be a named value (an
759
enumeration), an integer (specified in any format acceptable in C) or a
760 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
761
mean "true" or "on" and the value "0" to mean "false" or "off".  An
762 19 jeremybenn
example from a memory section shows each of these
763
 
764
     section memory
765
       type    = random
766
       pattern = 0x00
767
       name    = "FLASH"
768
       ...
769
     end
770
 
771
Many parameters are optional and take reasonable default values if not
772 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
773 19 jeremybenn
parameter in `section memory') _must_ be specified.
774
 
775
Subsections are introduced by a keyword, with a parameter value (no `='
776 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
777 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
778
 
779
     section ata
780
       ...
781
       device 0
782
         type    = 1
783
         file = "FILENAME"
784
         ...
785
       enddevice
786
       ...
787
     end
788
 
789
Some sections (for example `section sim') should appear only once.
790
Others (for example `section memory' may appear multiple times.
791
 
792
Sections may be omitted, _unless they contain parameters which are
793 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
794 19 jeremybenn
is optional (for example whether it has a UART), then that
795 82 jeremybenn
functionality will not be provided.  If the section describes a part of
796 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
797
parameters of that section will take their default values.
798
 
799
All optional parts of the functionality are always described by
800
sections including a `enabled' parameter, which can be set to 0 to
801
ensure that functionality is explicitly omitted.
802
 
803
Even if a section is disabled, all its parameters will be read and
804 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
805
the Or1ksim command line (*note Interactive Command Line: Interactive
806 19 jeremybenn
Command Line.).
807
 
808
     Tip: It generally clearer to have sections describing _all_
809
     components, with omitted functionality explicitly indicated by
810
     setting the `enabled' parameter to 0
811
 
812
The following sections describe the various configuration sections and
813
the parameters which may be set in each.
814
 
815

816
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
817
 
818
3.2 Simulator Configuration
819
===========================
820
 
821
* Menu:
822
 
823
* Simulator Behavior::
824
* Verification API Configuration::
825
* CUC Configuration::
826
 
827

828
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
829
 
830
3.2.1 Simulator Behavior
831
------------------------
832
 
833 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
834
appear only once.  The following parameters may be specified.
835 19 jeremybenn
 
836
`verbose = 0|1'
837 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
838 19 jeremybenn
 
839
`debug = 0-9'
840 82 jeremybenn
 
841
     higher the value the greater the number of messages.  Default 0.
842
     Negative values will be treated as 0 (with a warning).  Values
843
     that are too large will be treated as 9 (with a warning).
844 19 jeremybenn
 
845
`profile = 0|1'
846
     If 1 (true) generate a profiling file using the file specified in
847 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
848 19 jeremybenn
 
849
`prof_file = ``FILENAME'''
850 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
851
     Default `sim.profile'.  For backwards compatibility, the
852
     alternative name `prof_fn' is supported for this parameter, but
853
     deprecated.
854 19 jeremybenn
 
855
`mprofile = 0|1'
856
     If 1 (true) generate a memory profiling file using the file
857
     specified in the `mprof_file' parameter or otherwise
858 82 jeremybenn
     `sim.mprofile'.  Default 0.
859 19 jeremybenn
 
860
`mprof_fn = ``FILENAME'''
861
     Specifies the file to be used with the `mprofile' parameter.
862 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
863 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
864
     deprecated.
865
 
866
`history = 0|1'
867 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
868 19 jeremybenn
 
869
          Note: Setting this parameter seriously degrades performance.
870
 
871
          Note: If this execution flow tracking is enabled, then
872
          `dependstats' must be enabled in the CPU configuration
873
          section (*note CPU Configuration: CPU Configuration.).
874
 
875
`exe_log = 0|1'
876 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
877
     file specified in parameter `exe_log_file'.  Default 0.
878 19 jeremybenn
 
879
          Note: Setting this parameter seriously degrades performance.
880
 
881
`exe_log_type = default|hardware|simple|software'
882
     Type of execution log to produce.
883
 
884
    `default'
885 82 jeremybenn
          Produce default output for the execution log.  In the current
886 19 jeremybenn
          implementation this is the equivalent of `hardware'.
887
 
888
    `hardware'
889
          After each instruction execution, log the number of
890
          instructions executed so far, the next instruction to execute
891
          (in hex), the general purpose registers (GPRs), status
892
          register, exception program counter, exception, effective
893
          address register and exception status register.
894
 
895
    `simple'
896
          After each instruction execution, log the number of
897
          instructions executed so far and the next instruction to
898
          execute, symbolically disassembled.
899
 
900
    `software'
901
          After each instruction execution, log the number of
902
          instructions executed so far and the next instruction to
903 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
904 19 jeremybenn
          each operand to the instruction.
905
 
906
 
907 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
908 19 jeremybenn
     insensitive) will be treated as the default with a warning.
909
 
910
          Note: Execution logs can be _very_ big.
911
 
912
`exe_log_start = VALUE'
913 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
914 19 jeremybenn
 
915
`exe_log_end = VALUE'
916 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
917
     once started logging will continue until the simulator exits).
918 19 jeremybenn
 
919
`exe_log_marker = VALUE'
920
     Specifies the number of instructions between printing horizontal
921 82 jeremybenn
     markers.  Default is to produce no markers.
922 19 jeremybenn
 
923
`exe_log_file = FILENAME'
924
     Filename for the execution log filename if `exe_log' is enabled.
925 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
926 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
927
     deprecated.
928
 
929 202 julius
`exe_bin_insn_log = 0|1'
930
     Enable logging of executed instructions to a file in binary
931
     format. This is helpful for off-line dynamic execution analysis.
932
 
933
          Note: Execution logs can be _very_ big. For example, while
934 220 jeremybenn
          booting the Linux kernel, version 2.6.34, a log file 1.2GB in
935
          size was generated.
936 202 julius
 
937
`exe_bin_insn_log_file = FILENAME'
938
     Filename for the binary execution log filename if
939
     `exe_bin_insn_log' is enabled.  Default `exe-insn.bin'.
940
 
941 19 jeremybenn
`clkcycle = VALUE[ps|ns|us|ms]'
942 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
943
     specified, `ps' is assumed.  Default 4000ps (250MHz).
944 19 jeremybenn
 
945
 
946

947
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
948
 
949
3.2.2 Verification API (VAPI) Configuration
950
-------------------------------------------
951
 
952
The Verification API (VAPI) provides a TCP/IP interface to allow
953 82 jeremybenn
components of the simulation to be controlled externally.  *Note
954 19 jeremybenn
Verification API: Verification API, for more details.
955
 
956 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
957
section may appear at most once.  The following parameters may be
958 19 jeremybenn
specified.
959
 
960
`enabled = 0|1'
961
     If 1 (true), verification API is enabled and its server started.
962
     If 0 (the default), it is disabled.
963
 
964
`server_port = VALUE'
965
     When VAPI is enabled, communication will be via TCP/IP on the port
966 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
967 19 jeremybenn
     The default value is 50000.
968
 
969 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
970 19 jeremybenn
          practice suggests users should adopt port values in the
971 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
972 19 jeremybenn
 
973
`log_enabled = 0|1'
974
     If 1 (true), all VAPI requests and sent commands will be logged.
975 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
976 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
977
 
978
          Caution: This can generate a substantial amount of file I/O
979
          and seriously degrade simulator performance.
980
 
981
`hide_device_id = 0|1'
982 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
983
     device ID.  This feature (when set to 1) is provided for backwards
984 19 jeremybenn
     compatibility with an old version of VAPI.
985
 
986
`vapi_log_file = "FILENAME"'
987
     Use `filename' as the file for logged data is logging is enabled
988 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
989 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
990
     supported for this parameter, but deprecated.
991
 
992
 
993

994
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
995
 
996
3.2.3 Custom Unit Compiler (CUC) Configuration
997
----------------------------------------------
998
 
999
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
1000 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
1001
beyond the initial prototype phase.  The configuration parameters are
1002 19 jeremybenn
described here for the record.
1003
 
1004 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
1005
appear at most once.  The following parameters may be specified.
1006 19 jeremybenn
 
1007
`memory_order = none|weak|strong|exact'
1008
     This parameter specifies the memory ordering required:
1009
 
1010
    `memory_order=none'
1011
          Different memory ordering, even if there are dependencies.
1012
          Bursts can be made, width can change.
1013
 
1014 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
1015 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
1016
          change.
1017
 
1018 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
1019 19 jeremybenn
 
1020
          Exactly the same memory ordering and widths.
1021
 
1022
 
1023 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1024 19 jeremybenn
     orderings are ignored with a warning.
1025
 
1026
`calling_convention = 0|1'
1027 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1028 19 jeremybenn
     (the default), they may use other convenitions.
1029
 
1030
`enable_bursts = 0 | 1'
1031 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1032 19 jeremybenn
     not detected.
1033
 
1034
`no_multicycle = 0 | 1'
1035 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1036
     (the default), multicycle logic paths will be generated.
1037 19 jeremybenn
 
1038
`timings_file = "FILENAME"'
1039 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1040
     default value is `"virtex.tim"'.  For backwards compatibility, the
1041 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1042
     deprecated.
1043
 
1044
 
1045

1046
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1047
 
1048
3.3 Configuring the OpenRISC Architectural Components
1049
=====================================================
1050
 
1051
* Menu:
1052
 
1053
* CPU Configuration::
1054
* Memory Configuration::
1055
* Memory Management Configuration::
1056
* Cache Configuration::
1057
* Interrupt Configuration::
1058
* Power Management Configuration::
1059
* Branch Prediction Configuration::
1060
* Debug Interface Configuration::
1061
 
1062

1063
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1064
 
1065
3.3.1 CPU Configuration
1066
-----------------------
1067
 
1068 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1069
appear only once.  At present Or1ksim does not model multi-CPU systems.
1070 19 jeremybenn
The following parameters may be specified.
1071
 
1072
`ver = VALUE'
1073
 
1074
`cfg = VALUE'
1075
 
1076
`rev = VALUE'
1077
     The values are used to form the corresponding fields in the `VR'
1078 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1079 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1080
     and `cfg', 6 bits for `rev').
1081
 
1082
`upr = VALUE'
1083
     Used as the value of the Unit Present Register (UPR) Special
1084 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1085 19 jeremybenn
     i.e.
1086
        * UPR present (0x00000001)
1087
 
1088
        * Data cache present (0x00000002)
1089
 
1090
        * Instruction cache present (0x00000004)
1091
 
1092
        * Data MMY present (0x00000008)
1093
 
1094
        * Instruction MMU present (0x00000010)
1095
 
1096
        * Debug unit present (0x00000040)
1097
 
1098
        * Power management unit present (0x00000100)
1099
 
1100
        * Programmable interrupt controller present (0x00000200)
1101
 
1102
        * Tick timer present (0x00000400)
1103
 
1104
     However, with the exection of the UPR present (0x00000001) and tick
1105
     timer present, the various fields will be modified with the values
1106
     specified in their corresponding configuration sections.
1107
 
1108
`cfgr = VALUE'
1109
     Sets the CPU configuration register (Special Purpose Register 2) to
1110 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1111
     instruction set.  Attempts to set any other value are accepted, but
1112 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1113
 
1114
`sr = VALUE'
1115
     Sets the supervision register Special Purpose Register (SPR 0x11)
1116 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1117 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1118
 
1119 98 jeremybenn
          Note: This is particularly useful when an image is held in
1120
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1121
          so that interrupt vectors are basedf at 0xf0000000, rather
1122
          than 0x0.
1123
 
1124 19 jeremybenn
`superscalar = 0|1'
1125 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1126 19 jeremybenn
     0.
1127
 
1128
     In the current simulator, the only functional effect of superscalar
1129
     mode is to affect the calculation of the number of cycles taken to
1130
     execute an instruction.
1131
 
1132
          Caution: The code for this does not appear to be complete or
1133
          well tested, so users are advised not to use this option.
1134
 
1135
`hazards = 0|1'
1136 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1137
     value is 0.
1138 19 jeremybenn
 
1139
     In the current simulator, the only functional effect is to cause
1140
     logging of hazard waiting information if the CPU is superscalar.
1141
     However nowhere in the simulator is this data actually computed,
1142
     so the net result is probably to have no effect.
1143
 
1144
     if harzards are tracked, current hazards can be displayed using the
1145
     simulator's `r' command.
1146
 
1147
          Caution: The code for this does not appear to be complete or
1148
          well tested, so users are advised not to use this option.
1149
 
1150
`dependstats = 0|1'
1151 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1152
     value 0.
1153 19 jeremybenn
 
1154
     If these values are calculated, the depencies can be displayed
1155
     using the simulator's `stat' command.
1156
 
1157
          Note: This field must be enabled, if execution execution flow
1158
          tracking (field `history') has been requested in the simulator
1159
          configuration section (*note Simulator Behavior: Simulator
1160
          Behavior.).
1161
 
1162
`sbuf_len = VALUE'
1163
     The length of the store buffer is set to VALUE, which must be no
1164 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1165
     warning.  Negative values will be treated as 0 with a warning.
1166
     Use 0 to disable the store buffer.
1167 19 jeremybenn
 
1168
     When the store buffer is active, stores are accumulated and
1169
     committed when I/O is idle.
1170
 
1171 100 julius
`hardfloat = 0|1'
1172
     If 1, hardfloat instructions are enabled. Default value 0.
1173 19 jeremybenn
 
1174 104 jeremybenn
 
1175 19 jeremybenn

1176
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1177
 
1178
3.3.2 Memory Configuration
1179
--------------------------
1180
 
1181 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1182 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1183 19 jeremybenn
 
1184 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1185
     controller. If a memory controller is enabled, then the standard
1186
     OpenRISC C libraries will initialize it to expect 64MB memory
1187
     blocks, and any memory declarations _must_ reflect this.  The
1188
     section describing memory controller configuration describes the
1189
     steps necessary for using smaller or larger memory sections (*note
1190
     Memory Controller Configuration: Memory Controller Configuration.).
1191
 
1192
     If a memory controller is _not_ enabled, then the standard C
1193
     library code will generate memory access errors.  The solution is
1194
     to declare an additional writable memory block, mimicing the memory
1195
     controller's register bank as follows.
1196
 
1197
          section memory
1198
            pattern = 0x00
1199
            type = unknown
1200
            name = "MC shadow"
1201
            baseaddr = 0x93000000
1202
            size     = 0x00000080
1203
            delayr = 2
1204
            delayw = 4
1205
          end
1206
 
1207
 
1208
The following parameters may be specified.
1209
 
1210 19 jeremybenn
`type=random|pattern|unknown|zero'
1211 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1212 19 jeremybenn
     default value is `unknown'.
1213
 
1214
    `random'
1215 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1216 19 jeremybenn
          random generator may be set using the `random_seed' field in
1217
          this section (see below), thus ensuring the same "random"
1218
          values are used each time.
1219
 
1220
    `pattern'
1221
          Set the memory values to be a pattern value, which is set
1222
          using the `pattern' field in this section (see below).
1223
 
1224
    `unknown'
1225 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1226 240 julius
          This option will yield faster initialization of the
1227
          simulator.
1228 19 jeremybenn
 
1229
    `zero'
1230 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1231 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1232
          such.
1233
 
1234
               Note: As a consequence, if the `pattern' field is
1235
               _subsequently_ specified in this section, the value in
1236
               that field will be used instead of zero to initialize
1237
               the memory.
1238
 
1239
 
1240
`random_seed = VALUE'
1241 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1242 19 jeremybenn
     has any effect for memory type `random'.
1243
 
1244
     The default value is -1, which means the seed will be set from a
1245
     call to the `time' function, thus ensuring different random values
1246 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1247 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1248
     values used in any particular run.
1249
 
1250
`pattern = VALUE'
1251 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1252
     default value is 0.  This only has any effect for memory type
1253
     `pattern'.  The least significant 8 bits of this value is used to
1254
     initialize each byte.  More than 8 bits can be specified, but will
1255 19 jeremybenn
     ignored with a warning.
1256
 
1257
          Tip: The default value, is equivalent to setting the memory
1258 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1259 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1260
          and not specifying a value for `pattern'.
1261
 
1262
`baseaddr = VALUE'
1263 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1264 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1265
     The default value is 0.
1266
 
1267
`size = VALUE'
1268 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1269
     be a multiple of 4 (i.e.  word aligned).  The default value is
1270
     1024.
1271 19 jeremybenn
 
1272
          Note: When allocating memory, the simulator will allocate the
1273
          nearest 2^n bytes greater than or equal to VALUE, and will not
1274
          notice memory misses in any part of the memory between VALUE
1275
          and the amount allocated.
1276
 
1277
          As a consequence users are strongly recommended to specify
1278 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1279 19 jeremybenn
          amount of memory is required, it should be specified as
1280
          separate, contiguous blocks, each of which is a power of 2 in
1281
          size.
1282
 
1283
`name = "TEXT"'
1284 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1285
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1286 19 jeremybenn
     `"anonymous memory block"'.
1287
 
1288
          Note: It is not clear that this information is currently ever
1289 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1290 19 jeremybenn
          command of the simulator ignores it.
1291
 
1292
`ce = VALUE'
1293 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1294 19 jeremybenn
     instance should have a unique chip enable index, which should be
1295 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1296 19 jeremybenn
     controller when identifying different memory instances.
1297
 
1298 98 jeremybenn
     There is no requirement to set  `ce' if a memory controller is not
1299
     enabled. The default value is -1 (invalid).
1300 19 jeremybenn
 
1301
`mc = VALUE'
1302 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1303 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1304
     for a memory controller (*note Memory Controller Configuration:
1305
     Memory Controller Configuration.).
1306
 
1307 98 jeremybenn
     There is no requirement to set  `mc' if a memory controller is not
1308
     enabled. Default value is 0, which is also the default value of a
1309
     memory controller `index' field.  This is suitable therefore for
1310
     designs with just one memory controller.
1311 19 jeremybenn
 
1312
`delayr = VALUE'
1313 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1314
     memory does not support reading.  Default value 1.  The simulator
1315 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1316
     count when reading from main memory.
1317
 
1318
`delayw = VALUE'
1319 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1320
     memory does not support writing.  Default value 1.  The simulator
1321 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1322
     count when writing to main memory.
1323
 
1324
`log = "FILE"'
1325
     If specified, `file' names a file for all memory accesses to be
1326 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1327 19 jeremybenn
     that the memory is not logged.
1328
 
1329
 
1330

1331
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1332
 
1333
3.3.3 Memory Management Configuration
1334
-------------------------------------
1335
 
1336
Memory Management Unit (MMU) configuration is described in `section
1337
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1338 82 jeremybenn
Each section should appear at most once.  The following parameters may
1339 19 jeremybenn
be specified.
1340
 
1341
`enabled = 0|1'
1342
     If 1 (true), the data or instruction (as appropriate) MMU is
1343 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1344 19 jeremybenn
 
1345
`nsets = VALUE'
1346
     Sets the number of data or instruction (as appropriate) TLB sets to
1347 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1348
     which do not fit these criteria are ignored with a warning.  The
1349 19 jeremybenn
     default value is 1.
1350
 
1351
`nways = VALUE'
1352
     Sets the number of data or instruction (as appropriate) TLB ways to
1353 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1354
     this range are ignored with a warning.  The default value is 1.
1355 19 jeremybenn
 
1356
`pagesize = VALUE'
1357
     The data or instruction (as appropriate) MMU page size is set to
1358 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1359
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1360 19 jeremybenn
 
1361
`entrysize = VALUE'
1362
     The data or instruction (as appropriate) MMU entry size is set to
1363 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1364
     of 2 are ignored with a warning.  The default value is 1.
1365 19 jeremybenn
 
1366
          Note: Or1ksim does not appear to use the `entrysize' parameter
1367 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1368 19 jeremybenn
          not seem to matter.
1369
 
1370
`ustates = VALUE'
1371
     The number of instruction usage states for the data or instruction
1372
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1373 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1374 19 jeremybenn
     value is 2.
1375
 
1376
          Note: Or1ksim does not appear to use the `ustates' parameter
1377 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1378 19 jeremybenn
          not seem to matter.
1379
 
1380
`hitdelay = VALUE'
1381
     Set the number of cycles a data or instruction (as appropriate) MMU
1382 82 jeremybenn
     hit costs.  Default value 1.
1383 19 jeremybenn
 
1384
`missdelay = VALUE'
1385
     Set the number of cycles a data or instruction (as appropriate) MMU
1386 82 jeremybenn
     miss costs.  Default value 1.
1387 19 jeremybenn
 
1388
 
1389

1390
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1391
 
1392
3.3.4 Cache Configuration
1393
-------------------------
1394
 
1395
Cache configuration is described in `section dc' (for the data cache)
1396 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1397
appear at most once.  The following parameters may be specified.
1398 19 jeremybenn
 
1399
`enabled = 0|1'
1400
     If 1 (true), the data or instruction (as appropriate) cache is
1401 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1402 19 jeremybenn
 
1403
`nsets = VALUE'
1404
     Sets the number of data or instruction (as appropriate) cache sets
1405
     to VALUE, which must be a power of two, not exceeding
1406
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1407 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1408
     both defined in the code to be 1024).  The default value is 1.
1409 19 jeremybenn
 
1410
`nways = VALUE'
1411
     Sets the number of data or instruction (as appropriate) cache ways
1412
     to VALUE, which must be a power of two, not exceeding
1413
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1414 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1415
     both defined in the code to be 32).  The default value is 1.
1416 19 jeremybenn
 
1417
`blocksize = VALUE'
1418
     The data or instruction (as appropriate) cache block size is set to
1419 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1420 19 jeremybenn
 
1421
`ustates = VALUE'
1422
     The number of instruction usage states for the data or instruction
1423
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1424
     The default value is 2.
1425
 
1426
`hitdelay = VALUE'
1427 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1428
     cache hit costs.  Default value 1.
1429 19 jeremybenn
 
1430
`missdelay = VALUE'
1431 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1432
     cache miss costs.  Default value 1.
1433 19 jeremybenn
 
1434
`load_hitdelay = VALUE'
1435 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1436
     costs.  Default value 2.
1437 19 jeremybenn
 
1438
`load_missdelay = VALUE'
1439 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1440
     miss costs.  Default value 2.
1441 19 jeremybenn
 
1442
`store_hitdelay = VALUE'
1443 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1444
     costs.  Default value 0.
1445 19 jeremybenn
 
1446
`store_missdelay = VALUE'
1447 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1448
     miss costs.  Default value 0.
1449 19 jeremybenn
 
1450
 
1451

1452
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1453
 
1454
3.3.5 Interrupt Configuration
1455
-----------------------------
1456
 
1457
Programmable Interrupt Controller (PIC) configuration is described in
1458 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1459
mechanism for handling multiple interrupt controllers.  The following
1460 19 jeremybenn
parameters may be specified.
1461
 
1462
`enabled = 0|1'
1463 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1464
 
1465 19 jeremybenn
 
1466
`edge_trigger = 0|1'
1467
     If 1 (true, the default), the programmable interrupt controller is
1468 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1469 19 jeremybenn
 
1470
 
1471

1472
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1473
 
1474
3.3.6 Power Management Configuration
1475
------------------------------------
1476
 
1477 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1478 19 jeremybenn
(which only happens when the power management unit is enabled) of
1479
setting the different bits in the power management Special Purpose
1480
Register (PMR, SPR 0x4000) is
1481
 
1482
`SDF (bit mask 0x0000000f)'
1483
     No effect - these bits are ignored
1484
 
1485
`DME (bit mask 0x00000010)'
1486
`SME (bit mask 0x00000020)'
1487
     Both these bits cause the processor to stop executing
1488 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1489 19 jeremybenn
     VAPI etc) carry on as normal.
1490
 
1491
`DCGE (bit mask 0x00000004)'
1492
     No effect - this bit is ignored
1493
 
1494
`SUME (bit mask 0x00000008)'
1495
     Enabling this bit causes a message to be printed, advising that the
1496
     processor is suspending and the simulator exits.
1497
 
1498
 
1499
On reset all bits are cleared.
1500
 
1501 82 jeremybenn
Power management configuration is described in `section pm'.  This
1502
section may appear at most once.  The following parameter may be
1503 19 jeremybenn
specified.
1504
 
1505
`enabled = 0|1'
1506 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1507
     is disabled.
1508 19 jeremybenn
 
1509
 
1510

1511
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1512
 
1513
3.3.7 Branch Prediction Configuration
1514
-------------------------------------
1515
 
1516
From examining the code base, it seems the branch prediction function
1517 82 jeremybenn
is not fully implemented.  At present the functionality seems
1518
restricted to collection of statistics.
1519 19 jeremybenn
 
1520 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1521
section may appear at most once.  The following parameters may be
1522 19 jeremybenn
specified.
1523
 
1524
`enabled = 0|1'
1525 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1526 19 jeremybenn
     is disabled.
1527
 
1528
`btic = 0|1'
1529
     If 1 (true), the branch target instruction cache model is enabled.
1530
     If 0 (the default), it is disabled.
1531
 
1532
`sbp_bf_fwd = 0|1'
1533 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1534 19 jeremybenn
 
1535
     instruction.
1536
 
1537
`sbp_bnf_fwd = 0|1'
1538 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1539
     If 0 (the default), do not use forward prediction for this
1540 19 jeremybenn
     instruction.
1541
 
1542
`hitdelay = VALUE'
1543 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1544 19 jeremybenn
     value 0.
1545
 
1546
`missdelay = VALUE'
1547 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1548 19 jeremybenn
     value 0.
1549
 
1550
 
1551

1552
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1553
 
1554
3.3.8 Debug Interface Configuration
1555
-----------------------------------
1556
 
1557
The debug unit and debug interface configuration is described in
1558 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1559 19 jeremybenn
parameters may be specified.
1560
 
1561
`enabled = 0|1'
1562 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1563 19 jeremybenn
     disabled.
1564
 
1565
          Note: This enables the functionality of the debug unit (its
1566 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1567
          external interface to the debug unit.  For that, see
1568 235 jeremybenn
          `rsp_enabled' below.
1569 19 jeremybenn
 
1570
`rsp_enabled = 0|1'
1571
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1572
     provding an interface to an external GNU debugger, using the port
1573
     specified in the `rsp_port' field (see below), or the
1574 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1575 19 jeremybenn
     not started, and no external interface is provided.
1576
 
1577
     For more detailed information on the interface to the GNU Debugger
1578
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1579
     Practical Experience with the OpenRISC 1000 Architecture', by
1580
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1581
 
1582
`rsp_port = VALUE'
1583
     VALUE specifies the port to be used for the GDB "Remote Serial
1584 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1585
     51000.  If the value 0 is specified, Or1ksim will instead look for
1586 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1587
 
1588
          Tip: There is no registered port for Or1ksim "Remote Serial
1589 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1590
          users should adopt port values in the "Dynamic" or "Private"
1591
          port range, i.e.  49152-65535.
1592 19 jeremybenn
 
1593
`vapi_id = VALUE'
1594
     VALUE specifies the value of the Verification API (VAPI) base
1595 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1596 19 jeremybenn
     Verification API, for more details.
1597
 
1598
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1599
     JTAG protocol transactions will be logged to the VAPI log file, if
1600 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
1601
     the debug unit.  No VAPI commands are sent, nor requests handled.
1602 19 jeremybenn
 
1603
 
1604

1605
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
1606
 
1607
3.4 Configuring Memory Mapped Peripherals
1608
=========================================
1609
 
1610 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1611 19 jeremybenn
(unlike other components) by default they are enabled.
1612
 
1613
* Menu:
1614
 
1615
* Memory Controller Configuration::
1616
* UART Configuration::
1617
* DMA Configuration::
1618
* Ethernet Configuration::
1619
* GPIO Configuration::
1620
* Display Interface Configuration::
1621
* Frame Buffer Configuration::
1622
* Keyboard Configuration::
1623
* Disc Interface Configuration::
1624
* Generic Peripheral Configuration::
1625
 
1626

1627
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
1628
 
1629
3.4.1 Memory Controller Configuration
1630
-------------------------------------
1631
 
1632
The memory controller used in Or1ksim is the component implemented at
1633 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
1634 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
1635 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1636
memory mapped component, which resides on the main OpenRISC Wishbone
1637
data bus.
1638 19 jeremybenn
 
1639 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
1640 19 jeremybenn
section may appear multiple times, specifying multiple memory
1641 98 jeremybenn
controllers.
1642 19 jeremybenn
 
1643 98 jeremybenn
     Caution: The standard OpenRISC C libraries will initialize the
1644
     memory controller to expect 64MB memory blocks, and any memory
1645
     declarations _must_ reflect this.
1646
 
1647
     If smaller memory blocks are declared with a memory controller,
1648
     then sufficient memory will not be allocated by Or1ksim, but out of
1649
     range memory accesses will not be trapped. For example declaring a
1650
     memory section from 0-4MB with a memory controller enabled would
1651
     mean that accesses between 4MB and 64MB would be permitted, but
1652
     having no allocated memory would likely cause a segmentation fault.
1653
 
1654
     If the user is determined to use smaller memories with the memory
1655
     controller, then custom initialization code must be provided, to
1656
     ensure the memory controller traps out-of-memory accesses.
1657
 
1658
The following parameters may be specified.
1659
 
1660 19 jeremybenn
`enabled = 0|1'
1661 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
1662
     0, it is disabled.
1663 19 jeremybenn
 
1664
          Note: The memory controller can effectively also be disabled
1665
          by setting an appropriate power on control register value
1666 82 jeremybenn
          (see below).  However this should only be used if it is
1667 19 jeremybenn
          desired to specifically model this behavior of the memory
1668
          controller, not as a way of disabling the memory controller
1669
          in general.
1670
 
1671
`baseaddr = VALUE'
1672
     Set the base address of the memory controller's memory mapped
1673 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
1674 19 jeremybenn
     sensible value.
1675
 
1676
     The memory controller has a 7 bit address bus, with a total of 19
1677
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1678
     addresses 0x50 through 0x7c are not used).
1679
 
1680
`poc = VALUE'
1681
     Specifies the value of the power on control register, The least
1682
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
1683
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
1684
     the type of memory connected (use 0 for a disabled interface, 1
1685
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
1686
     devices).
1687
 
1688
     If other bits are specified, they are ignored with a warning.
1689
 
1690
          Caution: The default value, 0, corresponds to a disabled
1691
          8-bit bus, and is likely not the most suitable value
1692
 
1693
`index = VALUE'
1694
     Specify the index of this memory controller amongst all the memory
1695 82 jeremybenn
     controllers.  This value should be unique for each memory
1696 19 jeremybenn
     controller, and is used to associate specific memories with the
1697
     controller, through the `mc' field in the `section memory'
1698
     configuration (*note Memory Configuration: Memory Configuration.).
1699
 
1700
     The default value, 0, is suitable when there is only one memory
1701
     controller.
1702
 
1703
 
1704

1705
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
1706
 
1707
3.4.2 UART Configuration
1708
------------------------
1709
 
1710
The UART implemented in Or1ksim follows the specification of the
1711 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
1712 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
1713
 
1714
The component provides a number of interfaces to emulate the behavior
1715
of an external terminal connected to the UART.
1716
 
1717 82 jeremybenn
UART configuration is described in `section uart'.  This section may
1718
appear multiple times, specifying multiple UARTs.  The following
1719 19 jeremybenn
parameters may be specified.
1720
 
1721
`enabled = 0|1'
1722 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
1723 19 jeremybenn
     disabled.
1724
 
1725
`baseaddr = VALUE'
1726
     Set the base address of the UART's memory mapped registers to
1727 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1728 19 jeremybenn
 
1729
     The UART has a 3 bit address bus, with a total of 8 8-bit
1730
     registers, at addresses 0x0 through 0x7.
1731
 
1732
`channel = "TYPE:ARGS"'
1733
     Specify the channel representing the terminal connected to the UART
1734
     Rx & Tx pins.
1735
 
1736
    `channel="file:`rxfile',`txfile'"'
1737
          Read input characters from the file `rxfile' and write output
1738
          characters to the file `txfile' (which will be created if
1739
          required).
1740
 
1741
    `channel="xterm:ARGS"'
1742
          Create an xterm on startup, write UART Tx traffic to the
1743
          xterm and take Rx traffic from the keyboard when the xterm
1744 82 jeremybenn
          window is selected.  Additional arguments to the xterm
1745
          command (for example specifying window size may be specified
1746
          in ARGS, or this may be left blank.
1747 19 jeremybenn
 
1748
    `channel="tcp:VALUE"'
1749
          Open the TCP/IP port specified by VALUE and read and write
1750
          UART traffic from and to it.
1751
 
1752
          Typically a telnet session is connected to the other end of
1753
          this port.
1754
 
1755
               Tip: There is no registered port for Or1ksim telnet UART
1756 82 jeremybenn
               connection.  Priviledged access is required to read
1757 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
1758 240 julius
               Instead users should use port values in the "Dynamic"
1759
               or "Private" port range, i.e.  49152-65535.
1760 19 jeremybenn
 
1761
    `channel="fd:`rxfd',`txfd'"'
1762
          Read and write characters from and to the existing open
1763
          numerical file descriptors, file `rxfd' and `txfd'.
1764
 
1765
    `channel="tty:device=/dev/ttyS0,baud=9600"'
1766
          Read and write characters from and to a physical serial port.
1767 240 julius
          The precise device (shown here as `/dev/ttyS0') may vary
1768
          from machine to machine.
1769 19 jeremybenn
 
1770
 
1771
     The default value for this field is `"xterm:"'.
1772
 
1773
`irq = VALUE'
1774 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
1775 19 jeremybenn
 
1776
`16550 = 0|1'
1777 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
1778
     default), it has the functionality of a 16450.  The principal
1779 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
1780
 
1781
`jitter = VALUE'
1782
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
1783 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
1784 19 jeremybenn
 
1785
          Note: This functionality has yet to be implemented, so this
1786
          parameter has no effect.
1787
 
1788
`vapi_id = VALUE'
1789
     VALUE specifies the value of the Verification API (VAPI) base
1790 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
1791 19 jeremybenn
     Verification API, for more details, which details the use of the
1792
     VAPI with the UART.
1793
 
1794
 
1795

1796
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
1797
 
1798
3.4.3 DMA Configuration
1799
-----------------------
1800
 
1801
The DMA controller used in Or1ksim is the component implemented at
1802 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
1803 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
1804 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1805
memory mapped component, which resides on the main OpenRISC Wishbone
1806
data bus.  The present implementation is incomplete, intended only to
1807
support the Ethernet interface (*note Ethernet Configuration::),
1808
although the Ethernet interface is not yet completed.
1809 19 jeremybenn
 
1810 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
1811
appear multiple times, specifying multiple DMA controllers.  The
1812 19 jeremybenn
following parameters may be specified.
1813
 
1814
`enabled = 0|1'
1815 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
1816
     it is disabled.
1817 19 jeremybenn
 
1818
`baseaddr = VALUE'
1819
     Set the base address of the DMA's memory mapped registers to
1820 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1821 19 jeremybenn
 
1822
     The DMA controller has a 10 bit address bus, with a total of 253
1823 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
1824
     0x010 control the overall behavior of the DMA controller.  There
1825
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
1826
     channels available.  Addresses 0x014 through 0x01c are not used.
1827 19 jeremybenn
 
1828
`irq = VALUE'
1829 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
1830 19 jeremybenn
     0.
1831
 
1832
`vapi_id = VALUE'
1833
     VALUE specifies the value of the Verification API (VAPI) base
1834 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
1835 19 jeremybenn
     API: Verification API, for more details, which details the use of
1836
     the VAPI with the DMA controller.
1837
 
1838
 
1839

1840
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
1841
 
1842
3.4.4 Ethernet Configuration
1843
----------------------------
1844
 
1845
The Ethernet MAC used in Or1ksim is the component implemented at
1846 98 jeremybenn
OpenCores, and found in the top level SVN directory, `ethmac'.  It also
1847
forms part of the OpenRISC SoC, ORPSoC.  It is described in the
1848 19 jeremybenn
document `Ethernet IP Core Specification' by Igor Mohor, which can be
1849 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1850
which resides on the main OpenRISC Wishbone data bus.
1851 19 jeremybenn
 
1852 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
1853
section may appear multiple times, specifying multiple Ethernet
1854
interfaces.  The following parameters may be specified.
1855 19 jeremybenn
 
1856
`enabled = 0|1'
1857 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
1858
     is disabled.
1859 19 jeremybenn
 
1860
`baseaddr = VALUE'
1861
     Set the base address of the MAC's memory mapped registers to
1862 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1863 19 jeremybenn
 
1864
     The Ethernet MAC has a 7-bit address bus, with a total of 21
1865 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
1866 19 jeremybenn
 
1867
          Note: The Ethernet specification describes a Tx control
1868 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
1869
          is not implemented in the Or1ksim model.
1870 19 jeremybenn
 
1871
`dma = VALUE'
1872
     VALUE specifies the DMA controller with which this Ethernet is
1873 82 jeremybenn
     associated.  The default value is 0.
1874 19 jeremybenn
 
1875
          Note: Support for external DMA is not provided in the current
1876 82 jeremybenn
          implementation, and this value is ignored.  In any case there
1877 19 jeremybenn
          is no equivalent field to which this can be matched in the
1878
          current DMA component implementation (*note DMA
1879
          Configuration: DMA Configuration.).
1880
 
1881
`irq = VALUE'
1882 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
1883 19 jeremybenn
 
1884
`rtx_type = 0|1'
1885
     If 1 (true) use a socket interface to the Ethernet (see parameter
1886 82 jeremybenn
     `sockif' below).  If 0 (the default), use a file interface,
1887
     reading and writing from and to the files specified in the
1888
     `rxfile' and `txfile' parameters (see below).
1889 19 jeremybenn
 
1890
          Note: By default the socket interface is not provided in
1891 82 jeremybenn
          Or1ksim.  If it is required, this must be requested when
1892 19 jeremybenn
          configuring, by use of the `--enable-ethphy' option to
1893
          `configure'.
1894
 
1895
               configure --target=or32-uclinux --enable-ethphy ...
1896
 
1897
`rx_channel = RXVALUE'
1898
`tx_channel = TXVALUE'
1899
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
1900 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
1901 19 jeremybenn
 
1902
          Note: As noted above, support for external DMA is not
1903
          provided in the current implementation, and so these values
1904
          are ignored.
1905
 
1906
`rxfile = "RXFILE"'
1907
`txfile = "TXFILE"'
1908
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
1909
     as input and TXFILE specifies the fie to use as output.
1910
 
1911 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
1912
     packet length (32 bits), followed by that many bytes of data.
1913
     Once the input file is empty, the Ethernet MAC behaves as though
1914
     there were no data on the Ethernet.  The default values of these
1915 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
1916
 
1917 82 jeremybenn
     The input file must exist and be readable.  The output file must be
1918
     writable and will be created if necessary.  If either of these
1919 19 jeremybenn
     conditions is not met, a warning will be given.
1920
 
1921
`sockif = "SERVICE"'
1922
     When `rtx_type' is 1 (see above), SERVICE specifies the service to
1923 82 jeremybenn
     use for communication.  This may be TCP/IP or UDP/IP.  The default
1924 19 jeremybenn
     value of this parameter is `"or1ksim_eth"'.
1925
 
1926
`vapi_id = VALUE'
1927
     VALUE specifies the value of the Verification API (VAPI) base
1928 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
1929 19 jeremybenn
     Verification API, for more details, which details the use of the
1930
     VAPI with the DMA controller.
1931
 
1932
 
1933

1934
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
1935
 
1936
3.4.5 GPIO Configuration
1937
------------------------
1938
 
1939
The GPIO used in Or1ksim is the component implemented at OpenCores, and
1940 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
1941 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
1942 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
1943 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
1944
 
1945 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
1946
appear multiple times, specifying multiple GPIO devices.  The following
1947 19 jeremybenn
parameters may be specified.
1948
 
1949
`enabled = 0|1'
1950 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
1951 19 jeremybenn
     disabled.
1952
 
1953
`baseaddr = VALUE'
1954
     Set the base address of the GPIO's memory mapped registers to
1955 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1956 19 jeremybenn
 
1957
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
1958
     registers, although the number of bits that are actively used
1959 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
1960 19 jeremybenn
 
1961
`irq = VALUE'
1962 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
1963 19 jeremybenn
 
1964
`vapi_id = VALUE'
1965
     VALUE specifies the value of the Verification API (VAPI) base
1966 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
1967 19 jeremybenn
     Verification API, for more details, which details the use of the
1968 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
1969 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
1970
     but deprecated.
1971
 
1972
 
1973

1974
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
1975
 
1976
3.4.6 Display Interface Configuration
1977
-------------------------------------
1978
 
1979
Or1ksim models a VGA interface to an external monitor.  The VGA
1980
controller used in Or1ksim is the component implemented at OpenCores,
1981 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
1982 82 jeremybenn
for the optional hardware cursors.  It is described in the document
1983 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
1984 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1985
which resides on the main OpenRISC Wishbone data bus.
1986 19 jeremybenn
 
1987
The current implementation provides only functionality to dump the
1988
screen to a file at intervals.
1989
 
1990 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
1991 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
1992
The following parameters may be specified.
1993
 
1994
`enabled = 0|1'
1995 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
1996 19 jeremybenn
     disabled.
1997
 
1998
`baseaddr = VALUE'
1999
     Set the base address of the VGA controller's memory mapped
2000 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2001 19 jeremybenn
     sensible value.
2002
 
2003
     The VGA controller has a 12-bit address bus, with 7 32-bit
2004
     registers, at addresses 0x000 through 0x018, and two color lookup
2005 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2006 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2007
     are not used.
2008
 
2009
`irq = VALUE'
2010 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2011 19 jeremybenn
     0.
2012
 
2013
`refresh_rate = VALUE'
2014 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2015 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2016
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2017
     50 times per simulated second.
2018
 
2019
`txfile = "FILE"'
2020
     FILE specifies the base of the filename for screen dumps.
2021
     Successive screen dumps will be in BMP format, in files with the
2022
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2023 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2024 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2025
     supported for this parameter, but deprecated.
2026
 
2027
 
2028

2029
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2030
 
2031
3.4.7 Frame Buffer Configuration
2032
--------------------------------
2033
 
2034 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2035 19 jeremybenn
     configuration fields are described here, but the component should
2036 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2037 19 jeremybenn
     to make screen dumps to file.
2038
 
2039 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2040
may appear multiple times, specifying multiple frame buffers.  The
2041 19 jeremybenn
following parameters may be specified.
2042
 
2043
`enabled = 0|1'
2044 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2045 19 jeremybenn
     is disabled.
2046
 
2047
`baseaddr = VALUE'
2048
     Set the base address of the frame buffer's memory mapped registers
2049 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2050
     value.
2051 19 jeremybenn
 
2052
     The frame buffer has an 121-bit address bus, with 4 32-bit
2053
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2054 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2055 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2056
 
2057
`refresh_rate = VALUE'
2058 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2059 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2060
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2061
     50 times per simulated second.
2062
 
2063
`txfile = "FILE"'
2064
     FILE specifies the base of the filename for screen dumps.
2065
     Successive screen dumps will be in BMP format, in files with the
2066
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2067 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2068 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2069
     supported for this parameter, but deprecated.
2070
 
2071
 
2072

2073
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2074
 
2075
3.4.8 Keyboard Configuration (PS2)
2076
----------------------------------
2077
 
2078 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2079 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2080 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2081
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2082 19 jeremybenn
standard, this is presumably what is expected with this device.
2083
 
2084
The implementation only provides for keyboard support, which is
2085 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2086 19 jeremybenn
 
2087
     Caution: A standard i8042 device has two registers at addresses
2088 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2089
     suggests that the Or1ksim component places these registers at
2090
     addresses 0x00 and 0x04.
2091 19 jeremybenn
 
2092
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2093
     implements the i8042 device driver, anticipating these registers
2094 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2095 19 jeremybenn
     code will work.
2096
 
2097
     This component should be used with caution.
2098
 
2099 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2100
appear multiple times, specifying multiple keyboard interfaces.  The
2101 19 jeremybenn
following parameters may be specified.
2102
 
2103
`enabled = 0|1'
2104 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2105 19 jeremybenn
     disabled.
2106
 
2107
`baseaddr = VALUE'
2108
     Set the base address of the keyboard's memory mapped registers to
2109 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2110 19 jeremybenn
 
2111
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2112
     registers, at addresses 0x000 and 0x004.
2113
 
2114
          Caution: As noted above, a standard Intel 8042 interface
2115
          would expect to find these registers at locations 0x60 and
2116
          0x64, thus requiring at least a 7-bit bus.
2117
 
2118
`irq = VALUE'
2119 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2120 19 jeremybenn
     value 0.
2121
 
2122
`rxfile = "FILE"'
2123
     `file' specifies a file containing raw key stroke data, which
2124 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2125 19 jeremybenn
     `"kbd_in"'.
2126
 
2127
 
2128

2129
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2130
 
2131
3.4.9 Disc Interface Configuration
2132
----------------------------------
2133
 
2134
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2135
IDE Controller) component implemented at OpenCores, and found in the
2136 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2137 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2138 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2139
which resides on the main OpenRISC Wishbone data bus.
2140 19 jeremybenn
 
2141 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2142
may appear multiple times, specifying multiple disc controllers.  The
2143 19 jeremybenn
following parameters may be specified.
2144
 
2145
`enabled = 0|1'
2146 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2147 19 jeremybenn
     0, it is disabled.
2148
 
2149
`baseaddr = VALUE'
2150
     Set the base address of the ATA/ATAPI interface's memory mapped
2151 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2152 19 jeremybenn
     sensible value.
2153
 
2154
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2155 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2156
     ATA/ATAPI interface selected (see `dev_id' below), not all
2157
     registers will be available.
2158 19 jeremybenn
 
2159
`irq = VALUE'
2160 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2161 19 jeremybenn
     value 0.
2162
 
2163
`dev_id = 1|2|3'
2164
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2165 82 jeremybenn
     interface to model.  The default value is 1.
2166 19 jeremybenn
 
2167
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2168
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2169
     registers and the `RXD'/`TXD' registers.
2170
 
2171
`rev = VALUE'
2172
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2173 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2174
     be in the range 0-15.  Larger values are truncated with a warning.
2175 240 julius
     This only affects the reset value of the `STAT' register, where
2176
     it forms bits 24-27.
2177 19 jeremybenn
 
2178
`pio_mode0_t1 = VALUE'
2179
`pio_mode0_t2 = VALUE'
2180
`pio_mode0_t4 = VALUE'
2181
`pio_mode0_teoc = VALUE'
2182
     These parameters specify the timings for use with Programmed
2183 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2184 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2185 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2186 19 jeremybenn
     they do, they will be ignored with a warning.
2187
 
2188
     See the ATA/ATAPI-5 specification for explanations of each of these
2189 82 jeremybenn
     timing parameters.  The default values are:
2190 19 jeremybenn
 
2191
          pio_mode0_t1   =  6
2192
          pio_mode0_t2   = 28
2193
          pio_mode0_t4   =  2
2194
          pio_mode0_teoc = 23
2195
 
2196
`dma_mode0_tm = VALUE'
2197
`dma_mode0_td = VALUE'
2198
`dma_mode0_teoc = VALUE'
2199
     These parameters specify the timings for use with DMA transfers.
2200
     They are specified as the number of clock cycles - 2, rounded up
2201
     to the next highest integer, or zero if that would be negative.
2202 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2203
     ignored with a warning.
2204 19 jeremybenn
 
2205
     See the ATA/ATAPI-5 specification for explanations of each of these
2206 82 jeremybenn
     timing parameters.  The default values are:
2207 19 jeremybenn
 
2208
          dma_mode0_tm   =  4
2209
          dma_mode0_td   = 21
2210
          dma_mode0_teoc = 21
2211
 
2212
 
2213
3.4.9.1 ATA/ATAPI Device Configuration
2214
......................................
2215
 
2216 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2217 19 jeremybenn
device subsection is introduced by
2218
 
2219
     device VALUE
2220
 
2221 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2222
ends with `enddevice'.  Note that if the same device number is
2223
specified more than once, the previous values will be overwritten.
2224
Within the `device' subsection, the following parameters may appear:
2225 19 jeremybenn
 
2226
`type = VALUE'
2227
     VALUEspecifies the type of device: 0 (the default) for "not
2228
     connected", 1 for hard disk simulated in a file and 2 for local
2229
     system hard disk.
2230
 
2231
`file = "FILENAME"'
2232
     `filename' specifies the file to be used for a simulated ATA
2233 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2234 19 jeremybenn
     `"ata-FileN"', where N is the device number.
2235
 
2236
`size = VALUE'
2237
     VALUE specifies the size of a simulated ATA device if the file
2238 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2239 19 jeremybenn
 
2240
`packet = 0|1'
2241 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2242 19 jeremybenn
     default), do not implement the PACKET command feature set.
2243
 
2244
`firmware = "STR"'
2245
     Firmware to report in response to the "Identify Device" command.
2246
     Default `"02207031"'.
2247
 
2248
`heads = VALUE'
2249 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2250 19 jeremybenn
     heads.
2251
 
2252
`sectors = VALUE'
2253 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2254 19 jeremybenn
 
2255
`mwdma = 0|1|2|-1'
2256 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2257 19 jeremybenn
     disable.
2258
 
2259
`pio = 0|1|2|3|4'
2260 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2261 19 jeremybenn
 
2262
 
2263

2264
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2265
 
2266
3.4.10 Generic Peripheral Configuration
2267
---------------------------------------
2268
 
2269
When used as a library (*note Simulator Library: Simulator Library.),
2270
Or1ksim makes provision for any additional peripheral to be implemented
2271 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2272
generates "upcall"s to an external handler.  This interface can support
2273 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2274
for OSCI SystemC (see `http://www.systemc.org').
2275
 
2276
Generic peripheral configuration is described in `section generic'.
2277
This section may appear multiple times, specifying multiple external
2278 82 jeremybenn
peripherals.  The following parameters may be specified.
2279 19 jeremybenn
 
2280
`enabled = 0|1'
2281 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2282 19 jeremybenn
     0, it is disabled.
2283
 
2284
`baseaddr = VALUE'
2285
     Set the base address of the generic peripheral's memory mapped
2286 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2287 19 jeremybenn
     sensible value.
2288
 
2289
     The size of the memory mapped register space is controlled by the
2290
     `size' paramter, described below.
2291
 
2292
`size = VALUE'
2293
     Set the size of the generic peripheral's memory mapped register
2294 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2295 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2296
     parameter `baseaddr' (see above) will be directed to the external
2297
     interface.
2298
 
2299 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2300
     value is zero.  If VALUE is not an exact power of two, accesses to
2301 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2302
     generate a warning, and have no effect (reads will return zero).
2303
 
2304
`name = "STR"'
2305 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2306 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2307 82 jeremybenn
     reporting its status.  The default value is
2308 19 jeremybenn
     `"anonymous external peripheral"'.
2309
 
2310
`byte_enabled = 0|1'
2311
`hw_enabled = 0|1'
2312
`word_enabled = 0|1'
2313
     If 1 (true, the default), these parameters respectively enable the
2314 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2315 19 jeremybenn
     accesses of that width will fail.
2316
 
2317
 
2318

2319
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2320
 
2321
4 Interactive Command Line
2322
**************************
2323
 
2324
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2325 82 jeremybenn
provides the user with an interactive command line.  The commands
2326 19 jeremybenn
available, which may not be abbreviated, are:
2327
 
2328
`q'
2329
     Exit the simulator
2330
 
2331
`r'
2332 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2333 19 jeremybenn
     just executed and next to be executed instructions symbolically
2334
     and the state of the flag in the Supervision Register.
2335
 
2336
`t'
2337
     Execute the next instruction and then display register/instruction
2338
     information as with the `r' command (see above).
2339
 
2340
`run NUM [ hush ]'
2341 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2342 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2343
     above) _unless_ `hush' is specified.
2344
 
2345
`pr REG VALUE'
2346
     Patch register REG with VALUE.
2347
 
2348
`dm FROMADDR [ TOADDR ]'
2349 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2350
     not given, 64 bytes are displayed, starting at FROMADDR.
2351 19 jeremybenn
 
2352
          Caution: The output from this command is broken (a bug).
2353 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2354 19 jeremybenn
          instead of printing out the address at the start of each row,
2355
          it prints the address (of the first of the 16 bytes) before
2356
          _each_ byte.
2357
 
2358
`de FROMADDR [ TOADDR ]'
2359 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2360 19 jeremybenn
     given, 16 instructions are disassembled.
2361
 
2362
     The disassembly is entirely numerical, and gives no symbolic
2363
     information.
2364
 
2365
`pm ADDR VALUE'
2366
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2367
 
2368
`pc VALUE'
2369
     Patch the program counter with VALUE.
2370
 
2371
`cm FROMADDR TOADDR SIZE'
2372
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2373
 
2374
`break ADDR'
2375
     Toggle the breakpoint set at ADDR.
2376
 
2377
`breaks'
2378
     List all set breakpoints
2379
 
2380
`reset'
2381 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2382
     so execution will restart from the reset vector location, 0x100.
2383 19 jeremybenn
 
2384
`hist'
2385
     If saving the execution history has been configured (*note
2386
     Simulator Behavior: Simulator Behavior.), display the execution
2387
     history.
2388
 
2389
`stall'
2390
     Stall the processor, so that control is passed to the debug unit.
2391 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2392 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2393
     debuggers such as GDB.
2394
 
2395
`unstall'
2396 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2397
     This command is useful when debugging the JTAG interface, used by
2398 19 jeremybenn
     debuggers such as GDB.
2399
 
2400
`stats CATEGORY | clear'
2401
     Print the statistics for the given CATEGORY, if available, or
2402 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2403 19 jeremybenn
 
2404
    1
2405
          Miscellaneous statistics: branch predictions (if branch
2406
          predictions are enabled), branch target cache model (if
2407
          enabled), cache (if enbaled), MMU (if enabled) and number of
2408
          addtional load & store cycles.
2409
 
2410
          *Note Configuring the OpenRisc Achitectural Components: Core
2411
          OpenRISC Configuration, for details of how to enable these
2412
          various features.
2413
 
2414
    2
2415 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2416 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2417
 
2418
    3
2419 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2420 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2421
 
2422
    4
2423 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2424 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2425
          Configuration.).
2426
 
2427
    5
2428 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2429 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2430
 
2431
    6
2432 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2433 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2434
 
2435
 
2436
`info'
2437
     Display detailed information about the simulator configuration.
2438
     This is quite a lengthy about, because all MMU TLB information is
2439
     displayed.
2440
 
2441
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2442
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2443 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2444 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2445 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2446 19 jeremybenn
 
2447
     To save to a file, use the redirection function (described after
2448
     this table, below).
2449
 
2450
`dh FROMADDR [ TOADDR ]'
2451
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2452 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2453 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2454
 
2455
     To save to a file, use the redirection function (described after
2456
     this table, below).
2457
 
2458
`setdbch'
2459 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2460 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2461
     channels on the command line.
2462
 
2463
`set SECTION PARAM = VALUE'
2464
     Set the configuration parameter PARA in section SECTION to VALUE.
2465
     *Note Configuration: Configuration, for details of configuration
2466
     parameters and their settings.
2467
 
2468
`debug'
2469 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2470 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2471
     this parameter.
2472
 
2473
          Caution: This is effectively enabling or disabling the debug
2474 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2475 19 jeremybenn
          However using the remote debug interface while the debug unit
2476
          is disabled will lead to undefined behavior and likely crash
2477
          Or1ksim
2478
 
2479
`cuc'
2480
     Enter the the Custom Unit Compiler command prompt (*note CUC
2481
     Configuration: CUC Configuration.).
2482
 
2483
          Caution: The CUC must be properly configured, for this to
2484 82 jeremybenn
          succeed.  In particular a timing file must be available and
2485
          readable.  Otherwise Or1ksim will crash.
2486 19 jeremybenn
 
2487
`help'
2488
     Print out brief information about each command available.
2489
 
2490
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2491 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2492 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2493
     Profiling Utility.).
2494
 
2495
`profile [-vhcq] [-g FILE]'
2496 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2497
     usage as the standalone command (*note Profiling Utility:
2498
     Profiling Utility.).
2499 19 jeremybenn
 
2500
 
2501
For all commands, it is possible to redirect the output to a file, by
2502
using the redirection operator, `>'.
2503
 
2504
     COMMAND > FILENAME
2505
 
2506
This is particularly useful for commands dumping a large amount of
2507
output, such as `dv'.
2508
 
2509
     Caution: Unfortunately there is a serious bug with the redirection
2510 82 jeremybenn
     operator.  It does not return output to standard output after the
2511
     command completes.  Until this bug is fixed, file redirection
2512 19 jeremybenn
     should not be used.
2513
 
2514

2515
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2516
 
2517
5 Verification API (VAPI)
2518
*************************
2519
 
2520
The Verification API (VAPI) provides a TCP/IP interface to allow
2521 82 jeremybenn
components of the simulation to be controlled externally.  The
2522
interface is polled for new requests on each simulated clock cycle.
2523
Components within the simulator may send responses to such requests.
2524 19 jeremybenn
 
2525 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2526
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2527
with a single piece of data (also a 32 bit integer).  On the send side,
2528
it provides for sending a single VAPI ID and data.  However there is no
2529
explicit command-response structure.  Some components just accept
2530
requests (e.g.  to set values), some just generate sends (to report
2531 19 jeremybenn
values), and some do both.
2532
 
2533
Each component has a base ID (32 bit) and its commands will start from
2534 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2535
amongst components.  Request commands will be directed to the component
2536 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2537
 
2538
Thus if there are two components with base IDs of 0x200 and 0x300, and
2539
a request with VAPI ID of 0x203 is received, it will be directed to the
2540
first component as its command #3.
2541
 
2542
The results of VAPI interactions are logged (by default in `vapi.log'
2543
unless an alternative is specified in `section vapi').
2544
 
2545
Currently the following components support VAPI:
2546
 
2547
Debug Unit
2548
     Although the Debug Unit can specify a base VAPI ID, it is not used
2549
     to send commands or receive requests.
2550
 
2551
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2552
     exchanges are logged in the VAPI log file.
2553
 
2554
UART
2555
     If a base VAPI ID is specified, the UART sends details of any
2556
     chars or break characters sent, with dteails of the line control
2557
     register etc encoded in the data packet sent.
2558
 
2559
     This supports a single VAPI command request, but encodes a
2560
     sub-command in the top 8 bits of the associated data.
2561
 
2562
    `0x00'
2563
          This stuffs the least significant 8 bits of the data into the
2564
          serial register of the UART and the next 8 bits into the line
2565
          control register, effectively providing control of the next
2566
          character to be sent or received.
2567
 
2568
    `0x01'
2569
          The divisor latch bytes are set from the least significant 16
2570
          bits of the data.
2571
 
2572
    `0x02'
2573
          The line control register is set from bits 15-8 of the data.
2574
 
2575
    `0x03'
2576
          The UART skew is set from the least significant 16 bits of
2577
          the data
2578
 
2579
    `0x04'
2580
          If the 16th most significant bit of the data is 1, start
2581 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
2582
          are sent or cleared after the number of UART clock divider
2583
          ticks specified by the data (immediately if the data is zero).
2584 19 jeremybenn
 
2585
 
2586
DMA
2587
     Although the DMA unit supports a base VAPI ID in its configuration
2588
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
2589
     implemented.
2590
 
2591
Ethernet
2592 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
2593 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
2594 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
2595 19 jeremybenn
     VAPI requests.
2596
 
2597
    `ETH_VAPI_DATA (0)'
2598
 
2599
    `ETH_VAPI_CTRL (0)'
2600
 
2601
GPIO
2602
     If a base VAPI ID is specified, the GPIO sends out on its base
2603
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
2604
     VAPI ID) any changes in outputs.
2605
 
2606 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
2607 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
2608
     GPIO.
2609
 
2610
    `GPIO_VAPI_DATA (0)'
2611
          Set the next input to the commands data field
2612
 
2613
    `GPIO_VAPI_AUX (1)'
2614
          Set the GPIO auxiliary inputs to the data field
2615
 
2616
    `GPIO_VAPI_CLOCK (2)'
2617
          Add an external GPIO clock trigger of period specified in the
2618
          data field.
2619
 
2620
    `GPIO_VAPI_RGPIO_OE (3)'
2621
          Set the GPIO output enable to the data field
2622
 
2623
    `GPIO_VAPI_RGPIO_INTE (4)'
2624
          Set the next interrupt to the data field
2625
 
2626
    `GPIO_VAPI_RGPIO_PTRIG (5)'
2627
          Set the next trigger to the data field
2628
 
2629
    `GPIO_VAPI_RGPIO_AUX (6)'
2630
          Set the next auxiliary input to the data field
2631
 
2632
    `GPIO_VAPI_RGPIO_CTRL (7)'
2633
          Set th next control input to the data field
2634
 
2635
 
2636
 
2637

2638
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
2639
 
2640
6 A Guide to Or1ksim Internals
2641
******************************
2642
 
2643 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
2644 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
2645 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
2646
Linux manual page for `etags'.  A tag file can be created with:
2647 19 jeremybenn
 
2648
     make tags
2649
 
2650
* Menu:
2651
 
2652
* Coding Conventions::
2653
* Global Data Structures::
2654
* Concepts::
2655
* Internal Debugging::
2656 104 jeremybenn
* Regression Testing::
2657 19 jeremybenn
 
2658

2659
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
2660
 
2661
6.1 Coding Conventions for Or1ksim
2662
==================================
2663
 
2664
This chapter provides some guidelines for coding, to facilitate
2665
extensions to Or1ksim
2666
 
2667
_GNU Coding Standard_
2668
     Code should follow the GNU coding standard for C
2669 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
2670 19 jeremybenn
     through the `indent' program.
2671
 
2672
_`#include' headers_
2673
     All C source code files should include `config.h' before any other
2674
     file.
2675
 
2676
     This should be followed by inclusion of any system headers (but see
2677
     the comments about portability and `port.h' below) and then by any
2678
     Or1ksim package headers.
2679
 
2680
     If `port.h' is required, it should be the first package header to
2681
     be included after the system headers.
2682
 
2683
     All C source code and header files should directly include any
2684 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
2685
     other header having already included it.  The two exceptions are
2686 19 jeremybenn
 
2687
       1. All header files may assume that `config.h' has already been
2688
          included.
2689
 
2690
       2. System headers which impose portability problems should be
2691
          included by using the package header `port.h', rather than
2692 82 jeremybenn
          the system headers themselves.  This is the case for code
2693 19 jeremybenn
          requiring
2694
 
2695
             * `strndup' (from `string.h')
2696
 
2697
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
2698
 
2699
             * `isblank' (from `ctype.h')
2700
 
2701
 
2702
 
2703
_`#include' files once only_
2704
     All include files should be protected by `#ifndef' to ensure their
2705 82 jeremybenn
     definitions are only included once.  For instance a header file
2706 19 jeremybenn
     `X-Y.H' should surround its contents with:
2707
 
2708
          #ifndef X_Y__H
2709
          #define X_Y__H
2710
 
2711
          
2712
 
2713
          #endif  /* X_Y__H */
2714
 
2715
_Avoid `typedef'_
2716
     The GNU coding style for C does not have a clear way to distinguish
2717 82 jeremybenn
     between user type name and user variables.  For this reason
2718 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
2719 82 jeremybenn
     defined types.  This makes the code much easier to read.
2720 19 jeremybenn
 
2721
     There are some `typedef' declarations in the `argtable2' library
2722
     and the ELF and COFF headers, because this code is taken from
2723
     other places.
2724
 
2725
     Within Or1ksim legacy uses of `typedef' have largely been purged,
2726
     except in the Custom Unit Compiler (*note Custom Unit Compiler
2727
     (CUC) Configuration: CUC Configuration.).
2728
 
2729
     The remaining uses of `typedef' occur in two places:
2730
 
2731
        * `port/port.h' defines types to replace those in header files
2732
          that are not available (character functions, string
2733
          duplication, integer types).
2734
 
2735
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
2736
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
2737
          and signed register (`orreg_t') values.
2738
 
2739
 
2740
     Where new types are defined, they should appear in one of these two
2741 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
2742
     `arch.h' should always have the suffix `_h'.
2743 19 jeremybenn
 
2744
_Don't begin names with underscore_
2745
     Names beginning with `_' are intended to be part of the C
2746 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
2747 19 jeremybenn
 
2748
_Keep Non-global top level entities static_
2749
     All top level entities (functions, variables), which are not
2750
     explicitly part of a global interface should be declared static.
2751
     This ensures that unwanted connections are not inadvertently built
2752
     across the program.
2753
 
2754
_Use of `inline'_
2755 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
2756 19 jeremybenn
     out for themselves what is best in this respect.
2757
 
2758
_Initialization_
2759 82 jeremybenn
     All data structures should be explicitly initialized.  In
2760
     particular code should not rely on static data structures being
2761
     initialized to zero.
2762 19 jeremybenn
 
2763
     The rationale is that in future static data structures may become
2764 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
2765 19 jeremybenn
     historically.
2766
 
2767
     A specific case is with new peripherals, which should always
2768
     include a `start' function to pre-initialize all configuration
2769
     parameters to sensible defaults
2770
 
2771
_Configuration Validation_
2772
     All configuration values should be validated, preferably when
2773
     encountered, if not when the `section' is closed, or otherwise at
2774
     run time when the parameter is first used.
2775
 
2776
 
2777

2778
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
2779
 
2780
6.2 Global Data Structures
2781
==========================
2782
 
2783
`config'
2784
     The global variable `config' of type `struct config' holds the
2785
     configuration data for some of the Or1ksim components which are
2786 82 jeremybenn
     always present.  At present the components are:
2787 19 jeremybenn
 
2788
        * The simulator defined in `section sim' (*note Simulator
2789
          Configuration: Simulator Configuration.).
2790
 
2791
        * The Verification API (VAPI) defined  in `section vapi' (*note
2792
          Verification API (VAPI) Configuration: Verification API
2793
          Configuration.).
2794
 
2795
        * The Custom Unit Compiler (CUC), defined in `section cuc'
2796
          (*note Custom Unit Compiler (CUC) Configuration: CUC
2797
          Configuration.).
2798
 
2799
        * The CPU, defined in `section cpu' (*note CPU Configuration:
2800
          CPU Configuration.).
2801
 
2802
        * The data cache (but not the instruction cache), defined in
2803
          `section dc' (*note Cache Configuration: Cache
2804
          Configuration.).
2805
 
2806
        * The power management unit, defined in `section pm' (*note
2807
          Power Management Configuration: Power Management
2808
          Configuration.).
2809
 
2810
        * The programmable interrupt controller, defined in
2811
          `section pic' (*note Interrupt Configuration: Interrupt
2812
          Configuration.).
2813
 
2814
        * Branch prediciton, defined in `section bpb' (*note Branch
2815
          Prediction Configuration: Branch Prediction Configuration.).
2816
 
2817
        * The debug unit, defined in `section debug' (*note Debug
2818
          Interface Configuration: Debug Interface Configuration.).
2819
 
2820
 
2821
     This struct is made of a collection of structs, one for each
2822 82 jeremybenn
     component.  For example the simulator configuration is held in
2823 19 jeremybenn
     `config.sim'.
2824
 
2825
`config'
2826
     This is a linked list of data structures holding configuration data
2827
     for all sections which are not held in the main `config' data
2828 82 jeremybenn
     structure.  In general these are components (such as peripherals
2829
     and memory) which may occur multiple times.  However it also
2830
     handles some architectural components which may occur only once,
2831
     such as the memory management units, the instruction cache, the
2832
     interrupt controller and branch prediction.
2833 19 jeremybenn
 
2834
`runtime'
2835
     The global variable `runtime' of type `struct runtime' holds all
2836 82 jeremybenn
     the runtime information about the simulation.  To access this
2837 19 jeremybenn
     variable, `sim-config.h' must be included.
2838
 
2839
     This struct is itself made of 3 other structs, `cpu' (for CPU run
2840
     time state), `vapi' (for Verification API state) and `cuc' (for
2841
     Custom Unit Compiler state).
2842
 
2843
 
2844

2845
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
2846
 
2847
6.3 Concepts
2848
============
2849
 
2850
_Output Redirection_
2851 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
2852 19 jeremybenn
     should be explicitly written to this stream, or may use the
2853
     `PRINTF' macro, which will write its arguments to this output
2854
     stream.
2855
 
2856
_Reset Hooks_
2857
     Any peripheral may register a routine to be called when the the
2858
     processor is reset by calling `reg_sim_reset', providing a
2859 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
2860 19 jeremybenn
     that function will be called with the data stucture pointer as
2861
     argument.
2862
 
2863
 
2864

2865 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
2866 19 jeremybenn
 
2867
6.4 Internal Debugging
2868
======================
2869
 
2870
The function `debug' is like `printf', but with an extra first
2871 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
2872
the simulator configuration (*note Simulator Behavior: Simulator
2873
Behavior.) is greater than or equal to this value, the remaining
2874
arguments are printed to the current output stream (*note Output
2875
Redirection: Output Redirection.).
2876 19 jeremybenn
 
2877

2878 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
2879
 
2880
6.5 Regression Testing
2881
======================
2882
 
2883
Or1ksim now includes a regression test suite for both standalone and
2884
library usage as described earlier (*note Building and Installing:
2885
Build and Install.).  Running the tests requires that the OpenRISC
2886
toolchain and DejaGNU are both installed.
2887
 
2888
Tests are written using `expect', a derivative of TCL.  Documentation
2889
of DejaGnu, `expect' and TCL are freely available on the Web.  The
2890
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
2891
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
2892
provides a concise introduction.
2893
 
2894
All test code is found in the `testsuite' directory.  The key files and
2895
directories used are as follows.
2896
 
2897
`global-conf.exp'
2898
     This is the global DejaGNU configuration file used to set up
2899
     parameters common to all tests.  If the user has the environment
2900
     varialbe `DEJAGNU' defined, it will be used instead, but this is
2901
     not recommended.
2902
 
2903
`Makefile.am'
2904
     This is the top level `automake' file for the testsuite.  The only
2905
     changes likely to be needed here is additional local cleanup of
2906
     files created by new tests.
2907
 
2908
`README'
2909
     This contains details of all the tests
2910
 
2911
`config'
2912
     This contains DejaGnu board configurations.  Since the tests are
2913
     generally run on a Unix host, this should just contain `Unix.exp'.
2914
 
2915
`lib'
2916
     This contains DejaGnu tool specific configurations.  "Tool" has a
2917
     specific meaning in DejaGNU, referring just to a grouping of
2918
     tests.  In this case there are two such "tools", "or1ksim" and
2919
     "libsim" for tests of the standalone tool and tests of the library.
2920
 
2921
     Corresponding to this, there are two tool specific configuration
2922
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
2923
     procedures for common use among the tests.
2924
 
2925
`libsim.tests'
2926
`or1ksim.tests'
2927
     These are the directories of tests of the Or1ksim library.  They
2928
     also include Or1ksim configuration files and each has a
2929
     `Makefile.am' file.  `Makefile.am' should be updated whenever
2930
     files are added to this directory, to ensure they are included in
2931
     the distribution.
2932
 
2933
`test-code'
2934
     These are all the test programs to be compiled on the host (each
2935
     in its own directory).  In general these are programs to support
2936
     testing of the library, and build various programs linking in the
2937
     library.
2938
 
2939
`test-code'
2940
     These are all the test programs to be compiled with the OpenRISC
2941
     tool chain to run with either standalone Or1ksim or the library.
2942
     This directory includes its own `configure.ac', since it must set
2943
     up a separate tool chain based on the target, not the host.
2944
 
2945
 
2946
To add a new test needs the following steps.
2947
 
2948
   * Put new host C code in its own directory within `test-code'. Add
2949
     the directory to the existing `Makefile.am' in the `test-code'
2950
     directory and create a `Makefile.am' in the new directory to drive
2951
     building the test program(s). Don't forget to add the new
2952
     `Makefile' to the top level `configure.ac' so it gets generated.
2953
     Not all tests require code here.
2954
 
2955
   * Put new target C code in its own directory within
2956
     `test-code-or1k'. Once again modify & create `Makefile.am'. this
2957
     time though modify the `configure.ac' in the `test-code-or1k' so
2958
     the `Makefile' gets generated. The existing programs provide
2959
     examples to start from, including custom linker scripts where
2960
     needed.
2961
 
2962
   * Add one or more tests and configuration files to the relevant
2963
     "tool" test directory. Use the existing tests as templates. They
2964
     make heavy use of the `expect'/TCL procedures in the `config'
2965
     directory to facilitate driving the tests.
2966
 
2967
 
2968

2969 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
2970
 
2971
7 GNU Free Documentation License
2972
********************************
2973
 
2974
                      Version 1.2, November 2002
2975
 
2976
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
2977
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
2978
 
2979
     Everyone is permitted to copy and distribute verbatim copies
2980
     of this license document, but changing it is not allowed.
2981
 
2982
  0. PREAMBLE
2983
 
2984
     The purpose of this License is to make a manual, textbook, or other
2985
     functional and useful document "free" in the sense of freedom: to
2986
     assure everyone the effective freedom to copy and redistribute it,
2987
     with or without modifying it, either commercially or
2988
     noncommercially.  Secondarily, this License preserves for the
2989
     author and publisher a way to get credit for their work, while not
2990
     being considered responsible for modifications made by others.
2991
 
2992
     This License is a kind of "copyleft", which means that derivative
2993
     works of the document must themselves be free in the same sense.
2994
     It complements the GNU General Public License, which is a copyleft
2995
     license designed for free software.
2996
 
2997
     We have designed this License in order to use it for manuals for
2998
     free software, because free software needs free documentation: a
2999
     free program should come with manuals providing the same freedoms
3000
     that the software does.  But this License is not limited to
3001
     software manuals; it can be used for any textual work, regardless
3002
     of subject matter or whether it is published as a printed book.
3003
     We recommend this License principally for works whose purpose is
3004
     instruction or reference.
3005
 
3006
  1. APPLICABILITY AND DEFINITIONS
3007
 
3008
     This License applies to any manual or other work, in any medium,
3009
     that contains a notice placed by the copyright holder saying it
3010
     can be distributed under the terms of this License.  Such a notice
3011
     grants a world-wide, royalty-free license, unlimited in duration,
3012
     to use that work under the conditions stated herein.  The
3013
     "Document", below, refers to any such manual or work.  Any member
3014
     of the public is a licensee, and is addressed as "you".  You
3015
     accept the license if you copy, modify or distribute the work in a
3016
     way requiring permission under copyright law.
3017
 
3018
     A "Modified Version" of the Document means any work containing the
3019
     Document or a portion of it, either copied verbatim, or with
3020
     modifications and/or translated into another language.
3021
 
3022
     A "Secondary Section" is a named appendix or a front-matter section
3023
     of the Document that deals exclusively with the relationship of the
3024
     publishers or authors of the Document to the Document's overall
3025
     subject (or to related matters) and contains nothing that could
3026
     fall directly within that overall subject.  (Thus, if the Document
3027
     is in part a textbook of mathematics, a Secondary Section may not
3028
     explain any mathematics.)  The relationship could be a matter of
3029
     historical connection with the subject or with related matters, or
3030
     of legal, commercial, philosophical, ethical or political position
3031
     regarding them.
3032
 
3033
     The "Invariant Sections" are certain Secondary Sections whose
3034
     titles are designated, as being those of Invariant Sections, in
3035
     the notice that says that the Document is released under this
3036
     License.  If a section does not fit the above definition of
3037
     Secondary then it is not allowed to be designated as Invariant.
3038
     The Document may contain zero Invariant Sections.  If the Document
3039
     does not identify any Invariant Sections then there are none.
3040
 
3041
     The "Cover Texts" are certain short passages of text that are
3042
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3043
     that says that the Document is released under this License.  A
3044
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3045
     be at most 25 words.
3046
 
3047
     A "Transparent" copy of the Document means a machine-readable copy,
3048
     represented in a format whose specification is available to the
3049
     general public, that is suitable for revising the document
3050
     straightforwardly with generic text editors or (for images
3051
     composed of pixels) generic paint programs or (for drawings) some
3052
     widely available drawing editor, and that is suitable for input to
3053
     text formatters or for automatic translation to a variety of
3054
     formats suitable for input to text formatters.  A copy made in an
3055
     otherwise Transparent file format whose markup, or absence of
3056
     markup, has been arranged to thwart or discourage subsequent
3057
     modification by readers is not Transparent.  An image format is
3058
     not Transparent if used for any substantial amount of text.  A
3059
     copy that is not "Transparent" is called "Opaque".
3060
 
3061
     Examples of suitable formats for Transparent copies include plain
3062
     ASCII without markup, Texinfo input format, LaTeX input format,
3063
     SGML or XML using a publicly available DTD, and
3064
     standard-conforming simple HTML, PostScript or PDF designed for
3065
     human modification.  Examples of transparent image formats include
3066
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3067
     can be read and edited only by proprietary word processors, SGML or
3068
     XML for which the DTD and/or processing tools are not generally
3069
     available, and the machine-generated HTML, PostScript or PDF
3070
     produced by some word processors for output purposes only.
3071
 
3072
     The "Title Page" means, for a printed book, the title page itself,
3073
     plus such following pages as are needed to hold, legibly, the
3074
     material this License requires to appear in the title page.  For
3075
     works in formats which do not have any title page as such, "Title
3076
     Page" means the text near the most prominent appearance of the
3077
     work's title, preceding the beginning of the body of the text.
3078
 
3079
     A section "Entitled XYZ" means a named subunit of the Document
3080
     whose title either is precisely XYZ or contains XYZ in parentheses
3081
     following text that translates XYZ in another language.  (Here XYZ
3082
     stands for a specific section name mentioned below, such as
3083
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3084
     To "Preserve the Title" of such a section when you modify the
3085
     Document means that it remains a section "Entitled XYZ" according
3086
     to this definition.
3087
 
3088
     The Document may include Warranty Disclaimers next to the notice
3089
     which states that this License applies to the Document.  These
3090
     Warranty Disclaimers are considered to be included by reference in
3091
     this License, but only as regards disclaiming warranties: any other
3092
     implication that these Warranty Disclaimers may have is void and
3093
     has no effect on the meaning of this License.
3094
 
3095
  2. VERBATIM COPYING
3096
 
3097
     You may copy and distribute the Document in any medium, either
3098
     commercially or noncommercially, provided that this License, the
3099
     copyright notices, and the license notice saying this License
3100
     applies to the Document are reproduced in all copies, and that you
3101
     add no other conditions whatsoever to those of this License.  You
3102
     may not use technical measures to obstruct or control the reading
3103
     or further copying of the copies you make or distribute.  However,
3104
     you may accept compensation in exchange for copies.  If you
3105
     distribute a large enough number of copies you must also follow
3106
     the conditions in section 3.
3107
 
3108
     You may also lend copies, under the same conditions stated above,
3109
     and you may publicly display copies.
3110
 
3111
  3. COPYING IN QUANTITY
3112
 
3113
     If you publish printed copies (or copies in media that commonly
3114
     have printed covers) of the Document, numbering more than 100, and
3115
     the Document's license notice requires Cover Texts, you must
3116
     enclose the copies in covers that carry, clearly and legibly, all
3117
     these Cover Texts: Front-Cover Texts on the front cover, and
3118
     Back-Cover Texts on the back cover.  Both covers must also clearly
3119
     and legibly identify you as the publisher of these copies.  The
3120
     front cover must present the full title with all words of the
3121
     title equally prominent and visible.  You may add other material
3122
     on the covers in addition.  Copying with changes limited to the
3123
     covers, as long as they preserve the title of the Document and
3124
     satisfy these conditions, can be treated as verbatim copying in
3125
     other respects.
3126
 
3127
     If the required texts for either cover are too voluminous to fit
3128
     legibly, you should put the first ones listed (as many as fit
3129
     reasonably) on the actual cover, and continue the rest onto
3130
     adjacent pages.
3131
 
3132
     If you publish or distribute Opaque copies of the Document
3133
     numbering more than 100, you must either include a
3134
     machine-readable Transparent copy along with each Opaque copy, or
3135
     state in or with each Opaque copy a computer-network location from
3136
     which the general network-using public has access to download
3137
     using public-standard network protocols a complete Transparent
3138
     copy of the Document, free of added material.  If you use the
3139
     latter option, you must take reasonably prudent steps, when you
3140
     begin distribution of Opaque copies in quantity, to ensure that
3141
     this Transparent copy will remain thus accessible at the stated
3142
     location until at least one year after the last time you
3143
     distribute an Opaque copy (directly or through your agents or
3144
     retailers) of that edition to the public.
3145
 
3146
     It is requested, but not required, that you contact the authors of
3147
     the Document well before redistributing any large number of
3148
     copies, to give them a chance to provide you with an updated
3149
     version of the Document.
3150
 
3151
  4. MODIFICATIONS
3152
 
3153
     You may copy and distribute a Modified Version of the Document
3154
     under the conditions of sections 2 and 3 above, provided that you
3155
     release the Modified Version under precisely this License, with
3156
     the Modified Version filling the role of the Document, thus
3157
     licensing distribution and modification of the Modified Version to
3158
     whoever possesses a copy of it.  In addition, you must do these
3159
     things in the Modified Version:
3160
 
3161
       A. Use in the Title Page (and on the covers, if any) a title
3162
          distinct from that of the Document, and from those of
3163
          previous versions (which should, if there were any, be listed
3164
          in the History section of the Document).  You may use the
3165
          same title as a previous version if the original publisher of
3166
          that version gives permission.
3167
 
3168
       B. List on the Title Page, as authors, one or more persons or
3169
          entities responsible for authorship of the modifications in
3170
          the Modified Version, together with at least five of the
3171
          principal authors of the Document (all of its principal
3172
          authors, if it has fewer than five), unless they release you
3173
          from this requirement.
3174
 
3175
       C. State on the Title page the name of the publisher of the
3176
          Modified Version, as the publisher.
3177
 
3178
       D. Preserve all the copyright notices of the Document.
3179
 
3180
       E. Add an appropriate copyright notice for your modifications
3181
          adjacent to the other copyright notices.
3182
 
3183
       F. Include, immediately after the copyright notices, a license
3184
          notice giving the public permission to use the Modified
3185
          Version under the terms of this License, in the form shown in
3186
          the Addendum below.
3187
 
3188
       G. Preserve in that license notice the full lists of Invariant
3189
          Sections and required Cover Texts given in the Document's
3190
          license notice.
3191
 
3192
       H. Include an unaltered copy of this License.
3193
 
3194
       I. Preserve the section Entitled "History", Preserve its Title,
3195
          and add to it an item stating at least the title, year, new
3196
          authors, and publisher of the Modified Version as given on
3197
          the Title Page.  If there is no section Entitled "History" in
3198
          the Document, create one stating the title, year, authors,
3199
          and publisher of the Document as given on its Title Page,
3200
          then add an item describing the Modified Version as stated in
3201
          the previous sentence.
3202
 
3203
       J. Preserve the network location, if any, given in the Document
3204
          for public access to a Transparent copy of the Document, and
3205
          likewise the network locations given in the Document for
3206
          previous versions it was based on.  These may be placed in
3207
          the "History" section.  You may omit a network location for a
3208
          work that was published at least four years before the
3209
          Document itself, or if the original publisher of the version
3210
          it refers to gives permission.
3211
 
3212
       K. For any section Entitled "Acknowledgements" or "Dedications",
3213
          Preserve the Title of the section, and preserve in the
3214
          section all the substance and tone of each of the contributor
3215
          acknowledgements and/or dedications given therein.
3216
 
3217
       L. Preserve all the Invariant Sections of the Document,
3218
          unaltered in their text and in their titles.  Section numbers
3219
          or the equivalent are not considered part of the section
3220
          titles.
3221
 
3222
       M. Delete any section Entitled "Endorsements".  Such a section
3223
          may not be included in the Modified Version.
3224
 
3225
       N. Do not retitle any existing section to be Entitled
3226
          "Endorsements" or to conflict in title with any Invariant
3227
          Section.
3228
 
3229
       O. Preserve any Warranty Disclaimers.
3230
 
3231
     If the Modified Version includes new front-matter sections or
3232
     appendices that qualify as Secondary Sections and contain no
3233
     material copied from the Document, you may at your option
3234
     designate some or all of these sections as invariant.  To do this,
3235
     add their titles to the list of Invariant Sections in the Modified
3236
     Version's license notice.  These titles must be distinct from any
3237
     other section titles.
3238
 
3239
     You may add a section Entitled "Endorsements", provided it contains
3240
     nothing but endorsements of your Modified Version by various
3241
     parties--for example, statements of peer review or that the text
3242
     has been approved by an organization as the authoritative
3243
     definition of a standard.
3244
 
3245
     You may add a passage of up to five words as a Front-Cover Text,
3246
     and a passage of up to 25 words as a Back-Cover Text, to the end
3247
     of the list of Cover Texts in the Modified Version.  Only one
3248
     passage of Front-Cover Text and one of Back-Cover Text may be
3249
     added by (or through arrangements made by) any one entity.  If the
3250
     Document already includes a cover text for the same cover,
3251
     previously added by you or by arrangement made by the same entity
3252
     you are acting on behalf of, you may not add another; but you may
3253
     replace the old one, on explicit permission from the previous
3254
     publisher that added the old one.
3255
 
3256
     The author(s) and publisher(s) of the Document do not by this
3257
     License give permission to use their names for publicity for or to
3258
     assert or imply endorsement of any Modified Version.
3259
 
3260
  5. COMBINING DOCUMENTS
3261
 
3262
     You may combine the Document with other documents released under
3263
     this License, under the terms defined in section 4 above for
3264
     modified versions, provided that you include in the combination
3265
     all of the Invariant Sections of all of the original documents,
3266
     unmodified, and list them all as Invariant Sections of your
3267
     combined work in its license notice, and that you preserve all
3268
     their Warranty Disclaimers.
3269
 
3270
     The combined work need only contain one copy of this License, and
3271
     multiple identical Invariant Sections may be replaced with a single
3272
     copy.  If there are multiple Invariant Sections with the same name
3273
     but different contents, make the title of each such section unique
3274
     by adding at the end of it, in parentheses, the name of the
3275
     original author or publisher of that section if known, or else a
3276
     unique number.  Make the same adjustment to the section titles in
3277
     the list of Invariant Sections in the license notice of the
3278
     combined work.
3279
 
3280
     In the combination, you must combine any sections Entitled
3281
     "History" in the various original documents, forming one section
3282
     Entitled "History"; likewise combine any sections Entitled
3283
     "Acknowledgements", and any sections Entitled "Dedications".  You
3284
     must delete all sections Entitled "Endorsements."
3285
 
3286
  6. COLLECTIONS OF DOCUMENTS
3287
 
3288
     You may make a collection consisting of the Document and other
3289
     documents released under this License, and replace the individual
3290
     copies of this License in the various documents with a single copy
3291
     that is included in the collection, provided that you follow the
3292
     rules of this License for verbatim copying of each of the
3293
     documents in all other respects.
3294
 
3295
     You may extract a single document from such a collection, and
3296
     distribute it individually under this License, provided you insert
3297
     a copy of this License into the extracted document, and follow
3298
     this License in all other respects regarding verbatim copying of
3299
     that document.
3300
 
3301
  7. AGGREGATION WITH INDEPENDENT WORKS
3302
 
3303
     A compilation of the Document or its derivatives with other
3304
     separate and independent documents or works, in or on a volume of
3305
     a storage or distribution medium, is called an "aggregate" if the
3306
     copyright resulting from the compilation is not used to limit the
3307
     legal rights of the compilation's users beyond what the individual
3308
     works permit.  When the Document is included in an aggregate, this
3309
     License does not apply to the other works in the aggregate which
3310
     are not themselves derivative works of the Document.
3311
 
3312
     If the Cover Text requirement of section 3 is applicable to these
3313
     copies of the Document, then if the Document is less than one half
3314
     of the entire aggregate, the Document's Cover Texts may be placed
3315
     on covers that bracket the Document within the aggregate, or the
3316
     electronic equivalent of covers if the Document is in electronic
3317
     form.  Otherwise they must appear on printed covers that bracket
3318
     the whole aggregate.
3319
 
3320
  8. TRANSLATION
3321
 
3322
     Translation is considered a kind of modification, so you may
3323
     distribute translations of the Document under the terms of section
3324
     4.  Replacing Invariant Sections with translations requires special
3325
     permission from their copyright holders, but you may include
3326
     translations of some or all Invariant Sections in addition to the
3327
     original versions of these Invariant Sections.  You may include a
3328
     translation of this License, and all the license notices in the
3329
     Document, and any Warranty Disclaimers, provided that you also
3330
     include the original English version of this License and the
3331
     original versions of those notices and disclaimers.  In case of a
3332
     disagreement between the translation and the original version of
3333
     this License or a notice or disclaimer, the original version will
3334
     prevail.
3335
 
3336
     If a section in the Document is Entitled "Acknowledgements",
3337
     "Dedications", or "History", the requirement (section 4) to
3338
     Preserve its Title (section 1) will typically require changing the
3339
     actual title.
3340
 
3341
  9. TERMINATION
3342
 
3343
     You may not copy, modify, sublicense, or distribute the Document
3344
     except as expressly provided for under this License.  Any other
3345
     attempt to copy, modify, sublicense or distribute the Document is
3346
     void, and will automatically terminate your rights under this
3347
     License.  However, parties who have received copies, or rights,
3348
     from you under this License will not have their licenses
3349
     terminated so long as such parties remain in full compliance.
3350
 
3351
 10. FUTURE REVISIONS OF THIS LICENSE
3352
 
3353
     The Free Software Foundation may publish new, revised versions of
3354
     the GNU Free Documentation License from time to time.  Such new
3355
     versions will be similar in spirit to the present version, but may
3356
     differ in detail to address new problems or concerns.  See
3357
     `http://www.gnu.org/copyleft/'.
3358
 
3359
     Each version of the License is given a distinguishing version
3360
     number.  If the Document specifies that a particular numbered
3361
     version of this License "or any later version" applies to it, you
3362
     have the option of following the terms and conditions either of
3363
     that specified version or of any later version that has been
3364
     published (not as a draft) by the Free Software Foundation.  If
3365
     the Document does not specify a version number of this License,
3366
     you may choose any version ever published (not as a draft) by the
3367
     Free Software Foundation.
3368
 
3369
ADDENDUM: How to use this License for your documents
3370
====================================================
3371
 
3372
To use this License in a document you have written, include a copy of
3373
the License in the document and put the following copyright and license
3374
notices just after the title page:
3375
 
3376
       Copyright (C)  YEAR  YOUR NAME.
3377
       Permission is granted to copy, distribute and/or modify this document
3378
       under the terms of the GNU Free Documentation License, Version 1.2
3379
       or any later version published by the Free Software Foundation;
3380
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3381
       Texts.  A copy of the license is included in the section entitled ``GNU
3382
       Free Documentation License''.
3383
 
3384
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3385
replace the "with...Texts." line with this:
3386
 
3387
         with the Invariant Sections being LIST THEIR TITLES, with
3388
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3389
         being LIST.
3390
 
3391
If you have Invariant Sections without Cover Texts, or some other
3392
combination of the three, merge those two alternatives to suit the
3393
situation.
3394
 
3395
If your document contains nontrivial examples of program code, we
3396
recommend releasing these examples in parallel under your choice of
3397
free software license, such as the GNU General Public License, to
3398
permit their use in free software.
3399
 
3400

3401
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3402
 
3403
Index
3404
*****
3405
 
3406
 
3407
* Menu:
3408
3409
* --cumulative:                          Profiling Utility.   (line  26)
3410
* --debug-config:                        Standalone Simulator.
3411 235 jeremybenn
                                                              (line  50)
3412 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3413 127 jeremybenn
                                                              (line 105)
3414 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3415 127 jeremybenn
                                                              (line 118)
3416 124 jeremybenn
* --disable-debug:                       Configuring the Build.
3417 127 jeremybenn
                                                              (line  98)
3418 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3419 104 jeremybenn
                                                              (line  59)
3420 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3421 127 jeremybenn
                                                              (line 133)
3422 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3423 104 jeremybenn
                                                              (line  30)
3424 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3425 127 jeremybenn
                                                              (line  92)
3426
* --disable-unsigned-xori:               Configuring the Build.
3427 104 jeremybenn
                                                              (line  69)
3428 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3429 127 jeremybenn
                                                              (line 104)
3430 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3431 127 jeremybenn
                                                              (line 117)
3432 124 jeremybenn
* --enable-debug:                        Configuring the Build.
3433 127 jeremybenn
                                                              (line  97)
3434 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3435 104 jeremybenn
                                                              (line  58)
3436 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3437 104 jeremybenn
                                                              (line  37)
3438 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3439 235 jeremybenn
                                                              (line  79)
3440 19 jeremybenn
* --enable-ov-flag:                      Configuring the Build.
3441 127 jeremybenn
                                                              (line 132)
3442 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3443 235 jeremybenn
                                                              (line  76)
3444 19 jeremybenn
* --enable-profiling:                    Configuring the Build.
3445 104 jeremybenn
                                                              (line  29)
3446 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3447 127 jeremybenn
                                                              (line  91)
3448
* --enable-unsigned-xori:                Configuring the Build.
3449 104 jeremybenn
                                                              (line  68)
3450 19 jeremybenn
* --file:                                Standalone Simulator.
3451
                                                              (line  24)
3452
* --filename:                            Memory Profiling Utility.
3453
                                                              (line  51)
3454
* --generate:                            Profiling Utility.   (line  34)
3455
* --group:                               Memory Profiling Utility.
3456
                                                              (line  47)
3457
* --help:                                Standalone Simulator.
3458
                                                              (line  20)
3459
* --help (memory profiling utility):     Memory Profiling Utility.
3460
                                                              (line  22)
3461
* --help (profiling utility):            Profiling Utility.   (line  22)
3462
* --interactive:                         Standalone Simulator.
3463 235 jeremybenn
                                                              (line  56)
3464 19 jeremybenn
* --mode:                                Memory Profiling Utility.
3465
                                                              (line  26)
3466
* --nosrv:                               Standalone Simulator.
3467
                                                              (line  32)
3468
* --quiet:                               Profiling Utility.   (line  30)
3469
* --srv:                                 Standalone Simulator.
3470
                                                              (line  40)
3471
* --strict-npc:                          Standalone Simulator.
3472 235 jeremybenn
                                                              (line  59)
3473 19 jeremybenn
* --version:                             Standalone Simulator.
3474
                                                              (line  16)
3475
* --version (memory profiling utility):  Memory Profiling Utility.
3476
                                                              (line  17)
3477
* --version (profiling utility):         Profiling Utility.   (line  17)
3478
* -c:                                    Profiling Utility.   (line  26)
3479
* -d:                                    Standalone Simulator.
3480 235 jeremybenn
                                                              (line  50)
3481 19 jeremybenn
* -f <1>:                                Memory Profiling Utility.
3482
                                                              (line  51)
3483
* -f:                                    Standalone Simulator.
3484
                                                              (line  24)
3485 240 julius
* -g <1>:                                Profiling Utility.   (line  34)
3486
* -g:                                    Memory Profiling Utility.
3487 19 jeremybenn
                                                              (line  47)
3488
* -h:                                    Standalone Simulator.
3489
                                                              (line  20)
3490
* -h (memory profiling utility):         Memory Profiling Utility.
3491
                                                              (line  22)
3492
* -h (profiling utility):                Profiling Utility.   (line  22)
3493
* -i:                                    Standalone Simulator.
3494 235 jeremybenn
                                                              (line  56)
3495 19 jeremybenn
* -m:                                    Memory Profiling Utility.
3496
                                                              (line  26)
3497
* -q:                                    Profiling Utility.   (line  30)
3498
* -v:                                    Standalone Simulator.
3499
                                                              (line  16)
3500
* -v (memory profiling utility):         Memory Profiling Utility.
3501
                                                              (line  17)
3502
* -v (profiling utility):                Profiling Utility.   (line  17)
3503
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3504
                                                              (line  49)
3505
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3506
                                                              (line  55)
3507
* 0x02 UART VAPI sub-command (UART verification): Verification API.
3508
                                                              (line  59)
3509
* 0x03 UART VAPI sub-command (UART verification): Verification API.
3510
                                                              (line  62)
3511
* 0x04 UART VAPI sub-command (UART verification): Verification API.
3512
                                                              (line  66)
3513
* 16550 (UART configuration):            UART Configuration.  (line  73)
3514 82 jeremybenn
* all tests enabled:                     Configuring the Build.
3515 127 jeremybenn
                                                              (line 105)
3516 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
3517 127 jeremybenn
                                                              (line  98)
3518 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
3519
                                                              (line   6)
3520
* ATA/ATAPI device configuration:        Disc Interface Configuration.
3521
                                                              (line  88)
3522
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
3523
                                                              (line  32)
3524
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
3525
                                                              (line  22)
3526
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
3527
* baseaddr (Ethernet configuration):     Ethernet Configuration.
3528
                                                              (line  22)
3529
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
3530
                                                              (line  20)
3531
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
3532
                                                              (line  22)
3533
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
3534
* baseaddr (keyboard configuration):     Keyboard Configuration.
3535
                                                              (line  36)
3536
* baseaddr (memory configuration):       Memory Configuration.
3537 240 julius
                                                              (line  88)
3538 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
3539 98 jeremybenn
                                                              (line  46)
3540 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
3541
* baseaddr (VGA configuration):          Display Interface Configuration.
3542
                                                              (line  26)
3543
* blocksize (cache configuration):       Cache Configuration. (line  29)
3544
* BPB configuration:                     Branch Prediction Configuration.
3545
                                                              (line   6)
3546
* branch prediction configuration:       Branch Prediction Configuration.
3547
                                                              (line   6)
3548
* break (Interactive CLI):               Interactive Command Line.
3549
                                                              (line  57)
3550
* breakpoint list (Interactive CLI):     Interactive Command Line.
3551
                                                              (line  60)
3552
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
3553
                                                              (line  57)
3554
* breaks (Interactive CLI):              Interactive Command Line.
3555
                                                              (line  60)
3556
* btic (branch prediction configuration): Branch Prediction Configuration.
3557
                                                              (line  19)
3558
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3559
                                                              (line  48)
3560
* cache configuration:                   Cache Configuration. (line   6)
3561
* calling_convention (CUC configuration): CUC Configuration.  (line  34)
3562
* ce (memory configuration):             Memory Configuration.
3563 240 julius
                                                              (line 118)
3564 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
3565
* channel (UART configuration):          UART Configuration.  (line  29)
3566
* clear breakpoint (Interactive CLI):    Interactive Command Line.
3567
                                                              (line  57)
3568 202 julius
* clkcycle (simulator configuration):    Simulator Behavior.  (line 115)
3569 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
3570
                                                              (line  54)
3571
* command line for Or1ksim standalone use: Standalone Simulator.
3572
                                                              (line   6)
3573
* complex model:                         Configuring the Build.
3574 104 jeremybenn
                                                              (line  37)
3575 19 jeremybenn
* config:                                Global Data Structures.
3576
                                                              (line   7)
3577
* config.bpb:                            Global Data Structures.
3578
                                                              (line  37)
3579
* config.cpu:                            Global Data Structures.
3580
                                                              (line  22)
3581
* config.cuc:                            Global Data Structures.
3582
                                                              (line  18)
3583
* config.dc:                             Global Data Structures.
3584
                                                              (line  25)
3585
* config.debug:                          Global Data Structures.
3586
                                                              (line  40)
3587
* config.pic:                            Global Data Structures.
3588
                                                              (line  33)
3589
* config.pm:                             Global Data Structures.
3590
                                                              (line  29)
3591
* config.sim:                            Global Data Structures.
3592
                                                              (line  11)
3593
* config.vapi:                           Global Data Structures.
3594
                                                              (line  14)
3595
* configuration dynamic structure:       Global Data Structures.
3596
                                                              (line  49)
3597
* configuration file structure:          Configuration File Format.
3598
                                                              (line   6)
3599
* configuration global structure:        Global Data Structures.
3600
                                                              (line   7)
3601
* configuration info (Interactive CLI):  Interactive Command Line.
3602
                                                              (line 119)
3603
* configuration of generic peripherals:  Generic Peripheral Configuration.
3604
                                                              (line   6)
3605
* configuration parameter setting (Interactive CLI): Interactive Command Line.
3606
                                                              (line 146)
3607
* configuring branch prediction:         Branch Prediction Configuration.
3608
                                                              (line   6)
3609
* configuring data & instruction caches: Cache Configuration. (line   6)
3610
* configuring data & instruction MMUs:   Memory Management Configuration.
3611
                                                              (line   6)
3612
* configuring DMA:                       DMA Configuration.   (line   6)
3613
* configuring memory:                    Memory Configuration.
3614
                                                              (line   6)
3615
* configuring Or1ksim:                   Configuration.       (line   6)
3616
* configuring power management:          Power Management Configuration.
3617
                                                              (line   6)
3618
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
3619
                                                              (line   6)
3620
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
3621
* configuring the CPU:                   CPU Configuration.   (line   6)
3622
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
3623
                                                              (line   6)
3624
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
3625
                                                              (line   6)
3626
* configuring the Ethernet interface:    Ethernet Configuration.
3627
                                                              (line   6)
3628
* configuring the frame buffer:          Frame Buffer Configuration.
3629
                                                              (line   6)
3630
* configuring the GPIO:                  GPIO Configuration.  (line   6)
3631
* configuring the interrupt controller:  Interrupt Configuration.
3632
                                                              (line   6)
3633
* configuring the keyboard interface:    Keyboard Configuration.
3634
                                                              (line   6)
3635
* configuring the memory controller:     Memory Controller Configuration.
3636
                                                              (line   6)
3637
* configuring the processor:             CPU Configuration.   (line   6)
3638
* configuring the PS2 interface:         Keyboard Configuration.
3639
                                                              (line   6)
3640
* configuring the UART:                  UART Configuration.  (line   6)
3641
* configuring the Verification API (VAPI): Verification API Configuration.
3642
                                                              (line   6)
3643
* configuring the VGA interface:         Display Interface Configuration.
3644
                                                              (line   6)
3645
* copying memory (Interactive CLI):      Interactive Command Line.
3646
                                                              (line  54)
3647
* CPU configuration:                     CPU Configuration.   (line   6)
3648
* CUC configuration:                     CUC Configuration.   (line   6)
3649
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
3650
                                                              (line 162)
3651
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
3652
* data cache configuration:              Cache Configuration. (line   6)
3653
* data MMU configuration:                Memory Management Configuration.
3654
                                                              (line   6)
3655
* DCGE (power management register):      Power Management Configuration.
3656
                                                              (line  21)
3657
* debug (Interactive CLI):               Interactive Command Line.
3658 240 julius
                                                              (line 162)
3659 19 jeremybenn
* debug (simulator configuration):       Simulator Behavior.  (line  13)
3660
* debug channel toggle (Interactive CLI): Interactive Command Line.
3661
                                                              (line 141)
3662
* debug interface configuration:         Debug Interface Configuration.
3663
                                                              (line   6)
3664
* debug mode toggle (Interactive CLI):   Interactive Command Line.
3665
                                                              (line 151)
3666
* debug unit configuration:              Debug Interface Configuration.
3667
                                                              (line   6)
3668
* Debug Unit verification (VAPI):        Verification API.    (line  34)
3669
* debugging enabled (Argtable2):         Configuring the Build.
3670 127 jeremybenn
                                                              (line  98)
3671 104 jeremybenn
* DejaGnu board configurations:          Regression Testing.  (line  35)
3672
* DejaGnu configuration:                 Regression Testing.  (line  21)
3673
* DejaGNU tests directories:             Regression Testing.  (line  50)
3674
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
3675 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
3676 240 julius
                                                              (line 138)
3677 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
3678 240 julius
                                                              (line 144)
3679 98 jeremybenn
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
3680 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
3681
                                                              (line  36)
3682
* disassemble (Interactive CLI):         Interactive Command Line.
3683
                                                              (line  41)
3684
* disc interface configuration:          Disc Interface Configuration.
3685
                                                              (line   6)
3686
* disc interface device configuration:   Disc Interface Configuration.
3687
                                                              (line  88)
3688
* display interface configuration:       Display Interface Configuration.
3689
                                                              (line   6)
3690
* displaying memory (Interactive CLI):   Interactive Command Line.
3691
                                                              (line  31)
3692
* displaying registers (Interactive CLI): Interactive Command Line.
3693
                                                              (line  14)
3694
* dm (Interactive CLI):                  Interactive Command Line.
3695
                                                              (line  31)
3696
* dma (Ethernet configuration):          Ethernet Configuration.
3697 240 julius
                                                              (line  43)
3698 19 jeremybenn
* DMA configuration:                     DMA Configuration.   (line   6)
3699
* DMA verification (VAPI):               Verification API.    (line  73)
3700
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
3701
                                                              (line  70)
3702
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3703
                                                              (line  71)
3704
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
3705
                                                              (line  69)
3706
* DME (power management register):       Power Management Configuration.
3707
                                                              (line  15)
3708
* DMMU configuration:                    Memory Management Configuration.
3709
                                                              (line   6)
3710
* doze mode (power management register): Power Management Configuration.
3711
                                                              (line  15)
3712
* dv (Interactive CLI):                  Interactive Command Line.
3713
                                                              (line 124)
3714
* dynamic clock gating (power management register): Power Management Configuration.
3715
                                                              (line  21)
3716
* dynamic model:                         Configuring the Build.
3717 104 jeremybenn
                                                              (line  37)
3718 19 jeremybenn
* dynamic ports, use of:                 Verification API Configuration.
3719
                                                              (line  23)
3720
* edge_trigger (interrupt controller):   Interrupt Configuration.
3721
                                                              (line  16)
3722
* enable_bursts (CUC configuration):     CUC Configuration.   (line  38)
3723
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
3724
                                                              (line  18)
3725
* enabled (branch prediction configuration): Branch Prediction Configuration.
3726
                                                              (line  15)
3727
* enabled (cache configuration):         Cache Configuration. (line  11)
3728
* enabled (debug interface configuration): Debug Interface Configuration.
3729
                                                              (line  11)
3730
* enabled (DMA configuration):           DMA Configuration.   (line  20)
3731
* enabled (Ethernet configuration):      Ethernet Configuration.
3732
                                                              (line  18)
3733
* enabled (frame buffer configuration):  Frame Buffer Configuration.
3734
                                                              (line  16)
3735
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
3736
                                                              (line  18)
3737
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
3738
* enabled (interrupt controller):        Interrupt Configuration.
3739
                                                              (line  12)
3740
* enabled (keyboard configuration):      Keyboard Configuration.
3741
                                                              (line  32)
3742
* enabled (memory controller configuration): Memory Controller Configuration.
3743 98 jeremybenn
                                                              (line  35)
3744 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
3745
                                                              (line  12)
3746
* enabled (power management configuration): Power Management Configuration.
3747
                                                              (line  35)
3748
* enabled (UART configuration):          UART Configuration.  (line  18)
3749
* enabled (verification API configuration): Verification API Configuration.
3750
                                                              (line  15)
3751
* enabled (VGA configuration):           Display Interface Configuration.
3752
                                                              (line  22)
3753
* enabling Ethernet via socket:          Configuring the Build.
3754 104 jeremybenn
                                                              (line  59)
3755 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
3756
                                                              (line  32)
3757
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
3758
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
3759
* Ethernet configuration:                Ethernet Configuration.
3760
                                                              (line   6)
3761
* Ethernet verification (VAPI):          Verification API.    (line  78)
3762
* Ethernet via socket, enabling:         Configuring the Build.
3763 104 jeremybenn
                                                              (line  59)
3764 127 jeremybenn
* exclusive-OR immediate operand:        Configuring the Build.
3765
                                                              (line  69)
3766 202 julius
* exe_bin_insn_log (simulator configuration): Simulator Behavior.
3767
                                                              (line 103)
3768
* exe_bin_insn_log_file (simulator configuration): Simulator Behavior.
3769
                                                              (line 111)
3770 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
3771
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
3772
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
3773 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
3774 82 jeremybenn
                                                              (line  97)
3775 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
3776 82 jeremybenn
                                                              (line  93)
3777 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
3778 82 jeremybenn
                                                              (line  86)
3779
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
3780 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
3781 82 jeremybenn
                                                              (line  58)
3782 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
3783 82 jeremybenn
                                                              (line  62)
3784 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
3785 82 jeremybenn
                                                              (line  69)
3786 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
3787 82 jeremybenn
                                                              (line  74)
3788 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
3789
                                                              (line  23)
3790
* execution history (Interactive CLI):   Interactive Command Line.
3791
                                                              (line  67)
3792
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
3793
                                                              (line 104)
3794
* file (keyboard configuration):         Keyboard Configuration.
3795
                                                              (line  51)
3796
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
3797 82 jeremybenn
                                                              (line  36)
3798 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
3799
                                                              (line  47)
3800
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
3801
                                                              (line 117)
3802
* flag setting by instructions:          Configuring the Build.
3803 127 jeremybenn
                                                              (line 118)
3804 104 jeremybenn
* floating point multiply and add:       Known Issues.        (line  56)
3805
* floating point support:                Known Issues.        (line  42)
3806 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
3807
                                                              (line   6)
3808
* generic peripheral configuration:      Generic Peripheral Configuration.
3809
                                                              (line   6)
3810
* GPIO configuration:                    GPIO Configuration.  (line   6)
3811
* GPIO verification (VAPI):              Verification API.    (line  88)
3812
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
3813
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
3814
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
3815
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
3816
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
3817
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
3818
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
3819 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
3820 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
3821 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
3822
                                                              (line 121)
3823
* help (Interactive CLI):                Interactive Command Line.
3824
                                                              (line 170)
3825
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
3826
                                                              (line 133)
3827
* hide_device_id (verification API configuration): Verification API Configuration.
3828
                                                              (line  36)
3829
* hist (Interactive CLI):                Interactive Command Line.
3830
                                                              (line  67)
3831 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
3832 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
3833
                                                              (line  67)
3834
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
3835
                                                              (line  33)
3836
* hitdelay (instruction cache configuration): Cache Configuration.
3837
                                                              (line  38)
3838
* hitdelay (MMU configuration):          Memory Management Configuration.
3839
                                                              (line  51)
3840 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
3841 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3842
                                                              (line  49)
3843
* IMMU configuration:                    Memory Management Configuration.
3844
                                                              (line   6)
3845
* index (memory controller configuration): Memory Controller Configuration.
3846 98 jeremybenn
                                                              (line  68)
3847 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
3848
                                                              (line 119)
3849
* installing Or1ksim:                    Installation.        (line   6)
3850
* instruction cache configuration:       Cache Configuration. (line   6)
3851
* instruction MMU configuration:         Memory Management Configuration.
3852
                                                              (line   6)
3853
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
3854
* instruction profiling utility (Interactive CLI): Interactive Command Line.
3855
                                                              (line 178)
3856
* internal debugging:                    Internal Debugging.  (line   6)
3857
* interrupt controller configuration:    Interrupt Configuration.
3858
                                                              (line   6)
3859
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
3860
                                                              (line  32)
3861
* irq (DMA configuration):               DMA Configuration.   (line  34)
3862
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
3863
* irq (keyboard configuration):          Keyboard Configuration.
3864
                                                              (line  47)
3865
* irq (UART configuration):              UART Configuration.  (line  70)
3866
* irq (VGA configuration):               Display Interface Configuration.
3867
                                                              (line  37)
3868
* jitter (UART configuration):           UART Configuration.  (line  78)
3869
* keyboard configuration:                Keyboard Configuration.
3870
                                                              (line   6)
3871 104 jeremybenn
* lf.madd.s:                             Known Issues.        (line  56)
3872 19 jeremybenn
* library version of Or1ksim:            Simulator Library.   (line   6)
3873
* license for Or1ksim:                   GNU Free Documentation License.
3874
                                                              (line   6)
3875
* list breakpoints (Interactive CLI):    Interactive Command Line.
3876
                                                              (line  60)
3877
* load_hitdelay (data cache configuration): Cache Configuration.
3878
                                                              (line  46)
3879
* load_missdelay (data cache configuration): Cache Configuration.
3880
                                                              (line  50)
3881
* log (memory configuration):            Memory Configuration.
3882 240 julius
                                                              (line 150)
3883 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
3884
                                                              (line  28)
3885 93 jeremybenn
* long:                                  Simulator Library.   (line  87)
3886 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
3887 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
3888 240 julius
                                                              (line 127)
3889 19 jeremybenn
* memory configuration:                  Memory Configuration.
3890
                                                              (line   6)
3891
* memory controller configuration:       Memory Controller Configuration.
3892
                                                              (line   6)
3893
* memory copying (Interactive CLI):      Interactive Command Line.
3894
                                                              (line  54)
3895
* memory display (Interactive CLI):      Interactive Command Line.
3896
                                                              (line  31)
3897
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
3898
                                                              (line 133)
3899
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
3900
                                                              (line 124)
3901
* memory patching (Interactive CLI):     Interactive Command Line.
3902
                                                              (line  48)
3903
* memory profiling end address:          Memory Profiling Utility.
3904
                                                              (line  56)
3905
* memory profiling start address:        Memory Profiling Utility.
3906
                                                              (line  56)
3907
* memory profiling utility (Interactive CLI): Interactive Command Line.
3908
                                                              (line 173)
3909
* memory profiling version of Or1ksim:   Memory Profiling Utility.
3910
                                                              (line   6)
3911
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
3912
* memory_order=exact (CUC configuration): CUC Configuration.  (line  27)
3913
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
3914
* memory_order=strong (CUC configuration): CUC Configuration. (line  25)
3915
* memory_order=weak (CUC configuration): CUC Configuration.   (line  21)
3916
* missdelay (branch prediction configuration): Branch Prediction Configuration.
3917
                                                              (line  37)
3918
* missdelay (instruction cache configuration): Cache Configuration.
3919
                                                              (line  42)
3920
* missdelay (MMU configuration):         Memory Management Configuration.
3921
                                                              (line  55)
3922
* MMU configuration:                     Memory Management Configuration.
3923
                                                              (line   6)
3924 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
3925 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
3926 82 jeremybenn
                                                              (line  34)
3927 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
3928 240 julius
                                                              (line 178)
3929 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
3930 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
3931
                                                              (line 128)
3932
* name (generic peripheral configuration): Generic Peripheral Configuration.
3933
                                                              (line  42)
3934
* name (memory configuration):           Memory Configuration.
3935 240 julius
                                                              (line 109)
3936 19 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  42)
3937
* nsets (cache configuration):           Cache Configuration. (line  15)
3938
* nsets (MMU configuration):             Memory Management Configuration.
3939
                                                              (line  16)
3940
* nways (cache configuration):           Cache Configuration. (line  22)
3941
* nways (MMU configuration):             Memory Management Configuration.
3942
                                                              (line  22)
3943 93 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  77)
3944
* or1ksim_init:                          Simulator Library.   (line  14)
3945
* or1ksim_interrupt:                     Simulator Library.   (line  92)
3946
* or1ksim_interrupt_clear:               Simulator Library.   (line 110)
3947
* or1ksim_interrupt_set:                 Simulator Library.   (line 101)
3948
* or1ksim_is_le:                         Simulator Library.   (line  82)
3949 104 jeremybenn
* or1ksim_jtag_reset:                    Simulator Library.   (line 119)
3950
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 141)
3951
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 127)
3952 93 jeremybenn
* or1ksim_reset_duration:                Simulator Library.   (line  62)
3953
* or1ksim_run:                           Simulator Library.   (line  57)
3954
* or1ksim_set_time_point:                Simulator Library.   (line  73)
3955 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
3956
* overflow flag setting by instructions: Configuring the Build.
3957 127 jeremybenn
                                                              (line 133)
3958 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
3959
                                                              (line 113)
3960
* pagesize (MMU configuration):          Memory Management Configuration.
3961
                                                              (line  27)
3962
* patching memory (Interactive CLI):     Interactive Command Line.
3963
                                                              (line  48)
3964
* patching registers (Interactive CLI):  Interactive Command Line.
3965
                                                              (line  28)
3966
* patching the program counter (Interactive CLI): Interactive Command Line.
3967
                                                              (line  51)
3968
* pattern (memory configuration):        Memory Configuration.
3969 240 julius
                                                              (line  76)
3970 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
3971
                                                              (line  51)
3972
* PIC configuration:                     Interrupt Configuration.
3973
                                                              (line   6)
3974
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
3975
                                                              (line 132)
3976
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
3977
                                                              (line  51)
3978
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
3979
                                                              (line  52)
3980
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
3981
                                                              (line  53)
3982
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3983
                                                              (line  54)
3984
* pm (Interactive CLI):                  Interactive Command Line.
3985
                                                              (line  48)
3986
* PMR - DGCE:                            Power Management Configuration.
3987
                                                              (line  21)
3988
* PMR - DME:                             Power Management Configuration.
3989
                                                              (line  15)
3990
* PMR - SDF:                             Power Management Configuration.
3991
                                                              (line  12)
3992
* PMR - SME:                             Power Management Configuration.
3993
                                                              (line  16)
3994
* PMR - SUME:                            Power Management Configuration.
3995
                                                              (line  24)
3996
* PMU configuration:                     Power Management Configuration.
3997
                                                              (line   6)
3998
* poc (memory controller configuration): Memory Controller Configuration.
3999 98 jeremybenn
                                                              (line  55)
4000 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4001
                                                              (line  23)
4002
* power management configuration:        Power Management Configuration.
4003
                                                              (line   6)
4004
* power management register, DGCE:       Power Management Configuration.
4005
                                                              (line  21)
4006
* power management register, DME:        Power Management Configuration.
4007
                                                              (line  15)
4008
* power management register, SDF:        Power Management Configuration.
4009
                                                              (line  12)
4010
* power management register, SME:        Power Management Configuration.
4011
                                                              (line  16)
4012
* power management register, SUME:       Power Management Configuration.
4013
                                                              (line  24)
4014
* pr (Interactive CLI):                  Interactive Command Line.
4015
                                                              (line  28)
4016
* private ports, use of:                 Verification API Configuration.
4017
                                                              (line  23)
4018
* processor configuration:               CPU Configuration.   (line   6)
4019
* processor stall (Interactive CLI):     Interactive Command Line.
4020
                                                              (line  72)
4021
* processor unstall (Interactive CLI):   Interactive Command Line.
4022
                                                              (line  78)
4023
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4024
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4025
                                                              (line  23)
4026
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4027
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4028
* profiling utility (Interactive CLI):   Interactive Command Line.
4029
                                                              (line 178)
4030
* program counter patching (Interactive CLI): Interactive Command Line.
4031
                                                              (line  51)
4032
* programmable interrupt controller configuration: Interrupt Configuration.
4033
                                                              (line   6)
4034
* PS2 configuration:                     Keyboard Configuration.
4035
                                                              (line   6)
4036
* q (Interactive CLI):                   Interactive Command Line.
4037
                                                              (line  11)
4038
* quitting (Interactive CLI):            Interactive Command Line.
4039
                                                              (line  11)
4040
* r (Interactive CLI):                   Interactive Command Line.
4041
                                                              (line  14)
4042
* random_seed (memory configuration):    Memory Configuration.
4043 240 julius
                                                              (line  66)
4044 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4045 82 jeremybenn
                                                              (line  30)
4046 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4047
                                                              (line  41)
4048
* reg_sim_reset:                         Concepts.            (line  13)
4049
* register display (Interactive CLI):    Interactive Command Line.
4050
                                                              (line  14)
4051
* register over time statistics:         Configuring the Build.
4052 127 jeremybenn
                                                              (line  92)
4053 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4054
                                                              (line  28)
4055 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4056 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4057
                                                              (line  20)
4058 235 jeremybenn
* Remote Serial Protocol, --nosrv:       Standalone Simulator.
4059
                                                              (line  32)
4060
* Remote Serial Protocol, --srv:         Standalone Simulator.
4061
                                                              (line  40)
4062 19 jeremybenn
* reset (Interactive CLI):               Interactive Command Line.
4063
                                                              (line  63)
4064
* reset hooks:                           Concepts.            (line  13)
4065
* reset the simulator (Interactive CLI): Interactive Command Line.
4066
                                                              (line  63)
4067
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4068
                                                              (line  44)
4069
* rev (CPU configuration):               CPU Configuration.   (line  15)
4070
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4071
                                                              (line  20)
4072
* rsp_port (debug interface configuration): Debug Interface Configuration.
4073 235 jeremybenn
                                                              (line  32)
4074 19 jeremybenn
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4075
                                                              (line  46)
4076
* run (Interactive CLI):                 Interactive Command Line.
4077
                                                              (line  23)
4078
* running code (Interactive CLI):        Interactive Command Line.
4079
                                                              (line  23)
4080
* running Or1ksim:                       Usage.               (line   6)
4081
* runtime:                               Global Data Structures.
4082
                                                              (line  58)
4083
* runtime global structure:              Global Data Structures.
4084
                                                              (line  58)
4085
* runtime.cpu:                           Global Data Structures.
4086
                                                              (line  62)
4087
* runtime.cpu.fout:                      Concepts.            (line   7)
4088
* runtime.cuc:                           Global Data Structures.
4089
                                                              (line  62)
4090
* runtime.vapi:                          Global Data Structures.
4091
                                                              (line  62)
4092
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4093
                                                              (line  59)
4094
* rxfile (Ethernet configuration):       Ethernet Configuration.
4095
                                                              (line  68)
4096
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4097
                                                              (line  23)
4098
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4099
                                                              (line  28)
4100 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4101 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4102
                                                              (line  12)
4103
* section ata:                           Disc Interface Configuration.
4104
                                                              (line   6)
4105
* section bpb:                           Branch Prediction Configuration.
4106
                                                              (line   6)
4107
* section cpio:                          GPIO Configuration.  (line   6)
4108
* section cpu:                           CPU Configuration.   (line   6)
4109
* section cuc:                           CUC Configuration.   (line   6)
4110
* section dc:                            Cache Configuration. (line   6)
4111
* section debug:                         Debug Interface Configuration.
4112
                                                              (line   6)
4113
* section dma:                           DMA Configuration.   (line   6)
4114
* section dmmu:                          Memory Management Configuration.
4115
                                                              (line   6)
4116
* section ethernet:                      Ethernet Configuration.
4117
                                                              (line   6)
4118
* section fb:                            Frame Buffer Configuration.
4119
                                                              (line   6)
4120
* section generic:                       Generic Peripheral Configuration.
4121
                                                              (line   6)
4122
* section ic:                            Cache Configuration. (line   6)
4123
* section immu:                          Memory Management Configuration.
4124
                                                              (line   6)
4125
* section kb:                            Keyboard Configuration.
4126
                                                              (line   6)
4127
* section mc:                            Memory Controller Configuration.
4128
                                                              (line   6)
4129
* section memory:                        Memory Configuration.
4130
                                                              (line   6)
4131
* section pic:                           Interrupt Configuration.
4132
                                                              (line   6)
4133
* section pmu:                           Power Management Configuration.
4134
                                                              (line   6)
4135
* section sim:                           Simulator Behavior.  (line   6)
4136
* section uart:                          UART Configuration.  (line   6)
4137
* section vapi:                          Verification API Configuration.
4138
                                                              (line   6)
4139
* section vga:                           Display Interface Configuration.
4140
                                                              (line   6)
4141
* sections:                              Global Data Structures.
4142
                                                              (line  49)
4143
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4144
                                                              (line 125)
4145
* server_port (verification API configuration): Verification API Configuration.
4146
                                                              (line  19)
4147
* set (Interactive CLI):                 Interactive Command Line.
4148
                                                              (line 146)
4149
* set breakpoint (Interactive CLI):      Interactive Command Line.
4150
                                                              (line  57)
4151
* setdbch (Interactive CLI):             Interactive Command Line.
4152
                                                              (line 141)
4153
* simple model:                          Configuring the Build.
4154 104 jeremybenn
                                                              (line  37)
4155 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4156
* simulator configuration info (Interactive CLI): Interactive Command Line.
4157
                                                              (line 119)
4158
* simulator reset (Interactive CLI):     Interactive Command Line.
4159
                                                              (line  63)
4160
* simulator statistics (Interactive CLI): Interactive Command Line.
4161
                                                              (line  83)
4162
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4163
                                                              (line 109)
4164
* size (generic peripheral configuration): Generic Peripheral Configuration.
4165
                                                              (line  30)
4166
* size (memory configuration):           Memory Configuration.
4167 240 julius
                                                              (line  93)
4168 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4169
                                                              (line  16)
4170
* slow down factor (power management register): Power Management Configuration.
4171
                                                              (line  12)
4172
* SME (power management register):       Power Management Configuration.
4173
                                                              (line  16)
4174
* sockif (Ethernet configuration):       Ethernet Configuration.
4175
                                                              (line  83)
4176
* sr (CPU configuration):                CPU Configuration.   (line  53)
4177
* stall (Interactive CLI):               Interactive Command Line.
4178
                                                              (line  72)
4179
* stall the processor (Interactive CLI): Interactive Command Line.
4180
                                                              (line  72)
4181
* statistics, register over time:        Configuring the Build.
4182 127 jeremybenn
                                                              (line  92)
4183 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4184
                                                              (line  83)
4185
* stats (Interactive CLI):               Interactive Command Line.
4186
                                                              (line  83)
4187
* stepping code (Interactive CLI):       Interactive Command Line.
4188
                                                              (line  19)
4189
* store_hitdelay (data cache configuration): Cache Configuration.
4190
                                                              (line  54)
4191
* store_missdelay (data cache configuration): Cache Configuration.
4192
                                                              (line  58)
4193
* SUME (power management register):      Power Management Configuration.
4194
                                                              (line  24)
4195 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4196 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4197
                                                              (line  24)
4198
* t (Interactive CLI):                   Interactive Command Line.
4199
                                                              (line  19)
4200 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4201 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4202
                                                              (line  23)
4203
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4204 235 jeremybenn
                                                              (line  37)
4205 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4206
* test code for target:                  Regression Testing.  (line  63)
4207
* test make file:                        Regression Testing.  (line  27)
4208
* test README:                           Regression Testing.  (line  32)
4209
* testing:                               Regression Testing.  (line   6)
4210 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4211 127 jeremybenn
                                                              (line 105)
4212 19 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  46)
4213
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4214
                                                              (line  46)
4215
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4216
                                                              (line  57)
4217
* toggle debug channels (Interactive CLI): Interactive Command Line.
4218
                                                              (line 141)
4219
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4220
                                                              (line 151)
4221
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4222
                                                              (line  60)
4223
* txfile (Ethernet configuration):       Ethernet Configuration.
4224
                                                              (line  69)
4225
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4226 82 jeremybenn
                                                              (line  36)
4227 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4228
                                                              (line  47)
4229
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4230
                                                              (line  99)
4231
* type (memory configuration):           Memory Configuration.
4232 98 jeremybenn
                                                              (line  36)
4233 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4234 98 jeremybenn
                                                              (line  46)
4235 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4236 98 jeremybenn
                                                              (line  40)
4237 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4238 98 jeremybenn
                                                              (line  50)
4239 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4240 240 julius
                                                              (line  55)
4241 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4242
* UART I/O from/to a physical serial port: UART Configuration.
4243
                                                              (line  62)
4244
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4245
* UART I/O from/to files:                UART Configuration.  (line  33)
4246
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4247
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4248
* UART verification (VAPI):              Verification API.    (line  41)
4249
* unstall (Interactive CLI):             Interactive Command Line.
4250
                                                              (line  78)
4251
* unstall the processor (Interactive CLI): Interactive Command Line.
4252
                                                              (line  78)
4253
* upr (CPU configuration):               CPU Configuration.   (line  21)
4254
* ustates (cache configuration):         Cache Configuration. (line  33)
4255
* ustates (MMU configuration):           Memory Management Configuration.
4256
                                                              (line  41)
4257
* VAPI configuration:                    Verification API Configuration.
4258
                                                              (line   6)
4259
* VAPI for Debug Unit:                   Verification API.    (line  34)
4260
* VAPI for DMA:                          Verification API.    (line  73)
4261
* VAPI for Ethernet:                     Verification API.    (line  78)
4262
* VAPI for GPIO:                         Verification API.    (line  88)
4263
* VAPI for UART:                         Verification API.    (line  41)
4264
* vapi_id (debug interface configuration): Debug Interface Configuration.
4265 235 jeremybenn
                                                              (line  43)
4266 240 julius
* vapi_id (DMA configuration) <1>:       DMA Configuration.   (line  38)
4267
* vapi_id (DMA configuration):           Ethernet Configuration.
4268 19 jeremybenn
                                                              (line  88)
4269
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4270
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4271
* vapi_log_file (verification API configuration): Verification API Configuration.
4272
                                                              (line  41)
4273
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4274
                                                              (line  41)
4275
* ver (CPU configuration):               CPU Configuration.   (line  15)
4276
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4277
* Verification API configuration:        Verification API Configuration.
4278
                                                              (line   6)
4279
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4280
                                                              (line 124)
4281
* VGA configuration:                     Display Interface Configuration.
4282
 
4283
 
4284
                                                              (line  50)
4285
4286
4287

4288
Tag Table:
4289 240 julius
Node: Top829
4290
Node: Installation1239
4291
Node: Preparation1486
4292
Node: Configuring the Build1781
4293
Node: Build and Install7895
4294
Node: Known Issues8741
4295
Node: Usage11803
4296
Node: Standalone Simulator12017
4297
Node: Profiling Utility15045
4298
Node: Memory Profiling Utility15955
4299
Node: Simulator Library17320
4300
Node: Configuration25098
4301
Node: Configuration File Format25710
4302
Node: Configuration File Preprocessing26002
4303
Node: Configuration File Syntax26299
4304
Node: Simulator Configuration29084
4305
Node: Simulator Behavior29375
4306
Node: Verification API Configuration33904
4307
Node: CUC Configuration35844
4308
Node: Core OpenRISC Configuration37761
4309
Node: CPU Configuration38263
4310
Node: Memory Configuration42381
4311
Node: Memory Management Configuration48849
4312
Node: Cache Configuration51226
4313
Node: Interrupt Configuration53612
4314
Node: Power Management Configuration54348
4315
Node: Branch Prediction Configuration55625
4316
Node: Debug Interface Configuration56985
4317
Node: Peripheral Configuration59328
4318
Node: Memory Controller Configuration59954
4319
Node: UART Configuration63368
4320
Node: DMA Configuration66887
4321
Node: Ethernet Configuration68754
4322
Node: GPIO Configuration72730
4323
Node: Display Interface Configuration74363
4324
Node: Frame Buffer Configuration76672
4325
Node: Keyboard Configuration78536
4326
Node: Disc Interface Configuration80774
4327
Node: Generic Peripheral Configuration85717
4328
Node: Interactive Command Line88012
4329
Node: Verification API94986
4330
Node: Code Internals99416
4331
Node: Coding Conventions99999
4332
Node: Global Data Structures104426
4333
Node: Concepts107083
4334
Ref: Output Redirection107228
4335
Node: Internal Debugging107767
4336
Node: Regression Testing108291
4337
Node: GNU Free Documentation License112086

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