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This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
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../../doc/or1ksim.texi.
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4
INFO-DIR-SECTION Embedded development
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START-INFO-DIR-ENTRY
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* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
7
                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 346 jeremybenn
     tar jxf or1ksim-0.5.0rc1.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
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default to OpenRISC 1000 32-bit with a warning
83
 
84 346 jeremybenn
     ../or1ksim-0.5.0rc1/configure --target=or32-uclinux ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 104 jeremybenn
For testing (using `make check'), the `--target' parameter _must_ be
92 346 jeremybenn
specified, to allow the target tool chain to be selected.  If the tools
93 104 jeremybenn
have been installed using the standard OpenRISC script, then this
94
should be set to `or32-elf'.
95 19 jeremybenn
 
96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
101 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
`--enable-execution=dynamic'
108
     Or1ksim has developed to improve functionality and performance.
109
     This feature allows three versions of Or1ksim to be built
110
 
111
    `--enable-execution=simple'
112
          Build the original simple interpreting simulator
113
 
114
    `--enable-execution=complex'
115 82 jeremybenn
          Build a more complex interpreting simulator.  Experiments
116
          suggest this is 50% faster than the simple simulator.  This
117
          is the default.
118 19 jeremybenn
 
119
    `--enable-execution=dynamic'
120 82 jeremybenn
          Build a dynamically compiling simulator.  This is the way
121
          many modern ISS are built.  This represents a work in
122
          progress.  Currently Or1ksim will compile, but segfaults if
123
          configured with this option.
124 19 jeremybenn
 
125
 
126
     The default is `--enable-execution=complex'.
127
 
128
`--enable-ethphy'
129
`--disable-ethphy'
130
     If enabled, this option allows the Ethernet to be simulated by
131
     connecting via a socket (the alternative reads and writes, from
132 82 jeremybenn
     and to files).  This must then be configured using the relevant
133
     fields in the `ethernet' section of the configuration file.  *Note
134 19 jeremybenn
     Ethernet Configuration: Ethernet Configuration.
135
 
136
     The default is for this to be disabled.
137
 
138 127 jeremybenn
`--enable-unsigned-xori'
139
`--disable-unsigned-xori'
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     Historically, `l.xori', has sign extended its operand.  This is
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     inconsistent with the other logical opcodes (`l.andi', `l.ori'),
142
     but in the absence of `l.not', it allows a register to be inverted
143
     in a single instruction using:
144
 
145
          `l.xori  rD,rA,-1'
146
 
147
     This flag causes Or1ksim to treat the immediate operand as
148
     unsigned (i.e to zero-extend rather than sign-extend).
149
 
150
     The default is to sign-extend, so that existing code will continue
151
     to work.
152
 
153
          Caution: The GNU compiler tool chain makes heavy use of this
154
          instruction.  Using unsigned behavior will require the
155
          compiler to be modified accordingly.
156
 
157
          This option is provided for experimentation.  A future
158
          version of OpenRISC may adopt this more consistent behavior
159
          and also provide a `l.not' opcode.
160
 
161 19 jeremybenn
`--enable-range-stats'
162
`--disable-range-stats'
163
     If enabled, this option allows statistics to be collected to
164 82 jeremybenn
     analyse register access over time.  The default is for this to be
165 19 jeremybenn
     disabled.
166
 
167
`--enable-debug'
168
`--disable-debug'
169
     This is a feature of the Argtable2 package used to process
170 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
171
     Argtable2.  It is provided for completeness, but there is no
172
     reason why this feature should ever be needed by any Or1ksim user.
173 19 jeremybenn
 
174 82 jeremybenn
`--enable-all-tests'
175
`--disable-all-tests'
176
     Some of the tests (at the time of writing just one) will not
177
     compile without error.  If enabled with this flag, all test
178
     programs will be compiled with `make check'.
179 19 jeremybenn
 
180 82 jeremybenn
     This flag is intended for those working on the test package, who
181
     wish to get the missing test(s) working.
182
 
183
 
184 112 jeremybenn
A number of configuration flags have been removed since version 0.3.0,
185 346 jeremybenn
because they led to invalid behavior of Or1ksim.  Those removed are:
186 112 jeremybenn
 
187 124 jeremybenn
`--enable-arith-flag'
188
`--disable-arith-flag'
189
     If enabled, this option caused certain instructions to set the flag
190
     (`F' bit) in the supervision register if the result were zero.
191
     The instructions affected by this were `l.add', `l.addc',
192
     `l.addi', `l.and' and `l.andi'.
193
 
194 346 jeremybenn
     If set, this caused incorrect behavior.  Whether or not flags are
195 124 jeremybenn
     set is part of the OpenRISC 1000 architectural specification.  The
196
     only flags which should set this are the "set flag" instructions:
197
     `l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
198
     `l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
199
     `l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
200
     `l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
201
 
202 112 jeremybenn
`--enable-ov-flag'
203
`--disable-ov-flag'
204 124 jeremybenn
     This flag caused certain instructions to set the overflow flag.
205
     If not, those instructions would not set the overflow flat.  The
206
     instructions affected by this were `l.add', `l.addc', `l.addi',
207
     `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
208
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
209
     `l.sub', `l.xor' and `l.xori'.
210 112 jeremybenn
 
211
     This guaranteed incorrect behavior.  The OpenRISC 1000 architecture
212
     specification defines which flags are set by which instructions.
213
 
214
     Within the above list, the arithmetic instructions (`l.add',
215
     `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
216
     `l.sub'), together with `l.addic' which is missed out, set the
217
     overflow flag.  All the others (`l.and', `l.andi', `l.or',
218
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
219
     `l.xor' and `l.xori') do not.
220
 
221
 
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223
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
224
 
225
1.3 Building and Installing
226
===========================
227
 
228 82 jeremybenn
Build the tool with:
229 19 jeremybenn
 
230
     make all
231 82 jeremybenn
 
232
If you have the OpenRISC tool chain and DejaGNU installed, you can
233
verify the tool as follows (otherwise omit this step):
234
 
235
     make check
236
 
237
Install the tool with:
238
 
239 19 jeremybenn
     make install
240
 
241
This will install the three variations of the Or1ksim tool,
242
`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the
243
Or1ksim library, `libsim', the header file, `or1ksim.h' and this
244
documentation in `info' format.
245
 
246
The documentation may be created and installed in alternative formats
247
(PDF, Postscript, DVI, HTML) with for example:
248
 
249
     make pdf
250
     make install-pdf
251
 
252

253
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
254
 
255
1.4 Known Problems and Issues
256
=============================
257
 
258 346 jeremybenn
Full details of outstanding issues may be found in the `NEWS' file in
259
the main directory of the distribution.  The OpenRISC tracker may be
260
used to see the current state of these issues and to raise new problems
261
and feature requests.  It may be found at bugtracker.
262 19 jeremybenn
 
263 346 jeremybenn
The following issues are long standing and unlikely to be fixed in
264
Or1ksim in the near future.
265
 
266 19 jeremybenn
   * The Supervision Register Little Endian Enable (LEE) bit is
267 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
268 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
269
 
270
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
271 82 jeremybenn
     instances using the library.  This is clearly a problem when
272
     considering multi-core applications.  However it stems from the
273
     original design, and can only be fixed by a complete rewrite.  The
274 19 jeremybenn
     entire source code uses static global constants liberally!
275
 
276
 
277

278
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
279
 
280
2 Usage
281
*******
282
 
283
* Menu:
284
 
285
* Standalone Simulator::
286
* Profiling Utility::
287
* Memory Profiling Utility::
288
* Simulator Library::
289
 
290

291
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
292
 
293
2.1 Standalone Simulator
294
========================
295
 
296
The general form the standalone command is:
297
 
298 346 jeremybenn
     or32-uclinux-sim [-vhiqV] [-f FILE] [--nosrv] [--srv=[N]]
299
                      [-m ][-d STR]
300 19 jeremybenn
                      [--enable-profile] [--enable-mprofile] [FILE]
301
 
302 82 jeremybenn
Many of the options have both a short and a long form.  For example
303
`-h' or `--help'.
304 19 jeremybenn
 
305
`-v'
306
`--version'
307
     Print out the version and copyright notice for Or1ksim and exit.
308
 
309
`-h'
310
`--help'
311
     Print out help about the command line options and what they mean.
312
 
313 346 jeremybenn
`-i'
314
`--interactive'
315
     After starting, drop into the Or1ksim interactive command shell.
316
 
317
`-q'
318
`--quiet'
319
     Do not generate any information messages, only error messages.
320
 
321
`-V'
322
`--verbose'
323
     Generate extra output messages (equivalent of specifying the
324
     "verbose" option in the simulator configuration section (see *note
325
     Simulator Behavior: Simulator Behavior.).
326
 
327 19 jeremybenn
`-f FILE'
328
`--file FILE'
329
     Read configuration commands from the specified file, looking first
330
     in the current directory, and otherwise in the `$HOME/.or1k'
331 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
332
     in those two locations is used.  Failure to find the file is a
333
     fatal error.  *Note Configuration: Configuration, for detailed
334
     information on configuring Or1ksim.
335 19 jeremybenn
 
336
`--nosrv'
337 235 jeremybenn
     Do not start up the "Remote Serial Protocol" debug server.  This
338
     overrides any setting specified in the configuration file.  This
339
     option may not be specified with `--srv'.  If it is, a rude
340
     message is printed and the `--nosrv' option is ignored.
341 19 jeremybenn
 
342
`--srv'
343
 
344
`--srv=N'
345 235 jeremybenn
     Start up the "Remote Serial Protocol" debug server.  This
346
     overrides any setting specified in the configuration file.  If the
347
     parameter, N, is specified, use that as the TCP/IP port for the
348
     server, otherwise a random value from the private port range
349
     (41920-65535) will be used.  This option may not be specified with
350
     `--nosrv'.  If it is, a rude message is printed and the `--nosrv'
351
     option is ignored.
352 19 jeremybenn
 
353 346 jeremybenn
`-m=SIZE'
354
`--memory=SIZE'
355
     Configure a memory block of SIZE bytes, starting at address zero.
356
     The size may be followed by `k', `K', `m', `M', `g', `G', to
357
     indicate kilobytes (2^10 bytes), megabytes (2^20 bytes) and
358
     gigabytes (2^30 bytes).
359
 
360
     This is mainly intended for use when Or1ksim is used without a
361
     configuration file, to allow just the processor and memory to be
362
     set up.  This is the equivalent of specifying a configuration
363
     memory section with `baseaddr = 0' and `size = SIZE' and all other
364
     parameters taking their default value.
365
 
366
     If a configuration file is also used, it should be sure not to
367
     specify an overlapping memory block.
368
 
369 19 jeremybenn
`-d=CONFIG_STRING'
370
`--debug-config=CONFIG_STRING'
371 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
372
     use by developers only, and is not covered further here.  See the
373 19 jeremybenn
     source code for more details.
374
 
375 346 jeremybenn
`--report-memory-errors'
376
     By default all exceptions are now handled silently.  If this
377
     option is specified, bus exceptions will be reported with a
378
     message to standard error indicating the address at which the
379
     exception occurred.
380 19 jeremybenn
 
381 346 jeremybenn
     This was the default behaviour up to Or1ksim 0.4.0.  This flag is
382
     provided for those who wish to keep that behavior.
383
 
384 19 jeremybenn
`--strict-npc'
385
     In real hardware, setting the next program counter (NPC, SPR 16),
386 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
387
     until the pipeline refills, reading the NPC will return zero.
388
     This is typically the case when debugging, since the processor is
389 19 jeremybenn
     stalled.
390
 
391
     Historically, Or1ksim has always returned the value of the NPC,
392 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
393
     is used, then Or1ksim will mirror real hardware more accurately.
394
     If the NPC is changed while the processor is stalled, subsequent
395 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
396
 
397
     This is not currently the default behavior, since tools such as
398
     GDB have been implemented assuming the historic Or1ksim behavior.
399
     However at some time in the future it will become the default.
400
 
401
`--enable-profile'
402
     Enable instruction profiling.
403
 
404
`--enable-mprofile'
405
     Enable memory profiling.
406
 
407
 
408

409
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
410
 
411
2.2 Profiling Utility
412
=====================
413
 
414 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
415
It may be invoked as a standalone command, or from the Or1ksim CLI.
416
The general form the standalone command is:
417 19 jeremybenn
 
418
     or32-uclinux-profile [-vhcq] [-g=FILE]
419
 
420 82 jeremybenn
Many of the options have both a short and a long form.  For example
421
`-h' or `--help'.
422 19 jeremybenn
 
423
`-v'
424
`--version'
425
     Print out the version and copyright notice for the Or1ksim
426
     profiling utility and exit.
427
 
428
`-h'
429
`--help'
430
     Print out help about the command line options and what they mean.
431
 
432
`-c'
433
`--cumulative'
434
     Show cumulative sum of cycles in functions
435
 
436
`-q'
437
`--quiet'
438
     Suppress messages
439
 
440
`-g=FILE'
441
`--generate=FILE'
442 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
443 19 jeremybenn
     `sim.profile' is used.
444
 
445
 
446

447
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Simulator Library,  Prev: Profiling Utility,  Up: Usage
448
 
449
2.3 Memory Profiling Utility
450
============================
451
 
452 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
453
be invoked as a standalone command, or from the Or1ksim CLI.  The
454 19 jeremybenn
general form the standalone command is:
455
 
456
     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
457
 
458 82 jeremybenn
Many of the options have both a short and a long form.  For example
459
`-h' or `--help'.
460 19 jeremybenn
 
461
`-v'
462
`--version'
463
     Print out the version and copyright notice for the Or1ksim memory
464
     profiling utility and exit.
465
 
466
`-h'
467
`--help'
468
     Print out help about the command line options and what they mean.
469
 
470
`-m=M'
471
`--mode=M'
472 82 jeremybenn
     Specify the mode out output.  Permitted options are
473 19 jeremybenn
 
474
    `detailed'
475
    `d'
476 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
477 19 jeremybenn
 
478
    `pretty'
479
    `p'
480
          Pretty printed output.
481
 
482
    `access'
483
    `a'
484
          Memory accesses only.
485
 
486
    `width'
487
    `w'
488
          Access width only.
489
 
490
 
491
`-g=N'
492
`--group=N'
493
     Group 2^n bits of successive addresses together.
494
 
495
`-f=FILE'
496
`--filename=FILE'
497 82 jeremybenn
     The data file to analyse.  If not specified, the default,
498 19 jeremybenn
     `sim.profile' is used.
499
 
500
`FROM'
501
`TO'
502
     FROM and TO are respectively the start and end address of the
503
     region of memory to be analysed.
504
 
505
 
506

507
File: or1ksim.info,  Node: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
508
 
509
2.4 Simulator Library
510
=====================
511
 
512
Or1ksim may be used as a static of dynamic library, `libsim.a' or
513 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
514 19 jeremybenn
should be added to the link command.
515
 
516
The header file `or1ksim.h' contains appropriate declarations of the
517 82 jeremybenn
functions exported by the Or1ksim library.  These are:
518 19 jeremybenn
 
519 346 jeremybenn
 -- `or1ksim.h': int or1ksim_init (int ARGC, char *ARGV, void
520
          *CLASS_PTR,
521
     int (*UPR)(void *CLASS_PTR, unsigned long int ADDR, unsigned char
522 93 jeremybenn
     MASK[], unsigned char RDATA[], int DATA_LEN), int (*UPW)(void
523
     *CLASS_PTR, unsigned long int ADDR, unsigned char MASK[], unsigned
524
     char WDATA[], int DATA_LEN))
525
 
526 346 jeremybenn
     The initialization function is supplied with a vector of arguments,
527
     which are interpreted as arguments to the standalone version (see
528
     *note Standalone Simulator: Standalone Simulator.), a pointer to
529
     the calling class, CLASS_PTR (since the library may be used from
530
     C++) and two up-call functions, one for reads, UPR, and one for
531
     writes, UPW.
532 19 jeremybenn
 
533
     UPW is called for any write to an address external to the model
534 82 jeremybenn
     (determined by a `generic' section in the configuration file).
535
     UPR is called for any reads to an external address.  The CLASS_PTR
536
     is passed back with these upcalls, allowing the function to
537
     associate the call with the class which originally initialized the
538 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
539
     non-zero otherwise.  At the present time the meaning of non-zero
540
     values is not defined but this may change in the future.
541 19 jeremybenn
 
542 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
543 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
544 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
545
     address, since the upcall function must handle all generic
546
     devices, using the full address for decoding.
547 19 jeremybenn
 
548 346 jeremybenn
     Endianness is not a concern, since Or1ksim is transferring byte
549
     vectors, not multi-byte values.
550 19 jeremybenn
 
551 346 jeremybenn
     The result indicates whether the initialization was successful.
552
     The integer values are available as an `enum or1ksim', with
553
     possible values `OR1KSIM_RC_OK' and `OR1KSIM_RC_BADINIT'.
554 19 jeremybenn
 
555 346 jeremybenn
          Caution: This is a change from versions 0.3.0 and 0.4.0.  It
556
          further simplifies the interface, and makes Or1ksim more
557
          consistent with payload representation in SystemC TLM 2.0.
558
 
559 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
560
          single words (4 bytes), using masks if smaller values are
561
          required.  In this it mimcs the behavior of the WishBone bus.
562
 
563
 
564 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
565
     Run the simulator for the simulated duration specified (in
566 346 jeremybenn
     seconds).  A duration of -1 indicates `run forever'
567 19 jeremybenn
 
568 346 jeremybenn
     The result indicates how the run terminated.  The integer values
569
     are available as an `enum or1ksim', with possible values
570
     `OR1KSIM_RC_OK' (ran for the full duration), `OR1KSIM_RC_BRKPT'
571
     (terminated early due to hitting a breakpoint) and
572
     `OR1KSIM_RC_HALTED' (terminated early due to hitting `l.nop 1').
573 19 jeremybenn
 
574 346 jeremybenn
 
575 19 jeremybenn
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
576
     Change the duration of a run specified in an earlier call to
577 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
578 19 jeremybenn
     realizes it needs to change the duration of the run specified in
579
     the call to `or1ksim_run' that has been interrupted by the upcall.
580
 
581
     The time specified is the amount of time that the run must continue
582
     for (i.e the duration from _now_, not the duration from the
583
     original call to `or1ksim_run').
584
 
585
 
586
 -- `or1ksim.h': void or1ksim_set_time_point ()
587 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
588 19 jeremybenn
 
589
 
590
 -- `or1ksim.h': double or1ksim_get_time_period ()
591
     Return the simulated time (in seconds) that has elapsed since the
592
     last call to `or1ksim_set_time_point'.
593
 
594
 
595
 -- `or1ksim.h': int or1ksim_is_le ()
596
     Return 1 (logical true) if the Or1ksim simulation is
597
     little-endian, 0 otherwise.
598
 
599
 
600
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
601 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
602
     specified in the configuration file.
603 19 jeremybenn
 
604
 
605
 -- `or1ksim.h': void or1ksim_interrupt (int I)
606 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
607
     interrupt is then immediately cleared automatically.  A warning
608 19 jeremybenn
     will be generated and the interrupt request ignored if level
609
     sensitive interrupts have been configured with the programmable
610
     interrupt controller (*note Interrupt Configuration: Interrupt
611
     Configuration.).
612
 
613
 
614
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
615 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
616 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
617 82 jeremybenn
     `or1ksim_interrupt_clear'.  A warning will be generated, and the
618 19 jeremybenn
     interrupt request ignored if edge sensitive interrupts have been
619
     configured with the programmable interrupt controller (*note
620
     Interrupt Configuration: Interrupt Configuration.).
621
 
622
 
623
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
624
     Clear a level-triggered interrupt on interrupt line I, which was
625 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
626 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
627
     edge sensitive interrupts have been configured with the
628
     programmable interrupt controller (*note Interrupt Configuration:
629
     Interrupt Configuration.).
630
 
631
 
632 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
633 346 jeremybenn
     Drive a reset sequence through the JTAG interface.  Return the
634 104 jeremybenn
     (model) time taken for this action.  Remember that the JTAG has
635
     its own clock, which can be an order of magnitude slower than the
636
     main clock, so even a reset (5 JTAG cycles) could take 50
637
     processor clock cycles to complete.
638
 
639
 
640
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned
641
     char *JREG, int NUM_BITS)
642
 
643
     Shift the supplied register through the JTAG instruction register.
644 346 jeremybenn
     Return the (model) time taken for this action.  The register is
645 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
646
     least significant byte.  If the total number of bits is not an
647
     exact number of bytes, then the odd bits are found in the least
648
     significant end of the highest numbered byte.
649
 
650
     For example a 12-bit register would have bits 0-7 in byte 0 and
651
     bits 11-8 in the least significant 4 bits of byte 1.
652
 
653
 
654
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned
655
     char *JREG, int NUM_BITS)
656
 
657
     Shift the supplied register through the JTAG data register.
658 346 jeremybenn
     Return the (model) time taken for this action.  The register is
659 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
660
     least significant byte.  If the total number of bits is not an
661
     exact number of bytes, then the odd bits are found in the least
662
     significant end of the highest numbered byte.
663
 
664
     For example a 12-bit register would have bits 0-7 in byte 0 and
665
     bits 11-8 in the least significant 4 bits of byte 1.
666
 
667
 
668 346 jeremybenn
 -- `or1ksim.h': int or1ksim_read_mem (unsigned
669
     long int ADDR, unsigned char *BUF, int LEN)
670
 
671
     Read LEN bytes from ADDR, placing the result in BUF.  Return LEN
672
     on success and 0 on failure.
673
 
674
          Note: This function was added in Or1ksim 0.5.0.
675
 
676
 
677
 -- `or1ksim.h': int or1ksim_write_mem (unsigned
678
     long int ADDR, unsigned char *BUF, int LEN)
679
 
680
     Write LEN bytes to ADDR, taking the data from BUF.  Return LEN on
681
     success and 0 on failure.
682
 
683
          Note: This function was added in Or1ksim 0.5.0.
684
 
685
 
686
 -- `or1ksim.h': int or1ksim_read_spr (int SPRNUM, unsigned
687
     long int *SPRVAL_PTR)
688
 
689
     Read the SPR specified by SPRNUM, placing the result in
690
     SPRVAL_PTR.  Return non-zero on success and 0 on failure.
691
 
692
          Note: This function was added in Or1ksim 0.5.0.
693
 
694
 
695
 -- `or1ksim.h': int or1ksim_write_spr (int SPRNUM, unsigned
696
     long int SPRVA)
697
 
698
     Write SPRVAL to the SPR specified by SPRNUM.  Return non-zero on
699
     success and 0 on failure.
700
 
701
          Note: This function was added in Or1ksim 0.5.0.
702
 
703
 
704
 -- `or1ksim.h': int or1ksim_read_reg (int REGNUM, unsigned
705
     long int *REGVAL_PTR)
706
 
707
     Read the general purpose register specified by REGNUM, placing the
708
     result in REGVAL_PTR.  Return non-zero on success and 0 on failure.
709
 
710
          Note: This function was added in Or1ksim 0.5.0.
711
 
712
 
713
 -- `or1ksim.h': int or1ksim_write_reg (int REGNUM, unsigned
714
     long int REGVA)
715
 
716
     Write REGVAL to the general purpose register specified by REGNUM.
717
     Return non-zero on success and 0 on failure.
718
 
719
          Note: This function was added in Or1ksim 0.5.0.
720
 
721
 
722
 -- `or1ksim.h': void or1ksim_set_stall_state (int
723
     STATE)
724
 
725
     Set the processor's state according to STATE (1 = stalled, 0 = not
726
     stalled).
727
 
728
          Note: This function was added in Or1ksim 0.5.0.
729
 
730
 
731 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
732
installation directory (as specified with the `--prefix' option to the
733
`configure' script).
734
 
735
For example if the main installation directory is `/opt/or1ksim', the
736 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
737 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
738
(`libsim.so').
739
 
740
To link against the library add the `-lsim' flag when linking and do
741
one of the following:
742
 
743
   * Add the library directory to the `LD_LIBRARY_PATH' environment
744 82 jeremybenn
     variable during execution.  For example:
745 19 jeremybenn
 
746
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
747
 
748
   * Add the library directory to the `LD_RUN_PATH' environment
749 82 jeremybenn
     variable during linking.  For example:
750 19 jeremybenn
 
751
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
752
 
753
   * Use the linker `--rpath' option and specify the library directory
754 82 jeremybenn
     when linking your program.  For example
755 19 jeremybenn
 
756 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
757 19 jeremybenn
 
758
   * Add the library directory to `/etc/ld.so.conf'
759
 
760
 
761

762
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
763
 
764
3 Configuration
765
***************
766
 
767 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
768 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
769 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
770
the default `sim.cfg' is used.  The file is looked for first in the
771 224 jeremybenn
current directory, then in the `$HOME/.or1ksim' directory of the user.
772 19 jeremybenn
 
773
* Menu:
774
 
775
* Configuration File Format::
776
* Simulator Configuration::
777
* Core OpenRISC Configuration::
778
* Peripheral Configuration::
779
 
780

781
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
782
 
783
3.1 Configuration File Format
784
=============================
785
 
786 346 jeremybenn
The configuration file is a plain text file.  A reference example,
787
`sim.cfg', is included in the top level directory of the distribution.
788 19 jeremybenn
 
789
* Menu:
790
 
791
* Configuration File Preprocessing::
792
* Configuration File Syntax::
793
 
794

795
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
796
 
797
3.1.1 Configuration File Preprocessing
798
--------------------------------------
799
 
800 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
801 19 jeremybenn
`/*' and `*/').
802
 
803

804
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
805
 
806
3.1.2 Configuration File Syntax
807
-------------------------------
808
 
809
The configuration file is divided into a series of sections, with the
810
general form:
811
 
812
     section SECTION_NAME
813
 
814
       ...
815
 
816
     end
817
 
818
Sections may also have sub-sections within them (currently only the
819
ATA/ATAPI disc interface uses this).
820
 
821
Within a section, or sub-section are a series of parameter assignments,
822
one per line, withe the general form
823
 
824
       PARAMETER = VALUE
825
 
826
Depending on the parameter, the value may be a named value (an
827
enumeration), an integer (specified in any format acceptable in C) or a
828 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
829
mean "true" or "on" and the value "0" to mean "false" or "off".  An
830 19 jeremybenn
example from a memory section shows each of these
831
 
832
     section memory
833
       type    = random
834
       pattern = 0x00
835
       name    = "FLASH"
836
       ...
837
     end
838
 
839
Many parameters are optional and take reasonable default values if not
840 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
841 19 jeremybenn
parameter in `section memory') _must_ be specified.
842
 
843
Subsections are introduced by a keyword, with a parameter value (no `='
844 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
845 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
846
 
847
     section ata
848
       ...
849
       device 0
850
         type    = 1
851
         file = "FILENAME"
852
         ...
853
       enddevice
854
       ...
855
     end
856
 
857
Some sections (for example `section sim') should appear only once.
858
Others (for example `section memory' may appear multiple times.
859
 
860
Sections may be omitted, _unless they contain parameters which are
861 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
862 19 jeremybenn
is optional (for example whether it has a UART), then that
863 82 jeremybenn
functionality will not be provided.  If the section describes a part of
864 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
865
parameters of that section will take their default values.
866
 
867
All optional parts of the functionality are always described by
868
sections including a `enabled' parameter, which can be set to 0 to
869
ensure that functionality is explicitly omitted.
870
 
871
Even if a section is disabled, all its parameters will be read and
872 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
873
the Or1ksim command line (*note Interactive Command Line: Interactive
874 19 jeremybenn
Command Line.).
875
 
876
     Tip: It generally clearer to have sections describing _all_
877
     components, with omitted functionality explicitly indicated by
878
     setting the `enabled' parameter to 0
879
 
880
The following sections describe the various configuration sections and
881
the parameters which may be set in each.
882
 
883

884
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
885
 
886
3.2 Simulator Configuration
887
===========================
888
 
889
* Menu:
890
 
891
* Simulator Behavior::
892
* Verification API Configuration::
893
* CUC Configuration::
894
 
895

896
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
897
 
898
3.2.1 Simulator Behavior
899
------------------------
900
 
901 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
902
appear only once.  The following parameters may be specified.
903 19 jeremybenn
 
904
`verbose = 0|1'
905 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
906 19 jeremybenn
 
907
`debug = 0-9'
908 82 jeremybenn
 
909
     higher the value the greater the number of messages.  Default 0.
910
     Negative values will be treated as 0 (with a warning).  Values
911
     that are too large will be treated as 9 (with a warning).
912 19 jeremybenn
 
913
`profile = 0|1'
914
     If 1 (true) generate a profiling file using the file specified in
915 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
916 19 jeremybenn
 
917
`prof_file = ``FILENAME'''
918 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
919
     Default `sim.profile'.  For backwards compatibility, the
920
     alternative name `prof_fn' is supported for this parameter, but
921 346 jeremybenn
     deprecated.  Default `sim.profile'.
922 19 jeremybenn
 
923
`mprofile = 0|1'
924
     If 1 (true) generate a memory profiling file using the file
925
     specified in the `mprof_file' parameter or otherwise
926 82 jeremybenn
     `sim.mprofile'.  Default 0.
927 19 jeremybenn
 
928 346 jeremybenn
`mprof_file = ``FILENAME'''
929 19 jeremybenn
     Specifies the file to be used with the `mprofile' parameter.
930 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
931 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
932 346 jeremybenn
     deprecated.  Default `sim.mprofile'.
933 19 jeremybenn
 
934
`history = 0|1'
935 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
936 19 jeremybenn
 
937
          Note: Setting this parameter seriously degrades performance.
938
 
939
          Note: If this execution flow tracking is enabled, then
940
          `dependstats' must be enabled in the CPU configuration
941
          section (*note CPU Configuration: CPU Configuration.).
942
 
943
`exe_log = 0|1'
944 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
945
     file specified in parameter `exe_log_file'.  Default 0.
946 19 jeremybenn
 
947
          Note: Setting this parameter seriously degrades performance.
948
 
949
`exe_log_type = default|hardware|simple|software'
950
     Type of execution log to produce.
951
 
952
    `default'
953 82 jeremybenn
          Produce default output for the execution log.  In the current
954 19 jeremybenn
          implementation this is the equivalent of `hardware'.
955
 
956
    `hardware'
957
          After each instruction execution, log the number of
958
          instructions executed so far, the next instruction to execute
959
          (in hex), the general purpose registers (GPRs), status
960
          register, exception program counter, exception, effective
961
          address register and exception status register.
962
 
963
    `simple'
964
          After each instruction execution, log the number of
965
          instructions executed so far and the next instruction to
966
          execute, symbolically disassembled.
967
 
968
    `software'
969
          After each instruction execution, log the number of
970
          instructions executed so far and the next instruction to
971 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
972 19 jeremybenn
          each operand to the instruction.
973
 
974
 
975 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
976 19 jeremybenn
     insensitive) will be treated as the default with a warning.
977
 
978
          Note: Execution logs can be _very_ big.
979
 
980
`exe_log_start = VALUE'
981 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
982 19 jeremybenn
 
983
`exe_log_end = VALUE'
984 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
985
     once started logging will continue until the simulator exits).
986 19 jeremybenn
 
987
`exe_log_marker = VALUE'
988
     Specifies the number of instructions between printing horizontal
989 82 jeremybenn
     markers.  Default is to produce no markers.
990 19 jeremybenn
 
991
`exe_log_file = FILENAME'
992
     Filename for the execution log filename if `exe_log' is enabled.
993 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
994 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
995
     deprecated.
996
 
997 202 julius
`exe_bin_insn_log = 0|1'
998 346 jeremybenn
     Enable logging of executed instructions to a file in binary format.
999
     This is helpful for off-line dynamic execution analysis.
1000 202 julius
 
1001 346 jeremybenn
          Note: Execution logs can be _very_ big.  For example, while
1002 220 jeremybenn
          booting the Linux kernel, version 2.6.34, a log file 1.2GB in
1003
          size was generated.
1004 202 julius
 
1005
`exe_bin_insn_log_file = FILENAME'
1006
     Filename for the binary execution log filename if
1007
     `exe_bin_insn_log' is enabled.  Default `exe-insn.bin'.
1008
 
1009 19 jeremybenn
`clkcycle = VALUE[ps|ns|us|ms]'
1010 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
1011
     specified, `ps' is assumed.  Default 4000ps (250MHz).
1012 19 jeremybenn
 
1013
 
1014

1015
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
1016
 
1017
3.2.2 Verification API (VAPI) Configuration
1018
-------------------------------------------
1019
 
1020
The Verification API (VAPI) provides a TCP/IP interface to allow
1021 82 jeremybenn
components of the simulation to be controlled externally.  *Note
1022 19 jeremybenn
Verification API: Verification API, for more details.
1023
 
1024 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
1025
section may appear at most once.  The following parameters may be
1026 19 jeremybenn
specified.
1027
 
1028
`enabled = 0|1'
1029
     If 1 (true), verification API is enabled and its server started.
1030
     If 0 (the default), it is disabled.
1031
 
1032
`server_port = VALUE'
1033
     When VAPI is enabled, communication will be via TCP/IP on the port
1034 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
1035 19 jeremybenn
     The default value is 50000.
1036
 
1037 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
1038 19 jeremybenn
          practice suggests users should adopt port values in the
1039 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
1040 19 jeremybenn
 
1041
`log_enabled = 0|1'
1042
     If 1 (true), all VAPI requests and sent commands will be logged.
1043 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
1044 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
1045
 
1046
          Caution: This can generate a substantial amount of file I/O
1047
          and seriously degrade simulator performance.
1048
 
1049
`hide_device_id = 0|1'
1050 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
1051
     device ID.  This feature (when set to 1) is provided for backwards
1052 19 jeremybenn
     compatibility with an old version of VAPI.
1053
 
1054
`vapi_log_file = "FILENAME"'
1055
     Use `filename' as the file for logged data is logging is enabled
1056 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
1057 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
1058
     supported for this parameter, but deprecated.
1059
 
1060
 
1061

1062
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
1063
 
1064
3.2.3 Custom Unit Compiler (CUC) Configuration
1065
----------------------------------------------
1066
 
1067
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
1068 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
1069
beyond the initial prototype phase.  The configuration parameters are
1070 19 jeremybenn
described here for the record.
1071
 
1072 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
1073
appear at most once.  The following parameters may be specified.
1074 19 jeremybenn
 
1075
`memory_order = none|weak|strong|exact'
1076
     This parameter specifies the memory ordering required:
1077
 
1078
    `memory_order=none'
1079
          Different memory ordering, even if there are dependencies.
1080
          Bursts can be made, width can change.
1081
 
1082 346 jeremybenn
    `memory_order=weak'
1083 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
1084 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
1085
          change.
1086
 
1087 346 jeremybenn
    `memory_order=strong'
1088 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
1089 19 jeremybenn
 
1090 346 jeremybenn
    `memory_order=exact'
1091 19 jeremybenn
          Exactly the same memory ordering and widths.
1092
 
1093
 
1094 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1095 19 jeremybenn
     orderings are ignored with a warning.
1096
 
1097
`calling_convention = 0|1'
1098 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1099 19 jeremybenn
     (the default), they may use other convenitions.
1100
 
1101
`enable_bursts = 0 | 1'
1102 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1103 19 jeremybenn
     not detected.
1104
 
1105
`no_multicycle = 0 | 1'
1106 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1107
     (the default), multicycle logic paths will be generated.
1108 19 jeremybenn
 
1109
`timings_file = "FILENAME"'
1110 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1111
     default value is `"virtex.tim"'.  For backwards compatibility, the
1112 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1113
     deprecated.
1114
 
1115
 
1116

1117
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1118
 
1119
3.3 Configuring the OpenRISC Architectural Components
1120
=====================================================
1121
 
1122
* Menu:
1123
 
1124
* CPU Configuration::
1125
* Memory Configuration::
1126
* Memory Management Configuration::
1127
* Cache Configuration::
1128
* Interrupt Configuration::
1129
* Power Management Configuration::
1130
* Branch Prediction Configuration::
1131
* Debug Interface Configuration::
1132
 
1133

1134
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1135
 
1136
3.3.1 CPU Configuration
1137
-----------------------
1138
 
1139 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1140
appear only once.  At present Or1ksim does not model multi-CPU systems.
1141 19 jeremybenn
The following parameters may be specified.
1142
 
1143
`ver = VALUE'
1144
 
1145
`cfg = VALUE'
1146
 
1147
`rev = VALUE'
1148
     The values are used to form the corresponding fields in the `VR'
1149 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1150 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1151
     and `cfg', 6 bits for `rev').
1152
 
1153
`upr = VALUE'
1154
     Used as the value of the Unit Present Register (UPR) Special
1155 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1156 19 jeremybenn
     i.e.
1157
        * UPR present (0x00000001)
1158
 
1159
        * Data cache present (0x00000002)
1160
 
1161
        * Instruction cache present (0x00000004)
1162
 
1163
        * Data MMY present (0x00000008)
1164
 
1165
        * Instruction MMU present (0x00000010)
1166
 
1167
        * Debug unit present (0x00000040)
1168
 
1169
        * Power management unit present (0x00000100)
1170
 
1171
        * Programmable interrupt controller present (0x00000200)
1172
 
1173
        * Tick timer present (0x00000400)
1174
 
1175
     However, with the exection of the UPR present (0x00000001) and tick
1176
     timer present, the various fields will be modified with the values
1177
     specified in their corresponding configuration sections.
1178
 
1179
`cfgr = VALUE'
1180
     Sets the CPU configuration register (Special Purpose Register 2) to
1181 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1182
     instruction set.  Attempts to set any other value are accepted, but
1183 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1184
 
1185
`sr = VALUE'
1186
     Sets the supervision register Special Purpose Register (SPR 0x11)
1187 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1188 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1189
 
1190 98 jeremybenn
          Note: This is particularly useful when an image is held in
1191
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1192
          so that interrupt vectors are basedf at 0xf0000000, rather
1193
          than 0x0.
1194
 
1195 19 jeremybenn
`superscalar = 0|1'
1196 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1197 19 jeremybenn
     0.
1198
 
1199
     In the current simulator, the only functional effect of superscalar
1200
     mode is to affect the calculation of the number of cycles taken to
1201
     execute an instruction.
1202
 
1203
          Caution: The code for this does not appear to be complete or
1204
          well tested, so users are advised not to use this option.
1205
 
1206
`hazards = 0|1'
1207 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1208
     value is 0.
1209 19 jeremybenn
 
1210
     In the current simulator, the only functional effect is to cause
1211
     logging of hazard waiting information if the CPU is superscalar.
1212
     However nowhere in the simulator is this data actually computed,
1213
     so the net result is probably to have no effect.
1214
 
1215
     if harzards are tracked, current hazards can be displayed using the
1216
     simulator's `r' command.
1217
 
1218
          Caution: The code for this does not appear to be complete or
1219
          well tested, so users are advised not to use this option.
1220
 
1221
`dependstats = 0|1'
1222 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1223
     value 0.
1224 19 jeremybenn
 
1225
     If these values are calculated, the depencies can be displayed
1226
     using the simulator's `stat' command.
1227
 
1228
          Note: This field must be enabled, if execution execution flow
1229
          tracking (field `history') has been requested in the simulator
1230
          configuration section (*note Simulator Behavior: Simulator
1231
          Behavior.).
1232
 
1233
`sbuf_len = VALUE'
1234
     The length of the store buffer is set to VALUE, which must be no
1235 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1236
     warning.  Negative values will be treated as 0 with a warning.
1237
     Use 0 to disable the store buffer.
1238 19 jeremybenn
 
1239
     When the store buffer is active, stores are accumulated and
1240
     committed when I/O is idle.
1241
 
1242 100 julius
`hardfloat = 0|1'
1243 346 jeremybenn
     If 1, hardfloat instructions are enabled.  Default value 0.
1244 19 jeremybenn
 
1245 104 jeremybenn
 
1246 19 jeremybenn

1247
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1248
 
1249
3.3.2 Memory Configuration
1250
--------------------------
1251
 
1252 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1253 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1254 19 jeremybenn
 
1255 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1256 346 jeremybenn
     controller.  If a memory controller is enabled, then the standard
1257 98 jeremybenn
     OpenRISC C libraries will initialize it to expect 64MB memory
1258
     blocks, and any memory declarations _must_ reflect this.  The
1259
     section describing memory controller configuration describes the
1260
     steps necessary for using smaller or larger memory sections (*note
1261
     Memory Controller Configuration: Memory Controller Configuration.).
1262
 
1263
     If a memory controller is _not_ enabled, then the standard C
1264
     library code will generate memory access errors.  The solution is
1265
     to declare an additional writable memory block, mimicing the memory
1266
     controller's register bank as follows.
1267
 
1268
          section memory
1269
            pattern = 0x00
1270
            type = unknown
1271
            name = "MC shadow"
1272
            baseaddr = 0x93000000
1273
            size     = 0x00000080
1274
            delayr = 2
1275
            delayw = 4
1276
          end
1277
 
1278
 
1279
The following parameters may be specified.
1280
 
1281 19 jeremybenn
`type=random|pattern|unknown|zero'
1282 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1283 19 jeremybenn
     default value is `unknown'.
1284
 
1285
    `random'
1286 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1287 19 jeremybenn
          random generator may be set using the `random_seed' field in
1288
          this section (see below), thus ensuring the same "random"
1289
          values are used each time.
1290
 
1291
    `pattern'
1292
          Set the memory values to be a pattern value, which is set
1293
          using the `pattern' field in this section (see below).
1294
 
1295
    `unknown'
1296 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1297 240 julius
          This option will yield faster initialization of the
1298 346 jeremybenn
          simulator.  This is the default.
1299 19 jeremybenn
 
1300
    `zero'
1301 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1302 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1303
          such.
1304
 
1305
               Note: As a consequence, if the `pattern' field is
1306
               _subsequently_ specified in this section, the value in
1307
               that field will be used instead of zero to initialize
1308
               the memory.
1309
 
1310
 
1311
`random_seed = VALUE'
1312 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1313 19 jeremybenn
     has any effect for memory type `random'.
1314
 
1315
     The default value is -1, which means the seed will be set from a
1316
     call to the `time' function, thus ensuring different random values
1317 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1318 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1319
     values used in any particular run.
1320
 
1321
`pattern = VALUE'
1322 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1323
     default value is 0.  This only has any effect for memory type
1324
     `pattern'.  The least significant 8 bits of this value is used to
1325
     initialize each byte.  More than 8 bits can be specified, but will
1326 19 jeremybenn
     ignored with a warning.
1327
 
1328
          Tip: The default value, is equivalent to setting the memory
1329 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1330 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1331
          and not specifying a value for `pattern'.
1332
 
1333
`baseaddr = VALUE'
1334 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1335 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1336
     The default value is 0.
1337
 
1338
`size = VALUE'
1339 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1340
     be a multiple of 4 (i.e.  word aligned).  The default value is
1341
     1024.
1342 19 jeremybenn
 
1343
          Note: When allocating memory, the simulator will allocate the
1344
          nearest 2^n bytes greater than or equal to VALUE, and will not
1345
          notice memory misses in any part of the memory between VALUE
1346
          and the amount allocated.
1347
 
1348
          As a consequence users are strongly recommended to specify
1349 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1350 19 jeremybenn
          amount of memory is required, it should be specified as
1351
          separate, contiguous blocks, each of which is a power of 2 in
1352
          size.
1353
 
1354
`name = "TEXT"'
1355 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1356
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1357 19 jeremybenn
     `"anonymous memory block"'.
1358
 
1359
          Note: It is not clear that this information is currently ever
1360 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1361 19 jeremybenn
          command of the simulator ignores it.
1362
 
1363
`ce = VALUE'
1364 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1365 19 jeremybenn
     instance should have a unique chip enable index, which should be
1366 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1367 19 jeremybenn
     controller when identifying different memory instances.
1368
 
1369 346 jeremybenn
     There is no requirement to set `ce' if a memory controller is not
1370
     enabled.  The default value is -1 (invalid).
1371 19 jeremybenn
 
1372
`mc = VALUE'
1373 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1374 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1375
     for a memory controller (*note Memory Controller Configuration:
1376
     Memory Controller Configuration.).
1377
 
1378 346 jeremybenn
     There is no requirement to set `mc' if a memory controller is not
1379
     enabled.  Default value is 0, which is also the default value of a
1380 98 jeremybenn
     memory controller `index' field.  This is suitable therefore for
1381
     designs with just one memory controller.
1382 19 jeremybenn
 
1383
`delayr = VALUE'
1384 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1385
     memory does not support reading.  Default value 1.  The simulator
1386 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1387
     count when reading from main memory.
1388
 
1389
`delayw = VALUE'
1390 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1391
     memory does not support writing.  Default value 1.  The simulator
1392 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1393
     count when writing to main memory.
1394
 
1395
`log = "FILE"'
1396
     If specified, `file' names a file for all memory accesses to be
1397 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1398 19 jeremybenn
     that the memory is not logged.
1399
 
1400
 
1401

1402
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1403
 
1404
3.3.3 Memory Management Configuration
1405
-------------------------------------
1406
 
1407
Memory Management Unit (MMU) configuration is described in `section
1408
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1409 82 jeremybenn
Each section should appear at most once.  The following parameters may
1410 19 jeremybenn
be specified.
1411
 
1412
`enabled = 0|1'
1413
     If 1 (true), the data or instruction (as appropriate) MMU is
1414 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1415 19 jeremybenn
 
1416
`nsets = VALUE'
1417
     Sets the number of data or instruction (as appropriate) TLB sets to
1418 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1419
     which do not fit these criteria are ignored with a warning.  The
1420 19 jeremybenn
     default value is 1.
1421
 
1422
`nways = VALUE'
1423
     Sets the number of data or instruction (as appropriate) TLB ways to
1424 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1425
     this range are ignored with a warning.  The default value is 1.
1426 19 jeremybenn
 
1427
`pagesize = VALUE'
1428
     The data or instruction (as appropriate) MMU page size is set to
1429 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1430
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1431 19 jeremybenn
 
1432
`entrysize = VALUE'
1433
     The data or instruction (as appropriate) MMU entry size is set to
1434 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1435
     of 2 are ignored with a warning.  The default value is 1.
1436 19 jeremybenn
 
1437
          Note: Or1ksim does not appear to use the `entrysize' parameter
1438 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1439 19 jeremybenn
          not seem to matter.
1440
 
1441
`ustates = VALUE'
1442
     The number of instruction usage states for the data or instruction
1443
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1444 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1445 19 jeremybenn
     value is 2.
1446
 
1447
          Note: Or1ksim does not appear to use the `ustates' parameter
1448 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1449 19 jeremybenn
          not seem to matter.
1450
 
1451
`hitdelay = VALUE'
1452
     Set the number of cycles a data or instruction (as appropriate) MMU
1453 82 jeremybenn
     hit costs.  Default value 1.
1454 19 jeremybenn
 
1455
`missdelay = VALUE'
1456
     Set the number of cycles a data or instruction (as appropriate) MMU
1457 82 jeremybenn
     miss costs.  Default value 1.
1458 19 jeremybenn
 
1459
 
1460

1461
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1462
 
1463
3.3.4 Cache Configuration
1464
-------------------------
1465
 
1466
Cache configuration is described in `section dc' (for the data cache)
1467 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1468
appear at most once.  The following parameters may be specified.
1469 19 jeremybenn
 
1470
`enabled = 0|1'
1471
     If 1 (true), the data or instruction (as appropriate) cache is
1472 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1473 19 jeremybenn
 
1474
`nsets = VALUE'
1475
     Sets the number of data or instruction (as appropriate) cache sets
1476
     to VALUE, which must be a power of two, not exceeding
1477
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1478 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1479
     both defined in the code to be 1024).  The default value is 1.
1480 19 jeremybenn
 
1481
`nways = VALUE'
1482
     Sets the number of data or instruction (as appropriate) cache ways
1483
     to VALUE, which must be a power of two, not exceeding
1484
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1485 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1486
     both defined in the code to be 32).  The default value is 1.
1487 19 jeremybenn
 
1488
`blocksize = VALUE'
1489
     The data or instruction (as appropriate) cache block size is set to
1490 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1491 19 jeremybenn
 
1492
`ustates = VALUE'
1493
     The number of instruction usage states for the data or instruction
1494
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1495
     The default value is 2.
1496
 
1497
`hitdelay = VALUE'
1498 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1499
     cache hit costs.  Default value 1.
1500 19 jeremybenn
 
1501
`missdelay = VALUE'
1502 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1503
     cache miss costs.  Default value 1.
1504 19 jeremybenn
 
1505
`load_hitdelay = VALUE'
1506 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1507
     costs.  Default value 2.
1508 19 jeremybenn
 
1509
`load_missdelay = VALUE'
1510 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1511
     miss costs.  Default value 2.
1512 19 jeremybenn
 
1513
`store_hitdelay = VALUE'
1514 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1515
     costs.  Default value 0.
1516 19 jeremybenn
 
1517
`store_missdelay = VALUE'
1518 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1519
     miss costs.  Default value 0.
1520 19 jeremybenn
 
1521
 
1522

1523
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1524
 
1525
3.3.5 Interrupt Configuration
1526
-----------------------------
1527
 
1528
Programmable Interrupt Controller (PIC) configuration is described in
1529 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1530
mechanism for handling multiple interrupt controllers.  The following
1531 19 jeremybenn
parameters may be specified.
1532
 
1533
`enabled = 0|1'
1534 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1535
 
1536 19 jeremybenn
 
1537
`edge_trigger = 0|1'
1538
     If 1 (true, the default), the programmable interrupt controller is
1539 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1540 19 jeremybenn
 
1541
 
1542

1543
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1544
 
1545
3.3.6 Power Management Configuration
1546
------------------------------------
1547
 
1548 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1549 19 jeremybenn
(which only happens when the power management unit is enabled) of
1550
setting the different bits in the power management Special Purpose
1551
Register (PMR, SPR 0x4000) is
1552
 
1553
`SDF (bit mask 0x0000000f)'
1554
     No effect - these bits are ignored
1555
 
1556
`DME (bit mask 0x00000010)'
1557
`SME (bit mask 0x00000020)'
1558
     Both these bits cause the processor to stop executing
1559 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1560 19 jeremybenn
     VAPI etc) carry on as normal.
1561
 
1562
`DCGE (bit mask 0x00000004)'
1563
     No effect - this bit is ignored
1564
 
1565
`SUME (bit mask 0x00000008)'
1566
     Enabling this bit causes a message to be printed, advising that the
1567
     processor is suspending and the simulator exits.
1568
 
1569
 
1570
On reset all bits are cleared.
1571
 
1572 82 jeremybenn
Power management configuration is described in `section pm'.  This
1573
section may appear at most once.  The following parameter may be
1574 19 jeremybenn
specified.
1575
 
1576
`enabled = 0|1'
1577 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1578
     is disabled.
1579 19 jeremybenn
 
1580
 
1581

1582
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1583
 
1584
3.3.7 Branch Prediction Configuration
1585
-------------------------------------
1586
 
1587
From examining the code base, it seems the branch prediction function
1588 82 jeremybenn
is not fully implemented.  At present the functionality seems
1589
restricted to collection of statistics.
1590 19 jeremybenn
 
1591 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1592
section may appear at most once.  The following parameters may be
1593 19 jeremybenn
specified.
1594
 
1595
`enabled = 0|1'
1596 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1597 19 jeremybenn
     is disabled.
1598
 
1599
`btic = 0|1'
1600
     If 1 (true), the branch target instruction cache model is enabled.
1601
     If 0 (the default), it is disabled.
1602
 
1603
`sbp_bf_fwd = 0|1'
1604 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1605 19 jeremybenn
 
1606
     instruction.
1607
 
1608
`sbp_bnf_fwd = 0|1'
1609 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1610
     If 0 (the default), do not use forward prediction for this
1611 19 jeremybenn
     instruction.
1612
 
1613
`hitdelay = VALUE'
1614 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1615 19 jeremybenn
     value 0.
1616
 
1617
`missdelay = VALUE'
1618 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1619 19 jeremybenn
     value 0.
1620
 
1621
 
1622

1623
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1624
 
1625
3.3.8 Debug Interface Configuration
1626
-----------------------------------
1627
 
1628
The debug unit and debug interface configuration is described in
1629 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1630 19 jeremybenn
parameters may be specified.
1631
 
1632
`enabled = 0|1'
1633 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1634 19 jeremybenn
     disabled.
1635
 
1636
          Note: This enables the functionality of the debug unit (its
1637 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1638
          external interface to the debug unit.  For that, see
1639 235 jeremybenn
          `rsp_enabled' below.
1640 19 jeremybenn
 
1641
`rsp_enabled = 0|1'
1642
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1643
     provding an interface to an external GNU debugger, using the port
1644
     specified in the `rsp_port' field (see below), or the
1645 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1646 19 jeremybenn
     not started, and no external interface is provided.
1647
 
1648
     For more detailed information on the interface to the GNU Debugger
1649
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1650
     Practical Experience with the OpenRISC 1000 Architecture', by
1651
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1652
 
1653
`rsp_port = VALUE'
1654
     VALUE specifies the port to be used for the GDB "Remote Serial
1655 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1656
     51000.  If the value 0 is specified, Or1ksim will instead look for
1657 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1658
 
1659
          Tip: There is no registered port for Or1ksim "Remote Serial
1660 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1661
          users should adopt port values in the "Dynamic" or "Private"
1662
          port range, i.e.  49152-65535.
1663 19 jeremybenn
 
1664
`vapi_id = VALUE'
1665
     VALUE specifies the value of the Verification API (VAPI) base
1666 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1667 19 jeremybenn
     Verification API, for more details.
1668
 
1669
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1670
     JTAG protocol transactions will be logged to the VAPI log file, if
1671 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
1672
     the debug unit.  No VAPI commands are sent, nor requests handled.
1673 19 jeremybenn
 
1674
 
1675

1676
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
1677
 
1678
3.4 Configuring Memory Mapped Peripherals
1679
=========================================
1680
 
1681 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1682 19 jeremybenn
(unlike other components) by default they are enabled.
1683
 
1684
* Menu:
1685
 
1686
* Memory Controller Configuration::
1687
* UART Configuration::
1688
* DMA Configuration::
1689
* Ethernet Configuration::
1690
* GPIO Configuration::
1691
* Display Interface Configuration::
1692
* Frame Buffer Configuration::
1693
* Keyboard Configuration::
1694
* Disc Interface Configuration::
1695
* Generic Peripheral Configuration::
1696
 
1697

1698
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
1699
 
1700
3.4.1 Memory Controller Configuration
1701
-------------------------------------
1702
 
1703
The memory controller used in Or1ksim is the component implemented at
1704 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
1705 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
1706 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1707
memory mapped component, which resides on the main OpenRISC Wishbone
1708
data bus.
1709 19 jeremybenn
 
1710 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
1711 19 jeremybenn
section may appear multiple times, specifying multiple memory
1712 98 jeremybenn
controllers.
1713 19 jeremybenn
 
1714 98 jeremybenn
     Caution: The standard OpenRISC C libraries will initialize the
1715
     memory controller to expect 64MB memory blocks, and any memory
1716
     declarations _must_ reflect this.
1717
 
1718
     If smaller memory blocks are declared with a memory controller,
1719
     then sufficient memory will not be allocated by Or1ksim, but out of
1720 346 jeremybenn
     range memory accesses will not be trapped.  For example declaring a
1721 98 jeremybenn
     memory section from 0-4MB with a memory controller enabled would
1722
     mean that accesses between 4MB and 64MB would be permitted, but
1723
     having no allocated memory would likely cause a segmentation fault.
1724
 
1725
     If the user is determined to use smaller memories with the memory
1726
     controller, then custom initialization code must be provided, to
1727
     ensure the memory controller traps out-of-memory accesses.
1728
 
1729
The following parameters may be specified.
1730
 
1731 19 jeremybenn
`enabled = 0|1'
1732 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
1733
     0, it is disabled.
1734 19 jeremybenn
 
1735
          Note: The memory controller can effectively also be disabled
1736
          by setting an appropriate power on control register value
1737 82 jeremybenn
          (see below).  However this should only be used if it is
1738 19 jeremybenn
          desired to specifically model this behavior of the memory
1739
          controller, not as a way of disabling the memory controller
1740
          in general.
1741
 
1742
`baseaddr = VALUE'
1743
     Set the base address of the memory controller's memory mapped
1744 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
1745 19 jeremybenn
     sensible value.
1746
 
1747
     The memory controller has a 7 bit address bus, with a total of 19
1748
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1749
     addresses 0x50 through 0x7c are not used).
1750
 
1751
`poc = VALUE'
1752
     Specifies the value of the power on control register, The least
1753
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
1754
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
1755
     the type of memory connected (use 0 for a disabled interface, 1
1756
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
1757
     devices).
1758
 
1759
     If other bits are specified, they are ignored with a warning.
1760
 
1761
          Caution: The default value, 0, corresponds to a disabled
1762
          8-bit bus, and is likely not the most suitable value
1763
 
1764
`index = VALUE'
1765
     Specify the index of this memory controller amongst all the memory
1766 82 jeremybenn
     controllers.  This value should be unique for each memory
1767 19 jeremybenn
     controller, and is used to associate specific memories with the
1768
     controller, through the `mc' field in the `section memory'
1769
     configuration (*note Memory Configuration: Memory Configuration.).
1770
 
1771
     The default value, 0, is suitable when there is only one memory
1772
     controller.
1773
 
1774
 
1775

1776
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
1777
 
1778
3.4.2 UART Configuration
1779
------------------------
1780
 
1781
The UART implemented in Or1ksim follows the specification of the
1782 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
1783 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
1784
 
1785
The component provides a number of interfaces to emulate the behavior
1786
of an external terminal connected to the UART.
1787
 
1788 82 jeremybenn
UART configuration is described in `section uart'.  This section may
1789
appear multiple times, specifying multiple UARTs.  The following
1790 19 jeremybenn
parameters may be specified.
1791
 
1792
`enabled = 0|1'
1793 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
1794 19 jeremybenn
     disabled.
1795
 
1796
`baseaddr = VALUE'
1797
     Set the base address of the UART's memory mapped registers to
1798 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1799 19 jeremybenn
 
1800
     The UART has a 3 bit address bus, with a total of 8 8-bit
1801
     registers, at addresses 0x0 through 0x7.
1802
 
1803
`channel = "TYPE:ARGS"'
1804
     Specify the channel representing the terminal connected to the UART
1805
     Rx & Tx pins.
1806
 
1807
    `channel="file:`rxfile',`txfile'"'
1808
          Read input characters from the file `rxfile' and write output
1809
          characters to the file `txfile' (which will be created if
1810
          required).
1811
 
1812
    `channel="xterm:ARGS"'
1813
          Create an xterm on startup, write UART Tx traffic to the
1814
          xterm and take Rx traffic from the keyboard when the xterm
1815 82 jeremybenn
          window is selected.  Additional arguments to the xterm
1816
          command (for example specifying window size may be specified
1817
          in ARGS, or this may be left blank.
1818 19 jeremybenn
 
1819
    `channel="tcp:VALUE"'
1820
          Open the TCP/IP port specified by VALUE and read and write
1821
          UART traffic from and to it.
1822
 
1823
          Typically a telnet session is connected to the other end of
1824
          this port.
1825
 
1826
               Tip: There is no registered port for Or1ksim telnet UART
1827 82 jeremybenn
               connection.  Priviledged access is required to read
1828 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
1829 346 jeremybenn
               Instead users should use port values in the "Dynamic" or
1830
               "Private" port range, i.e.  49152-65535.
1831 19 jeremybenn
 
1832
    `channel="fd:`rxfd',`txfd'"'
1833
          Read and write characters from and to the existing open
1834
          numerical file descriptors, file `rxfd' and `txfd'.
1835
 
1836
    `channel="tty:device=/dev/ttyS0,baud=9600"'
1837
          Read and write characters from and to a physical serial port.
1838 346 jeremybenn
          The precise device (shown here as `/dev/ttyS0') may vary from
1839
          machine to machine.
1840 19 jeremybenn
 
1841
 
1842
     The default value for this field is `"xterm:"'.
1843
 
1844
`irq = VALUE'
1845 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
1846 19 jeremybenn
 
1847
`16550 = 0|1'
1848 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
1849
     default), it has the functionality of a 16450.  The principal
1850 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
1851
 
1852
`jitter = VALUE'
1853
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
1854 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
1855 19 jeremybenn
 
1856
          Note: This functionality has yet to be implemented, so this
1857
          parameter has no effect.
1858
 
1859
`vapi_id = VALUE'
1860
     VALUE specifies the value of the Verification API (VAPI) base
1861 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
1862 19 jeremybenn
     Verification API, for more details, which details the use of the
1863
     VAPI with the UART.
1864
 
1865
 
1866

1867
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
1868
 
1869
3.4.3 DMA Configuration
1870
-----------------------
1871
 
1872
The DMA controller used in Or1ksim is the component implemented at
1873 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
1874 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
1875 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1876
memory mapped component, which resides on the main OpenRISC Wishbone
1877
data bus.  The present implementation is incomplete, intended only to
1878
support the Ethernet interface (*note Ethernet Configuration::),
1879
although the Ethernet interface is not yet completed.
1880 19 jeremybenn
 
1881 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
1882
appear multiple times, specifying multiple DMA controllers.  The
1883 19 jeremybenn
following parameters may be specified.
1884
 
1885
`enabled = 0|1'
1886 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
1887
     it is disabled.
1888 19 jeremybenn
 
1889
`baseaddr = VALUE'
1890
     Set the base address of the DMA's memory mapped registers to
1891 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1892 19 jeremybenn
 
1893
     The DMA controller has a 10 bit address bus, with a total of 253
1894 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
1895
     0x010 control the overall behavior of the DMA controller.  There
1896
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
1897
     channels available.  Addresses 0x014 through 0x01c are not used.
1898 19 jeremybenn
 
1899
`irq = VALUE'
1900 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
1901 19 jeremybenn
     0.
1902
 
1903
`vapi_id = VALUE'
1904
     VALUE specifies the value of the Verification API (VAPI) base
1905 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
1906 19 jeremybenn
     API: Verification API, for more details, which details the use of
1907
     the VAPI with the DMA controller.
1908
 
1909
 
1910

1911
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
1912
 
1913
3.4.4 Ethernet Configuration
1914
----------------------------
1915
 
1916
The Ethernet MAC used in Or1ksim is the component implemented at
1917 98 jeremybenn
OpenCores, and found in the top level SVN directory, `ethmac'.  It also
1918
forms part of the OpenRISC SoC, ORPSoC.  It is described in the
1919 19 jeremybenn
document `Ethernet IP Core Specification' by Igor Mohor, which can be
1920 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1921
which resides on the main OpenRISC Wishbone data bus.
1922 19 jeremybenn
 
1923 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
1924
section may appear multiple times, specifying multiple Ethernet
1925
interfaces.  The following parameters may be specified.
1926 19 jeremybenn
 
1927
`enabled = 0|1'
1928 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
1929
     is disabled.
1930 19 jeremybenn
 
1931
`baseaddr = VALUE'
1932
     Set the base address of the MAC's memory mapped registers to
1933 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1934 19 jeremybenn
 
1935
     The Ethernet MAC has a 7-bit address bus, with a total of 21
1936 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
1937 19 jeremybenn
 
1938
          Note: The Ethernet specification describes a Tx control
1939 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
1940
          is not implemented in the Or1ksim model.
1941 19 jeremybenn
 
1942
`dma = VALUE'
1943
     VALUE specifies the DMA controller with which this Ethernet is
1944 82 jeremybenn
     associated.  The default value is 0.
1945 19 jeremybenn
 
1946
          Note: Support for external DMA is not provided in the current
1947 82 jeremybenn
          implementation, and this value is ignored.  In any case there
1948 19 jeremybenn
          is no equivalent field to which this can be matched in the
1949
          current DMA component implementation (*note DMA
1950
          Configuration: DMA Configuration.).
1951
 
1952
`irq = VALUE'
1953 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
1954 19 jeremybenn
 
1955
`rtx_type = 0|1'
1956
     If 1 (true) use a socket interface to the Ethernet (see parameter
1957 82 jeremybenn
     `sockif' below).  If 0 (the default), use a file interface,
1958
     reading and writing from and to the files specified in the
1959
     `rxfile' and `txfile' parameters (see below).
1960 19 jeremybenn
 
1961
          Note: By default the socket interface is not provided in
1962 82 jeremybenn
          Or1ksim.  If it is required, this must be requested when
1963 19 jeremybenn
          configuring, by use of the `--enable-ethphy' option to
1964
          `configure'.
1965
 
1966
               configure --target=or32-uclinux --enable-ethphy ...
1967
 
1968
`rx_channel = RXVALUE'
1969
`tx_channel = TXVALUE'
1970
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
1971 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
1972 19 jeremybenn
 
1973
          Note: As noted above, support for external DMA is not
1974
          provided in the current implementation, and so these values
1975
          are ignored.
1976
 
1977
`rxfile = "RXFILE"'
1978
`txfile = "TXFILE"'
1979
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
1980
     as input and TXFILE specifies the fie to use as output.
1981
 
1982 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
1983
     packet length (32 bits), followed by that many bytes of data.
1984
     Once the input file is empty, the Ethernet MAC behaves as though
1985
     there were no data on the Ethernet.  The default values of these
1986 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
1987
 
1988 82 jeremybenn
     The input file must exist and be readable.  The output file must be
1989
     writable and will be created if necessary.  If either of these
1990 19 jeremybenn
     conditions is not met, a warning will be given.
1991
 
1992
`sockif = "SERVICE"'
1993
     When `rtx_type' is 1 (see above), SERVICE specifies the service to
1994 82 jeremybenn
     use for communication.  This may be TCP/IP or UDP/IP.  The default
1995 19 jeremybenn
     value of this parameter is `"or1ksim_eth"'.
1996
 
1997
`vapi_id = VALUE'
1998
     VALUE specifies the value of the Verification API (VAPI) base
1999 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
2000 19 jeremybenn
     Verification API, for more details, which details the use of the
2001
     VAPI with the DMA controller.
2002
 
2003
 
2004

2005
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
2006
 
2007
3.4.5 GPIO Configuration
2008
------------------------
2009
 
2010
The GPIO used in Or1ksim is the component implemented at OpenCores, and
2011 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
2012 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
2013 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
2014 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
2015
 
2016 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
2017
appear multiple times, specifying multiple GPIO devices.  The following
2018 19 jeremybenn
parameters may be specified.
2019
 
2020
`enabled = 0|1'
2021 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
2022 19 jeremybenn
     disabled.
2023
 
2024
`baseaddr = VALUE'
2025
     Set the base address of the GPIO's memory mapped registers to
2026 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2027 19 jeremybenn
 
2028
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
2029
     registers, although the number of bits that are actively used
2030 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
2031 19 jeremybenn
 
2032
`irq = VALUE'
2033 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
2034 19 jeremybenn
 
2035
`vapi_id = VALUE'
2036
     VALUE specifies the value of the Verification API (VAPI) base
2037 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
2038 19 jeremybenn
     Verification API, for more details, which details the use of the
2039 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
2040 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
2041
     but deprecated.
2042
 
2043
 
2044

2045
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
2046
 
2047
3.4.6 Display Interface Configuration
2048
-------------------------------------
2049
 
2050
Or1ksim models a VGA interface to an external monitor.  The VGA
2051
controller used in Or1ksim is the component implemented at OpenCores,
2052 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
2053 82 jeremybenn
for the optional hardware cursors.  It is described in the document
2054 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
2055 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2056
which resides on the main OpenRISC Wishbone data bus.
2057 19 jeremybenn
 
2058
The current implementation provides only functionality to dump the
2059
screen to a file at intervals.
2060
 
2061 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
2062 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
2063
The following parameters may be specified.
2064
 
2065
`enabled = 0|1'
2066 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
2067 19 jeremybenn
     disabled.
2068
 
2069
`baseaddr = VALUE'
2070
     Set the base address of the VGA controller's memory mapped
2071 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2072 19 jeremybenn
     sensible value.
2073
 
2074
     The VGA controller has a 12-bit address bus, with 7 32-bit
2075
     registers, at addresses 0x000 through 0x018, and two color lookup
2076 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2077 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2078
     are not used.
2079
 
2080
`irq = VALUE'
2081 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2082 19 jeremybenn
     0.
2083
 
2084
`refresh_rate = VALUE'
2085 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2086 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2087
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2088
     50 times per simulated second.
2089
 
2090
`txfile = "FILE"'
2091
     FILE specifies the base of the filename for screen dumps.
2092
     Successive screen dumps will be in BMP format, in files with the
2093
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2094 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2095 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2096
     supported for this parameter, but deprecated.
2097
 
2098
 
2099

2100
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2101
 
2102
3.4.7 Frame Buffer Configuration
2103
--------------------------------
2104
 
2105 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2106 19 jeremybenn
     configuration fields are described here, but the component should
2107 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2108 19 jeremybenn
     to make screen dumps to file.
2109
 
2110 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2111
may appear multiple times, specifying multiple frame buffers.  The
2112 19 jeremybenn
following parameters may be specified.
2113
 
2114
`enabled = 0|1'
2115 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2116 19 jeremybenn
     is disabled.
2117
 
2118
`baseaddr = VALUE'
2119
     Set the base address of the frame buffer's memory mapped registers
2120 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2121
     value.
2122 19 jeremybenn
 
2123
     The frame buffer has an 121-bit address bus, with 4 32-bit
2124
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2125 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2126 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2127
 
2128
`refresh_rate = VALUE'
2129 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2130 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2131
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2132
     50 times per simulated second.
2133
 
2134
`txfile = "FILE"'
2135
     FILE specifies the base of the filename for screen dumps.
2136
     Successive screen dumps will be in BMP format, in files with the
2137
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2138 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2139 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2140
     supported for this parameter, but deprecated.
2141
 
2142
 
2143

2144
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2145
 
2146
3.4.8 Keyboard Configuration (PS2)
2147
----------------------------------
2148
 
2149 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2150 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2151 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2152
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2153 19 jeremybenn
standard, this is presumably what is expected with this device.
2154
 
2155
The implementation only provides for keyboard support, which is
2156 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2157 19 jeremybenn
 
2158
     Caution: A standard i8042 device has two registers at addresses
2159 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2160
     suggests that the Or1ksim component places these registers at
2161
     addresses 0x00 and 0x04.
2162 19 jeremybenn
 
2163
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2164
     implements the i8042 device driver, anticipating these registers
2165 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2166 19 jeremybenn
     code will work.
2167
 
2168
     This component should be used with caution.
2169
 
2170 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2171
appear multiple times, specifying multiple keyboard interfaces.  The
2172 19 jeremybenn
following parameters may be specified.
2173
 
2174
`enabled = 0|1'
2175 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2176 19 jeremybenn
     disabled.
2177
 
2178
`baseaddr = VALUE'
2179
     Set the base address of the keyboard's memory mapped registers to
2180 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2181 19 jeremybenn
 
2182
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2183
     registers, at addresses 0x000 and 0x004.
2184
 
2185
          Caution: As noted above, a standard Intel 8042 interface
2186
          would expect to find these registers at locations 0x60 and
2187
          0x64, thus requiring at least a 7-bit bus.
2188
 
2189
`irq = VALUE'
2190 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2191 19 jeremybenn
     value 0.
2192
 
2193
`rxfile = "FILE"'
2194
     `file' specifies a file containing raw key stroke data, which
2195 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2196 19 jeremybenn
     `"kbd_in"'.
2197
 
2198
 
2199

2200
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2201
 
2202
3.4.9 Disc Interface Configuration
2203
----------------------------------
2204
 
2205
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2206
IDE Controller) component implemented at OpenCores, and found in the
2207 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2208 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2209 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2210
which resides on the main OpenRISC Wishbone data bus.
2211 19 jeremybenn
 
2212 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2213
may appear multiple times, specifying multiple disc controllers.  The
2214 19 jeremybenn
following parameters may be specified.
2215
 
2216
`enabled = 0|1'
2217 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2218 19 jeremybenn
     0, it is disabled.
2219
 
2220
`baseaddr = VALUE'
2221
     Set the base address of the ATA/ATAPI interface's memory mapped
2222 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2223 19 jeremybenn
     sensible value.
2224
 
2225
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2226 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2227
     ATA/ATAPI interface selected (see `dev_id' below), not all
2228
     registers will be available.
2229 19 jeremybenn
 
2230
`irq = VALUE'
2231 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2232 19 jeremybenn
     value 0.
2233
 
2234
`dev_id = 1|2|3'
2235
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2236 82 jeremybenn
     interface to model.  The default value is 1.
2237 19 jeremybenn
 
2238
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2239
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2240
     registers and the `RXD'/`TXD' registers.
2241
 
2242
`rev = VALUE'
2243
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2244 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2245
     be in the range 0-15.  Larger values are truncated with a warning.
2246 346 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2247
     forms bits 24-27.
2248 19 jeremybenn
 
2249
`pio_mode0_t1 = VALUE'
2250
`pio_mode0_t2 = VALUE'
2251
`pio_mode0_t4 = VALUE'
2252
`pio_mode0_teoc = VALUE'
2253
     These parameters specify the timings for use with Programmed
2254 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2255 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2256 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2257 19 jeremybenn
     they do, they will be ignored with a warning.
2258
 
2259
     See the ATA/ATAPI-5 specification for explanations of each of these
2260 82 jeremybenn
     timing parameters.  The default values are:
2261 19 jeremybenn
 
2262
          pio_mode0_t1   =  6
2263
          pio_mode0_t2   = 28
2264
          pio_mode0_t4   =  2
2265
          pio_mode0_teoc = 23
2266
 
2267
`dma_mode0_tm = VALUE'
2268
`dma_mode0_td = VALUE'
2269
`dma_mode0_teoc = VALUE'
2270
     These parameters specify the timings for use with DMA transfers.
2271
     They are specified as the number of clock cycles - 2, rounded up
2272
     to the next highest integer, or zero if that would be negative.
2273 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2274
     ignored with a warning.
2275 19 jeremybenn
 
2276
     See the ATA/ATAPI-5 specification for explanations of each of these
2277 82 jeremybenn
     timing parameters.  The default values are:
2278 19 jeremybenn
 
2279
          dma_mode0_tm   =  4
2280
          dma_mode0_td   = 21
2281
          dma_mode0_teoc = 21
2282
 
2283
 
2284
3.4.9.1 ATA/ATAPI Device Configuration
2285
......................................
2286
 
2287 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2288 19 jeremybenn
device subsection is introduced by
2289
 
2290
     device VALUE
2291
 
2292 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2293
ends with `enddevice'.  Note that if the same device number is
2294
specified more than once, the previous values will be overwritten.
2295
Within the `device' subsection, the following parameters may appear:
2296 19 jeremybenn
 
2297
`type = VALUE'
2298
     VALUEspecifies the type of device: 0 (the default) for "not
2299
     connected", 1 for hard disk simulated in a file and 2 for local
2300
     system hard disk.
2301
 
2302
`file = "FILENAME"'
2303
     `filename' specifies the file to be used for a simulated ATA
2304 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2305 346 jeremybenn
     `"ata_fileN"', where N is the device number.
2306 19 jeremybenn
 
2307
`size = VALUE'
2308
     VALUE specifies the size of a simulated ATA device if the file
2309 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2310 19 jeremybenn
 
2311
`packet = 0|1'
2312 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2313 19 jeremybenn
     default), do not implement the PACKET command feature set.
2314
 
2315
`firmware = "STR"'
2316
     Firmware to report in response to the "Identify Device" command.
2317
     Default `"02207031"'.
2318
 
2319
`heads = VALUE'
2320 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2321 19 jeremybenn
     heads.
2322
 
2323
`sectors = VALUE'
2324 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2325 19 jeremybenn
 
2326
`mwdma = 0|1|2|-1'
2327 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2328 19 jeremybenn
     disable.
2329
 
2330
`pio = 0|1|2|3|4'
2331 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2332 19 jeremybenn
 
2333
 
2334

2335
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2336
 
2337
3.4.10 Generic Peripheral Configuration
2338
---------------------------------------
2339
 
2340
When used as a library (*note Simulator Library: Simulator Library.),
2341
Or1ksim makes provision for any additional peripheral to be implemented
2342 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2343
generates "upcall"s to an external handler.  This interface can support
2344 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2345
for OSCI SystemC (see `http://www.systemc.org').
2346
 
2347
Generic peripheral configuration is described in `section generic'.
2348
This section may appear multiple times, specifying multiple external
2349 82 jeremybenn
peripherals.  The following parameters may be specified.
2350 19 jeremybenn
 
2351
`enabled = 0|1'
2352 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2353 19 jeremybenn
     0, it is disabled.
2354
 
2355
`baseaddr = VALUE'
2356
     Set the base address of the generic peripheral's memory mapped
2357 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2358 19 jeremybenn
     sensible value.
2359
 
2360
     The size of the memory mapped register space is controlled by the
2361
     `size' paramter, described below.
2362
 
2363
`size = VALUE'
2364
     Set the size of the generic peripheral's memory mapped register
2365 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2366 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2367
     parameter `baseaddr' (see above) will be directed to the external
2368
     interface.
2369
 
2370 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2371
     value is zero.  If VALUE is not an exact power of two, accesses to
2372 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2373
     generate a warning, and have no effect (reads will return zero).
2374
 
2375
`name = "STR"'
2376 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2377 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2378 82 jeremybenn
     reporting its status.  The default value is
2379 19 jeremybenn
     `"anonymous external peripheral"'.
2380
 
2381
`byte_enabled = 0|1'
2382
`hw_enabled = 0|1'
2383
`word_enabled = 0|1'
2384
     If 1 (true, the default), these parameters respectively enable the
2385 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2386 19 jeremybenn
     accesses of that width will fail.
2387
 
2388
 
2389

2390
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2391
 
2392
4 Interactive Command Line
2393
**************************
2394
 
2395
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2396 82 jeremybenn
provides the user with an interactive command line.  The commands
2397 19 jeremybenn
available, which may not be abbreviated, are:
2398
 
2399
`q'
2400
     Exit the simulator
2401
 
2402
`r'
2403 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2404 19 jeremybenn
     just executed and next to be executed instructions symbolically
2405
     and the state of the flag in the Supervision Register.
2406
 
2407
`t'
2408
     Execute the next instruction and then display register/instruction
2409
     information as with the `r' command (see above).
2410
 
2411
`run NUM [ hush ]'
2412 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2413 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2414
     above) _unless_ `hush' is specified.
2415
 
2416
`pr REG VALUE'
2417
     Patch register REG with VALUE.
2418
 
2419
`dm FROMADDR [ TOADDR ]'
2420 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2421
     not given, 64 bytes are displayed, starting at FROMADDR.
2422 19 jeremybenn
 
2423
          Caution: The output from this command is broken (a bug).
2424 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2425 19 jeremybenn
          instead of printing out the address at the start of each row,
2426
          it prints the address (of the first of the 16 bytes) before
2427
          _each_ byte.
2428
 
2429
`de FROMADDR [ TOADDR ]'
2430 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2431 19 jeremybenn
     given, 16 instructions are disassembled.
2432
 
2433
     The disassembly is entirely numerical, and gives no symbolic
2434
     information.
2435
 
2436
`pm ADDR VALUE'
2437
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2438
 
2439
`pc VALUE'
2440
     Patch the program counter with VALUE.
2441
 
2442
`cm FROMADDR TOADDR SIZE'
2443
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2444
 
2445
`break ADDR'
2446
     Toggle the breakpoint set at ADDR.
2447
 
2448
`breaks'
2449
     List all set breakpoints
2450
 
2451
`reset'
2452 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2453
     so execution will restart from the reset vector location, 0x100.
2454 19 jeremybenn
 
2455
`hist'
2456
     If saving the execution history has been configured (*note
2457
     Simulator Behavior: Simulator Behavior.), display the execution
2458
     history.
2459
 
2460
`stall'
2461
     Stall the processor, so that control is passed to the debug unit.
2462 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2463 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2464
     debuggers such as GDB.
2465
 
2466
`unstall'
2467 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2468
     This command is useful when debugging the JTAG interface, used by
2469 19 jeremybenn
     debuggers such as GDB.
2470
 
2471
`stats CATEGORY | clear'
2472
     Print the statistics for the given CATEGORY, if available, or
2473 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2474 19 jeremybenn
 
2475
    1
2476
          Miscellaneous statistics: branch predictions (if branch
2477
          predictions are enabled), branch target cache model (if
2478
          enabled), cache (if enbaled), MMU (if enabled) and number of
2479
          addtional load & store cycles.
2480
 
2481
          *Note Configuring the OpenRisc Achitectural Components: Core
2482
          OpenRISC Configuration, for details of how to enable these
2483
          various features.
2484
 
2485
    2
2486 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2487 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2488
 
2489
    3
2490 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2491 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2492
 
2493
    4
2494 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2495 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2496
          Configuration.).
2497
 
2498
    5
2499 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2500 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2501
 
2502
    6
2503 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2504 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2505
 
2506
 
2507
`info'
2508
     Display detailed information about the simulator configuration.
2509
     This is quite a lengthy about, because all MMU TLB information is
2510
     displayed.
2511
 
2512
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2513
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2514 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2515 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2516 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2517 19 jeremybenn
 
2518
     To save to a file, use the redirection function (described after
2519
     this table, below).
2520
 
2521
`dh FROMADDR [ TOADDR ]'
2522
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2523 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2524 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2525
 
2526
     To save to a file, use the redirection function (described after
2527
     this table, below).
2528
 
2529
`setdbch'
2530 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2531 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2532
     channels on the command line.
2533
 
2534
`set SECTION PARAM = VALUE'
2535
     Set the configuration parameter PARA in section SECTION to VALUE.
2536
     *Note Configuration: Configuration, for details of configuration
2537
     parameters and their settings.
2538
 
2539
`debug'
2540 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2541 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2542
     this parameter.
2543
 
2544
          Caution: This is effectively enabling or disabling the debug
2545 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2546 19 jeremybenn
          However using the remote debug interface while the debug unit
2547
          is disabled will lead to undefined behavior and likely crash
2548
          Or1ksim
2549
 
2550
`cuc'
2551
     Enter the the Custom Unit Compiler command prompt (*note CUC
2552
     Configuration: CUC Configuration.).
2553
 
2554
          Caution: The CUC must be properly configured, for this to
2555 82 jeremybenn
          succeed.  In particular a timing file must be available and
2556
          readable.  Otherwise Or1ksim will crash.
2557 19 jeremybenn
 
2558
`help'
2559
     Print out brief information about each command available.
2560
 
2561
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2562 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2563 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2564
     Profiling Utility.).
2565
 
2566
`profile [-vhcq] [-g FILE]'
2567 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2568
     usage as the standalone command (*note Profiling Utility:
2569
     Profiling Utility.).
2570 19 jeremybenn
 
2571
 
2572
For all commands, it is possible to redirect the output to a file, by
2573
using the redirection operator, `>'.
2574
 
2575
     COMMAND > FILENAME
2576
 
2577
This is particularly useful for commands dumping a large amount of
2578
output, such as `dv'.
2579
 
2580
     Caution: Unfortunately there is a serious bug with the redirection
2581 82 jeremybenn
     operator.  It does not return output to standard output after the
2582
     command completes.  Until this bug is fixed, file redirection
2583 19 jeremybenn
     should not be used.
2584
 
2585

2586
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2587
 
2588
5 Verification API (VAPI)
2589
*************************
2590
 
2591
The Verification API (VAPI) provides a TCP/IP interface to allow
2592 82 jeremybenn
components of the simulation to be controlled externally.  The
2593
interface is polled for new requests on each simulated clock cycle.
2594
Components within the simulator may send responses to such requests.
2595 19 jeremybenn
 
2596 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2597
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2598
with a single piece of data (also a 32 bit integer).  On the send side,
2599
it provides for sending a single VAPI ID and data.  However there is no
2600
explicit command-response structure.  Some components just accept
2601
requests (e.g.  to set values), some just generate sends (to report
2602 19 jeremybenn
values), and some do both.
2603
 
2604
Each component has a base ID (32 bit) and its commands will start from
2605 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2606
amongst components.  Request commands will be directed to the component
2607 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2608
 
2609
Thus if there are two components with base IDs of 0x200 and 0x300, and
2610
a request with VAPI ID of 0x203 is received, it will be directed to the
2611
first component as its command #3.
2612
 
2613
The results of VAPI interactions are logged (by default in `vapi.log'
2614
unless an alternative is specified in `section vapi').
2615
 
2616
Currently the following components support VAPI:
2617
 
2618
Debug Unit
2619
     Although the Debug Unit can specify a base VAPI ID, it is not used
2620
     to send commands or receive requests.
2621
 
2622
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2623
     exchanges are logged in the VAPI log file.
2624
 
2625
UART
2626
     If a base VAPI ID is specified, the UART sends details of any
2627
     chars or break characters sent, with dteails of the line control
2628
     register etc encoded in the data packet sent.
2629
 
2630
     This supports a single VAPI command request, but encodes a
2631
     sub-command in the top 8 bits of the associated data.
2632
 
2633
    `0x00'
2634
          This stuffs the least significant 8 bits of the data into the
2635
          serial register of the UART and the next 8 bits into the line
2636
          control register, effectively providing control of the next
2637
          character to be sent or received.
2638
 
2639
    `0x01'
2640
          The divisor latch bytes are set from the least significant 16
2641
          bits of the data.
2642
 
2643
    `0x02'
2644
          The line control register is set from bits 15-8 of the data.
2645
 
2646
    `0x03'
2647
          The UART skew is set from the least significant 16 bits of
2648
          the data
2649
 
2650
    `0x04'
2651
          If the 16th most significant bit of the data is 1, start
2652 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
2653
          are sent or cleared after the number of UART clock divider
2654
          ticks specified by the data (immediately if the data is zero).
2655 19 jeremybenn
 
2656
 
2657
DMA
2658
     Although the DMA unit supports a base VAPI ID in its configuration
2659
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
2660
     implemented.
2661
 
2662
Ethernet
2663 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
2664 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
2665 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
2666 19 jeremybenn
     VAPI requests.
2667
 
2668
    `ETH_VAPI_DATA (0)'
2669
 
2670
    `ETH_VAPI_CTRL (0)'
2671
 
2672
GPIO
2673
     If a base VAPI ID is specified, the GPIO sends out on its base
2674
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
2675
     VAPI ID) any changes in outputs.
2676
 
2677 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
2678 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
2679
     GPIO.
2680
 
2681
    `GPIO_VAPI_DATA (0)'
2682
          Set the next input to the commands data field
2683
 
2684
    `GPIO_VAPI_AUX (1)'
2685
          Set the GPIO auxiliary inputs to the data field
2686
 
2687
    `GPIO_VAPI_CLOCK (2)'
2688
          Add an external GPIO clock trigger of period specified in the
2689
          data field.
2690
 
2691
    `GPIO_VAPI_RGPIO_OE (3)'
2692
          Set the GPIO output enable to the data field
2693
 
2694
    `GPIO_VAPI_RGPIO_INTE (4)'
2695
          Set the next interrupt to the data field
2696
 
2697
    `GPIO_VAPI_RGPIO_PTRIG (5)'
2698
          Set the next trigger to the data field
2699
 
2700
    `GPIO_VAPI_RGPIO_AUX (6)'
2701
          Set the next auxiliary input to the data field
2702
 
2703
    `GPIO_VAPI_RGPIO_CTRL (7)'
2704
          Set th next control input to the data field
2705
 
2706
 
2707
 
2708

2709
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
2710
 
2711
6 A Guide to Or1ksim Internals
2712
******************************
2713
 
2714 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
2715 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
2716 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
2717
Linux manual page for `etags'.  A tag file can be created with:
2718 19 jeremybenn
 
2719
     make tags
2720
 
2721
* Menu:
2722
 
2723
* Coding Conventions::
2724
* Global Data Structures::
2725
* Concepts::
2726
* Internal Debugging::
2727 104 jeremybenn
* Regression Testing::
2728 19 jeremybenn
 
2729

2730
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
2731
 
2732
6.1 Coding Conventions for Or1ksim
2733
==================================
2734
 
2735
This chapter provides some guidelines for coding, to facilitate
2736
extensions to Or1ksim
2737
 
2738
_GNU Coding Standard_
2739
     Code should follow the GNU coding standard for C
2740 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
2741 19 jeremybenn
     through the `indent' program.
2742
 
2743
_`#include' headers_
2744
     All C source code files should include `config.h' before any other
2745
     file.
2746
 
2747
     This should be followed by inclusion of any system headers (but see
2748
     the comments about portability and `port.h' below) and then by any
2749
     Or1ksim package headers.
2750
 
2751
     If `port.h' is required, it should be the first package header to
2752
     be included after the system headers.
2753
 
2754
     All C source code and header files should directly include any
2755 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
2756
     other header having already included it.  The two exceptions are
2757 19 jeremybenn
 
2758
       1. All header files may assume that `config.h' has already been
2759
          included.
2760
 
2761
       2. System headers which impose portability problems should be
2762
          included by using the package header `port.h', rather than
2763 82 jeremybenn
          the system headers themselves.  This is the case for code
2764 19 jeremybenn
          requiring
2765
 
2766
             * `strndup' (from `string.h')
2767
 
2768
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
2769
 
2770
             * `isblank' (from `ctype.h')
2771
 
2772
 
2773
 
2774
_`#include' files once only_
2775
     All include files should be protected by `#ifndef' to ensure their
2776 82 jeremybenn
     definitions are only included once.  For instance a header file
2777 19 jeremybenn
     `X-Y.H' should surround its contents with:
2778
 
2779
          #ifndef X_Y__H
2780
          #define X_Y__H
2781
 
2782
          
2783
 
2784
          #endif  /* X_Y__H */
2785
 
2786
_Avoid `typedef'_
2787
     The GNU coding style for C does not have a clear way to distinguish
2788 82 jeremybenn
     between user type name and user variables.  For this reason
2789 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
2790 82 jeremybenn
     defined types.  This makes the code much easier to read.
2791 19 jeremybenn
 
2792
     There are some `typedef' declarations in the `argtable2' library
2793
     and the ELF and COFF headers, because this code is taken from
2794
     other places.
2795
 
2796
     Within Or1ksim legacy uses of `typedef' have largely been purged,
2797
     except in the Custom Unit Compiler (*note Custom Unit Compiler
2798
     (CUC) Configuration: CUC Configuration.).
2799
 
2800
     The remaining uses of `typedef' occur in two places:
2801
 
2802
        * `port/port.h' defines types to replace those in header files
2803
          that are not available (character functions, string
2804
          duplication, integer types).
2805
 
2806
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
2807
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
2808
          and signed register (`orreg_t') values.
2809
 
2810
 
2811
     Where new types are defined, they should appear in one of these two
2812 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
2813
     `arch.h' should always have the suffix `_h'.
2814 19 jeremybenn
 
2815
_Don't begin names with underscore_
2816
     Names beginning with `_' are intended to be part of the C
2817 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
2818 19 jeremybenn
 
2819
_Keep Non-global top level entities static_
2820
     All top level entities (functions, variables), which are not
2821
     explicitly part of a global interface should be declared static.
2822
     This ensures that unwanted connections are not inadvertently built
2823
     across the program.
2824
 
2825
_Use of `inline'_
2826 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
2827 19 jeremybenn
     out for themselves what is best in this respect.
2828
 
2829
_Initialization_
2830 82 jeremybenn
     All data structures should be explicitly initialized.  In
2831
     particular code should not rely on static data structures being
2832
     initialized to zero.
2833 19 jeremybenn
 
2834
     The rationale is that in future static data structures may become
2835 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
2836 19 jeremybenn
     historically.
2837
 
2838
     A specific case is with new peripherals, which should always
2839
     include a `start' function to pre-initialize all configuration
2840
     parameters to sensible defaults
2841
 
2842
_Configuration Validation_
2843
     All configuration values should be validated, preferably when
2844
     encountered, if not when the `section' is closed, or otherwise at
2845
     run time when the parameter is first used.
2846
 
2847
 
2848

2849
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
2850
 
2851
6.2 Global Data Structures
2852
==========================
2853
 
2854
`config'
2855
     The global variable `config' of type `struct config' holds the
2856
     configuration data for some of the Or1ksim components which are
2857 82 jeremybenn
     always present.  At present the components are:
2858 19 jeremybenn
 
2859
        * The simulator defined in `section sim' (*note Simulator
2860
          Configuration: Simulator Configuration.).
2861
 
2862
        * The Verification API (VAPI) defined  in `section vapi' (*note
2863
          Verification API (VAPI) Configuration: Verification API
2864
          Configuration.).
2865
 
2866
        * The Custom Unit Compiler (CUC), defined in `section cuc'
2867
          (*note Custom Unit Compiler (CUC) Configuration: CUC
2868
          Configuration.).
2869
 
2870
        * The CPU, defined in `section cpu' (*note CPU Configuration:
2871
          CPU Configuration.).
2872
 
2873
        * The data cache (but not the instruction cache), defined in
2874
          `section dc' (*note Cache Configuration: Cache
2875
          Configuration.).
2876
 
2877
        * The power management unit, defined in `section pm' (*note
2878
          Power Management Configuration: Power Management
2879
          Configuration.).
2880
 
2881
        * The programmable interrupt controller, defined in
2882
          `section pic' (*note Interrupt Configuration: Interrupt
2883
          Configuration.).
2884
 
2885
        * Branch prediciton, defined in `section bpb' (*note Branch
2886
          Prediction Configuration: Branch Prediction Configuration.).
2887
 
2888
        * The debug unit, defined in `section debug' (*note Debug
2889
          Interface Configuration: Debug Interface Configuration.).
2890
 
2891
 
2892
     This struct is made of a collection of structs, one for each
2893 82 jeremybenn
     component.  For example the simulator configuration is held in
2894 19 jeremybenn
     `config.sim'.
2895
 
2896
`config'
2897
     This is a linked list of data structures holding configuration data
2898
     for all sections which are not held in the main `config' data
2899 82 jeremybenn
     structure.  In general these are components (such as peripherals
2900
     and memory) which may occur multiple times.  However it also
2901
     handles some architectural components which may occur only once,
2902
     such as the memory management units, the instruction cache, the
2903
     interrupt controller and branch prediction.
2904 19 jeremybenn
 
2905
`runtime'
2906
     The global variable `runtime' of type `struct runtime' holds all
2907 82 jeremybenn
     the runtime information about the simulation.  To access this
2908 19 jeremybenn
     variable, `sim-config.h' must be included.
2909
 
2910
     This struct is itself made of 3 other structs, `cpu' (for CPU run
2911
     time state), `vapi' (for Verification API state) and `cuc' (for
2912
     Custom Unit Compiler state).
2913
 
2914
 
2915

2916
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
2917
 
2918
6.3 Concepts
2919
============
2920
 
2921
_Output Redirection_
2922 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
2923 19 jeremybenn
     should be explicitly written to this stream, or may use the
2924
     `PRINTF' macro, which will write its arguments to this output
2925
     stream.
2926
 
2927
_Reset Hooks_
2928
     Any peripheral may register a routine to be called when the the
2929
     processor is reset by calling `reg_sim_reset', providing a
2930 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
2931 19 jeremybenn
     that function will be called with the data stucture pointer as
2932
     argument.
2933
 
2934
 
2935

2936 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
2937 19 jeremybenn
 
2938
6.4 Internal Debugging
2939
======================
2940
 
2941
The function `debug' is like `printf', but with an extra first
2942 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
2943
the simulator configuration (*note Simulator Behavior: Simulator
2944
Behavior.) is greater than or equal to this value, the remaining
2945
arguments are printed to the current output stream (*note Output
2946
Redirection: Output Redirection.).
2947 19 jeremybenn
 
2948

2949 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
2950
 
2951
6.5 Regression Testing
2952
======================
2953
 
2954
Or1ksim now includes a regression test suite for both standalone and
2955
library usage as described earlier (*note Building and Installing:
2956
Build and Install.).  Running the tests requires that the OpenRISC
2957
toolchain and DejaGNU are both installed.
2958
 
2959
Tests are written using `expect', a derivative of TCL.  Documentation
2960
of DejaGnu, `expect' and TCL are freely available on the Web.  The
2961
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
2962
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
2963
provides a concise introduction.
2964
 
2965
All test code is found in the `testsuite' directory.  The key files and
2966
directories used are as follows.
2967
 
2968
`global-conf.exp'
2969
     This is the global DejaGNU configuration file used to set up
2970
     parameters common to all tests.  If the user has the environment
2971
     varialbe `DEJAGNU' defined, it will be used instead, but this is
2972
     not recommended.
2973
 
2974
`Makefile.am'
2975
     This is the top level `automake' file for the testsuite.  The only
2976
     changes likely to be needed here is additional local cleanup of
2977
     files created by new tests.
2978
 
2979
`README'
2980
     This contains details of all the tests
2981
 
2982
`config'
2983
     This contains DejaGnu board configurations.  Since the tests are
2984
     generally run on a Unix host, this should just contain `Unix.exp'.
2985
 
2986
`lib'
2987
     This contains DejaGnu tool specific configurations.  "Tool" has a
2988
     specific meaning in DejaGNU, referring just to a grouping of
2989
     tests.  In this case there are two such "tools", "or1ksim" and
2990
     "libsim" for tests of the standalone tool and tests of the library.
2991
 
2992
     Corresponding to this, there are two tool specific configuration
2993
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
2994
     procedures for common use among the tests.
2995
 
2996
`libsim.tests'
2997
`or1ksim.tests'
2998
     These are the directories of tests of the Or1ksim library.  They
2999
     also include Or1ksim configuration files and each has a
3000
     `Makefile.am' file.  `Makefile.am' should be updated whenever
3001
     files are added to this directory, to ensure they are included in
3002
     the distribution.
3003
 
3004
`test-code'
3005
     These are all the test programs to be compiled on the host (each
3006
     in its own directory).  In general these are programs to support
3007
     testing of the library, and build various programs linking in the
3008
     library.
3009
 
3010
`test-code'
3011
     These are all the test programs to be compiled with the OpenRISC
3012
     tool chain to run with either standalone Or1ksim or the library.
3013
     This directory includes its own `configure.ac', since it must set
3014
     up a separate tool chain based on the target, not the host.
3015
 
3016
 
3017
To add a new test needs the following steps.
3018
 
3019 346 jeremybenn
   * Put new host C code in its own directory within `test-code'.  Add
3020 104 jeremybenn
     the directory to the existing `Makefile.am' in the `test-code'
3021
     directory and create a `Makefile.am' in the new directory to drive
3022 346 jeremybenn
     building the test program(s).  Don't forget to add the new
3023 104 jeremybenn
     `Makefile' to the top level `configure.ac' so it gets generated.
3024
     Not all tests require code here.
3025
 
3026 346 jeremybenn
   * Put new target C code in its own directory within `test-code-or1k'.
3027
     Once again modify & create `Makefile.am'.  This time modify the
3028
     `configure.ac' in the `test-code-or1k' so the `Makefile' gets
3029
     generated.  The existing programs provide examples to start from,
3030
     including custom linker scripts where needed.
3031 104 jeremybenn
 
3032
   * Add one or more tests and configuration files to the relevant
3033 346 jeremybenn
     "tool" test directory.  Use the existing tests as templates.  They
3034 104 jeremybenn
     make heavy use of the `expect'/TCL procedures in the `config'
3035
     directory to facilitate driving the tests.
3036
 
3037
 
3038

3039 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
3040
 
3041
7 GNU Free Documentation License
3042
********************************
3043
 
3044
                      Version 1.2, November 2002
3045
 
3046
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
3047
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
3048
 
3049
     Everyone is permitted to copy and distribute verbatim copies
3050
     of this license document, but changing it is not allowed.
3051
 
3052
  0. PREAMBLE
3053
 
3054
     The purpose of this License is to make a manual, textbook, or other
3055
     functional and useful document "free" in the sense of freedom: to
3056
     assure everyone the effective freedom to copy and redistribute it,
3057
     with or without modifying it, either commercially or
3058
     noncommercially.  Secondarily, this License preserves for the
3059
     author and publisher a way to get credit for their work, while not
3060
     being considered responsible for modifications made by others.
3061
 
3062
     This License is a kind of "copyleft", which means that derivative
3063
     works of the document must themselves be free in the same sense.
3064
     It complements the GNU General Public License, which is a copyleft
3065
     license designed for free software.
3066
 
3067
     We have designed this License in order to use it for manuals for
3068
     free software, because free software needs free documentation: a
3069
     free program should come with manuals providing the same freedoms
3070
     that the software does.  But this License is not limited to
3071
     software manuals; it can be used for any textual work, regardless
3072
     of subject matter or whether it is published as a printed book.
3073
     We recommend this License principally for works whose purpose is
3074
     instruction or reference.
3075
 
3076
  1. APPLICABILITY AND DEFINITIONS
3077
 
3078
     This License applies to any manual or other work, in any medium,
3079
     that contains a notice placed by the copyright holder saying it
3080
     can be distributed under the terms of this License.  Such a notice
3081
     grants a world-wide, royalty-free license, unlimited in duration,
3082
     to use that work under the conditions stated herein.  The
3083
     "Document", below, refers to any such manual or work.  Any member
3084
     of the public is a licensee, and is addressed as "you".  You
3085
     accept the license if you copy, modify or distribute the work in a
3086
     way requiring permission under copyright law.
3087
 
3088
     A "Modified Version" of the Document means any work containing the
3089
     Document or a portion of it, either copied verbatim, or with
3090
     modifications and/or translated into another language.
3091
 
3092
     A "Secondary Section" is a named appendix or a front-matter section
3093
     of the Document that deals exclusively with the relationship of the
3094
     publishers or authors of the Document to the Document's overall
3095
     subject (or to related matters) and contains nothing that could
3096
     fall directly within that overall subject.  (Thus, if the Document
3097
     is in part a textbook of mathematics, a Secondary Section may not
3098
     explain any mathematics.)  The relationship could be a matter of
3099
     historical connection with the subject or with related matters, or
3100
     of legal, commercial, philosophical, ethical or political position
3101
     regarding them.
3102
 
3103
     The "Invariant Sections" are certain Secondary Sections whose
3104
     titles are designated, as being those of Invariant Sections, in
3105
     the notice that says that the Document is released under this
3106
     License.  If a section does not fit the above definition of
3107
     Secondary then it is not allowed to be designated as Invariant.
3108
     The Document may contain zero Invariant Sections.  If the Document
3109
     does not identify any Invariant Sections then there are none.
3110
 
3111
     The "Cover Texts" are certain short passages of text that are
3112
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3113
     that says that the Document is released under this License.  A
3114
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3115
     be at most 25 words.
3116
 
3117
     A "Transparent" copy of the Document means a machine-readable copy,
3118
     represented in a format whose specification is available to the
3119
     general public, that is suitable for revising the document
3120
     straightforwardly with generic text editors or (for images
3121
     composed of pixels) generic paint programs or (for drawings) some
3122
     widely available drawing editor, and that is suitable for input to
3123
     text formatters or for automatic translation to a variety of
3124
     formats suitable for input to text formatters.  A copy made in an
3125
     otherwise Transparent file format whose markup, or absence of
3126
     markup, has been arranged to thwart or discourage subsequent
3127
     modification by readers is not Transparent.  An image format is
3128
     not Transparent if used for any substantial amount of text.  A
3129
     copy that is not "Transparent" is called "Opaque".
3130
 
3131
     Examples of suitable formats for Transparent copies include plain
3132
     ASCII without markup, Texinfo input format, LaTeX input format,
3133
     SGML or XML using a publicly available DTD, and
3134
     standard-conforming simple HTML, PostScript or PDF designed for
3135
     human modification.  Examples of transparent image formats include
3136
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3137
     can be read and edited only by proprietary word processors, SGML or
3138
     XML for which the DTD and/or processing tools are not generally
3139
     available, and the machine-generated HTML, PostScript or PDF
3140
     produced by some word processors for output purposes only.
3141
 
3142
     The "Title Page" means, for a printed book, the title page itself,
3143
     plus such following pages as are needed to hold, legibly, the
3144
     material this License requires to appear in the title page.  For
3145
     works in formats which do not have any title page as such, "Title
3146
     Page" means the text near the most prominent appearance of the
3147
     work's title, preceding the beginning of the body of the text.
3148
 
3149
     A section "Entitled XYZ" means a named subunit of the Document
3150
     whose title either is precisely XYZ or contains XYZ in parentheses
3151
     following text that translates XYZ in another language.  (Here XYZ
3152
     stands for a specific section name mentioned below, such as
3153
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3154
     To "Preserve the Title" of such a section when you modify the
3155
     Document means that it remains a section "Entitled XYZ" according
3156
     to this definition.
3157
 
3158
     The Document may include Warranty Disclaimers next to the notice
3159
     which states that this License applies to the Document.  These
3160
     Warranty Disclaimers are considered to be included by reference in
3161
     this License, but only as regards disclaiming warranties: any other
3162
     implication that these Warranty Disclaimers may have is void and
3163
     has no effect on the meaning of this License.
3164
 
3165
  2. VERBATIM COPYING
3166
 
3167
     You may copy and distribute the Document in any medium, either
3168
     commercially or noncommercially, provided that this License, the
3169
     copyright notices, and the license notice saying this License
3170
     applies to the Document are reproduced in all copies, and that you
3171
     add no other conditions whatsoever to those of this License.  You
3172
     may not use technical measures to obstruct or control the reading
3173
     or further copying of the copies you make or distribute.  However,
3174
     you may accept compensation in exchange for copies.  If you
3175
     distribute a large enough number of copies you must also follow
3176
     the conditions in section 3.
3177
 
3178
     You may also lend copies, under the same conditions stated above,
3179
     and you may publicly display copies.
3180
 
3181
  3. COPYING IN QUANTITY
3182
 
3183
     If you publish printed copies (or copies in media that commonly
3184
     have printed covers) of the Document, numbering more than 100, and
3185
     the Document's license notice requires Cover Texts, you must
3186
     enclose the copies in covers that carry, clearly and legibly, all
3187
     these Cover Texts: Front-Cover Texts on the front cover, and
3188
     Back-Cover Texts on the back cover.  Both covers must also clearly
3189
     and legibly identify you as the publisher of these copies.  The
3190
     front cover must present the full title with all words of the
3191
     title equally prominent and visible.  You may add other material
3192
     on the covers in addition.  Copying with changes limited to the
3193
     covers, as long as they preserve the title of the Document and
3194
     satisfy these conditions, can be treated as verbatim copying in
3195
     other respects.
3196
 
3197
     If the required texts for either cover are too voluminous to fit
3198
     legibly, you should put the first ones listed (as many as fit
3199
     reasonably) on the actual cover, and continue the rest onto
3200
     adjacent pages.
3201
 
3202
     If you publish or distribute Opaque copies of the Document
3203
     numbering more than 100, you must either include a
3204
     machine-readable Transparent copy along with each Opaque copy, or
3205
     state in or with each Opaque copy a computer-network location from
3206
     which the general network-using public has access to download
3207
     using public-standard network protocols a complete Transparent
3208
     copy of the Document, free of added material.  If you use the
3209
     latter option, you must take reasonably prudent steps, when you
3210
     begin distribution of Opaque copies in quantity, to ensure that
3211
     this Transparent copy will remain thus accessible at the stated
3212
     location until at least one year after the last time you
3213
     distribute an Opaque copy (directly or through your agents or
3214
     retailers) of that edition to the public.
3215
 
3216
     It is requested, but not required, that you contact the authors of
3217
     the Document well before redistributing any large number of
3218
     copies, to give them a chance to provide you with an updated
3219
     version of the Document.
3220
 
3221
  4. MODIFICATIONS
3222
 
3223
     You may copy and distribute a Modified Version of the Document
3224
     under the conditions of sections 2 and 3 above, provided that you
3225
     release the Modified Version under precisely this License, with
3226
     the Modified Version filling the role of the Document, thus
3227
     licensing distribution and modification of the Modified Version to
3228
     whoever possesses a copy of it.  In addition, you must do these
3229
     things in the Modified Version:
3230
 
3231
       A. Use in the Title Page (and on the covers, if any) a title
3232
          distinct from that of the Document, and from those of
3233
          previous versions (which should, if there were any, be listed
3234
          in the History section of the Document).  You may use the
3235
          same title as a previous version if the original publisher of
3236
          that version gives permission.
3237
 
3238
       B. List on the Title Page, as authors, one or more persons or
3239
          entities responsible for authorship of the modifications in
3240
          the Modified Version, together with at least five of the
3241
          principal authors of the Document (all of its principal
3242
          authors, if it has fewer than five), unless they release you
3243
          from this requirement.
3244
 
3245
       C. State on the Title page the name of the publisher of the
3246
          Modified Version, as the publisher.
3247
 
3248
       D. Preserve all the copyright notices of the Document.
3249
 
3250
       E. Add an appropriate copyright notice for your modifications
3251
          adjacent to the other copyright notices.
3252
 
3253
       F. Include, immediately after the copyright notices, a license
3254
          notice giving the public permission to use the Modified
3255
          Version under the terms of this License, in the form shown in
3256
          the Addendum below.
3257
 
3258
       G. Preserve in that license notice the full lists of Invariant
3259
          Sections and required Cover Texts given in the Document's
3260
          license notice.
3261
 
3262
       H. Include an unaltered copy of this License.
3263
 
3264
       I. Preserve the section Entitled "History", Preserve its Title,
3265
          and add to it an item stating at least the title, year, new
3266
          authors, and publisher of the Modified Version as given on
3267
          the Title Page.  If there is no section Entitled "History" in
3268
          the Document, create one stating the title, year, authors,
3269
          and publisher of the Document as given on its Title Page,
3270
          then add an item describing the Modified Version as stated in
3271
          the previous sentence.
3272
 
3273
       J. Preserve the network location, if any, given in the Document
3274
          for public access to a Transparent copy of the Document, and
3275
          likewise the network locations given in the Document for
3276
          previous versions it was based on.  These may be placed in
3277
          the "History" section.  You may omit a network location for a
3278
          work that was published at least four years before the
3279
          Document itself, or if the original publisher of the version
3280
          it refers to gives permission.
3281
 
3282
       K. For any section Entitled "Acknowledgements" or "Dedications",
3283
          Preserve the Title of the section, and preserve in the
3284
          section all the substance and tone of each of the contributor
3285
          acknowledgements and/or dedications given therein.
3286
 
3287
       L. Preserve all the Invariant Sections of the Document,
3288
          unaltered in their text and in their titles.  Section numbers
3289
          or the equivalent are not considered part of the section
3290
          titles.
3291
 
3292
       M. Delete any section Entitled "Endorsements".  Such a section
3293
          may not be included in the Modified Version.
3294
 
3295
       N. Do not retitle any existing section to be Entitled
3296
          "Endorsements" or to conflict in title with any Invariant
3297
          Section.
3298
 
3299
       O. Preserve any Warranty Disclaimers.
3300
 
3301
     If the Modified Version includes new front-matter sections or
3302
     appendices that qualify as Secondary Sections and contain no
3303
     material copied from the Document, you may at your option
3304
     designate some or all of these sections as invariant.  To do this,
3305
     add their titles to the list of Invariant Sections in the Modified
3306
     Version's license notice.  These titles must be distinct from any
3307
     other section titles.
3308
 
3309
     You may add a section Entitled "Endorsements", provided it contains
3310
     nothing but endorsements of your Modified Version by various
3311
     parties--for example, statements of peer review or that the text
3312
     has been approved by an organization as the authoritative
3313
     definition of a standard.
3314
 
3315
     You may add a passage of up to five words as a Front-Cover Text,
3316
     and a passage of up to 25 words as a Back-Cover Text, to the end
3317
     of the list of Cover Texts in the Modified Version.  Only one
3318
     passage of Front-Cover Text and one of Back-Cover Text may be
3319
     added by (or through arrangements made by) any one entity.  If the
3320
     Document already includes a cover text for the same cover,
3321
     previously added by you or by arrangement made by the same entity
3322
     you are acting on behalf of, you may not add another; but you may
3323
     replace the old one, on explicit permission from the previous
3324
     publisher that added the old one.
3325
 
3326
     The author(s) and publisher(s) of the Document do not by this
3327
     License give permission to use their names for publicity for or to
3328
     assert or imply endorsement of any Modified Version.
3329
 
3330
  5. COMBINING DOCUMENTS
3331
 
3332
     You may combine the Document with other documents released under
3333
     this License, under the terms defined in section 4 above for
3334
     modified versions, provided that you include in the combination
3335
     all of the Invariant Sections of all of the original documents,
3336
     unmodified, and list them all as Invariant Sections of your
3337
     combined work in its license notice, and that you preserve all
3338
     their Warranty Disclaimers.
3339
 
3340
     The combined work need only contain one copy of this License, and
3341
     multiple identical Invariant Sections may be replaced with a single
3342
     copy.  If there are multiple Invariant Sections with the same name
3343
     but different contents, make the title of each such section unique
3344
     by adding at the end of it, in parentheses, the name of the
3345
     original author or publisher of that section if known, or else a
3346
     unique number.  Make the same adjustment to the section titles in
3347
     the list of Invariant Sections in the license notice of the
3348
     combined work.
3349
 
3350
     In the combination, you must combine any sections Entitled
3351
     "History" in the various original documents, forming one section
3352
     Entitled "History"; likewise combine any sections Entitled
3353
     "Acknowledgements", and any sections Entitled "Dedications".  You
3354
     must delete all sections Entitled "Endorsements."
3355
 
3356
  6. COLLECTIONS OF DOCUMENTS
3357
 
3358
     You may make a collection consisting of the Document and other
3359
     documents released under this License, and replace the individual
3360
     copies of this License in the various documents with a single copy
3361
     that is included in the collection, provided that you follow the
3362
     rules of this License for verbatim copying of each of the
3363
     documents in all other respects.
3364
 
3365
     You may extract a single document from such a collection, and
3366
     distribute it individually under this License, provided you insert
3367
     a copy of this License into the extracted document, and follow
3368
     this License in all other respects regarding verbatim copying of
3369
     that document.
3370
 
3371
  7. AGGREGATION WITH INDEPENDENT WORKS
3372
 
3373
     A compilation of the Document or its derivatives with other
3374
     separate and independent documents or works, in or on a volume of
3375
     a storage or distribution medium, is called an "aggregate" if the
3376
     copyright resulting from the compilation is not used to limit the
3377
     legal rights of the compilation's users beyond what the individual
3378
     works permit.  When the Document is included in an aggregate, this
3379
     License does not apply to the other works in the aggregate which
3380
     are not themselves derivative works of the Document.
3381
 
3382
     If the Cover Text requirement of section 3 is applicable to these
3383
     copies of the Document, then if the Document is less than one half
3384
     of the entire aggregate, the Document's Cover Texts may be placed
3385
     on covers that bracket the Document within the aggregate, or the
3386
     electronic equivalent of covers if the Document is in electronic
3387
     form.  Otherwise they must appear on printed covers that bracket
3388
     the whole aggregate.
3389
 
3390
  8. TRANSLATION
3391
 
3392
     Translation is considered a kind of modification, so you may
3393
     distribute translations of the Document under the terms of section
3394
     4.  Replacing Invariant Sections with translations requires special
3395
     permission from their copyright holders, but you may include
3396
     translations of some or all Invariant Sections in addition to the
3397
     original versions of these Invariant Sections.  You may include a
3398
     translation of this License, and all the license notices in the
3399
     Document, and any Warranty Disclaimers, provided that you also
3400
     include the original English version of this License and the
3401
     original versions of those notices and disclaimers.  In case of a
3402
     disagreement between the translation and the original version of
3403
     this License or a notice or disclaimer, the original version will
3404
     prevail.
3405
 
3406
     If a section in the Document is Entitled "Acknowledgements",
3407
     "Dedications", or "History", the requirement (section 4) to
3408
     Preserve its Title (section 1) will typically require changing the
3409
     actual title.
3410
 
3411
  9. TERMINATION
3412
 
3413
     You may not copy, modify, sublicense, or distribute the Document
3414
     except as expressly provided for under this License.  Any other
3415
     attempt to copy, modify, sublicense or distribute the Document is
3416
     void, and will automatically terminate your rights under this
3417
     License.  However, parties who have received copies, or rights,
3418
     from you under this License will not have their licenses
3419
     terminated so long as such parties remain in full compliance.
3420
 
3421
 10. FUTURE REVISIONS OF THIS LICENSE
3422
 
3423
     The Free Software Foundation may publish new, revised versions of
3424
     the GNU Free Documentation License from time to time.  Such new
3425
     versions will be similar in spirit to the present version, but may
3426
     differ in detail to address new problems or concerns.  See
3427
     `http://www.gnu.org/copyleft/'.
3428
 
3429
     Each version of the License is given a distinguishing version
3430
     number.  If the Document specifies that a particular numbered
3431
     version of this License "or any later version" applies to it, you
3432
     have the option of following the terms and conditions either of
3433
     that specified version or of any later version that has been
3434
     published (not as a draft) by the Free Software Foundation.  If
3435
     the Document does not specify a version number of this License,
3436
     you may choose any version ever published (not as a draft) by the
3437
     Free Software Foundation.
3438
 
3439
ADDENDUM: How to use this License for your documents
3440
====================================================
3441
 
3442
To use this License in a document you have written, include a copy of
3443
the License in the document and put the following copyright and license
3444
notices just after the title page:
3445
 
3446
       Copyright (C)  YEAR  YOUR NAME.
3447
       Permission is granted to copy, distribute and/or modify this document
3448
       under the terms of the GNU Free Documentation License, Version 1.2
3449
       or any later version published by the Free Software Foundation;
3450
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3451
       Texts.  A copy of the license is included in the section entitled ``GNU
3452
       Free Documentation License''.
3453
 
3454
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3455
replace the "with...Texts." line with this:
3456
 
3457
         with the Invariant Sections being LIST THEIR TITLES, with
3458
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3459
         being LIST.
3460
 
3461
If you have Invariant Sections without Cover Texts, or some other
3462
combination of the three, merge those two alternatives to suit the
3463
situation.
3464
 
3465
If your document contains nontrivial examples of program code, we
3466
recommend releasing these examples in parallel under your choice of
3467
free software license, such as the GNU General Public License, to
3468
permit their use in free software.
3469
 
3470

3471
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3472
 
3473
Index
3474
*****
3475
 
3476
 
3477
* Menu:
3478
3479
* --cumulative:                          Profiling Utility.   (line  26)
3480
* --debug-config:                        Standalone Simulator.
3481 346 jeremybenn
                                                              (line  81)
3482 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3483 127 jeremybenn
                                                              (line 105)
3484 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3485 127 jeremybenn
                                                              (line 118)
3486 124 jeremybenn
* --disable-debug:                       Configuring the Build.
3487 127 jeremybenn
                                                              (line  98)
3488 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3489 104 jeremybenn
                                                              (line  59)
3490 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3491 127 jeremybenn
                                                              (line 133)
3492 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3493 104 jeremybenn
                                                              (line  30)
3494 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3495 127 jeremybenn
                                                              (line  92)
3496
* --disable-unsigned-xori:               Configuring the Build.
3497 104 jeremybenn
                                                              (line  69)
3498 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3499 127 jeremybenn
                                                              (line 104)
3500 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3501 127 jeremybenn
                                                              (line 117)
3502 124 jeremybenn
* --enable-debug:                        Configuring the Build.
3503 127 jeremybenn
                                                              (line  97)
3504 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3505 104 jeremybenn
                                                              (line  58)
3506 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3507 104 jeremybenn
                                                              (line  37)
3508 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3509 346 jeremybenn
                                                              (line 115)
3510 19 jeremybenn
* --enable-ov-flag:                      Configuring the Build.
3511 127 jeremybenn
                                                              (line 132)
3512 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3513 346 jeremybenn
                                                              (line 112)
3514 19 jeremybenn
* --enable-profiling:                    Configuring the Build.
3515 104 jeremybenn
                                                              (line  29)
3516 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3517 127 jeremybenn
                                                              (line  91)
3518
* --enable-unsigned-xori:                Configuring the Build.
3519 104 jeremybenn
                                                              (line  68)
3520 19 jeremybenn
* --file:                                Standalone Simulator.
3521 346 jeremybenn
                                                              (line  39)
3522 19 jeremybenn
* --filename:                            Memory Profiling Utility.
3523
                                                              (line  51)
3524
* --generate:                            Profiling Utility.   (line  34)
3525
* --group:                               Memory Profiling Utility.
3526
                                                              (line  47)
3527
* --help:                                Standalone Simulator.
3528 346 jeremybenn
                                                              (line  21)
3529 19 jeremybenn
* --help (memory profiling utility):     Memory Profiling Utility.
3530
                                                              (line  22)
3531
* --help (profiling utility):            Profiling Utility.   (line  22)
3532
* --interactive:                         Standalone Simulator.
3533 346 jeremybenn
                                                              (line  25)
3534
* --memory:                              Standalone Simulator.
3535
                                                              (line  65)
3536 19 jeremybenn
* --mode:                                Memory Profiling Utility.
3537
                                                              (line  26)
3538
* --nosrv:                               Standalone Simulator.
3539 346 jeremybenn
                                                              (line  47)
3540
* --quiet <1>:                           Profiling Utility.   (line  30)
3541
* --quiet:                               Standalone Simulator.
3542
                                                              (line  29)
3543
* --report-memory-errors:                Standalone Simulator.
3544
                                                              (line  86)
3545 19 jeremybenn
* --srv:                                 Standalone Simulator.
3546 346 jeremybenn
                                                              (line  55)
3547 19 jeremybenn
* --strict-npc:                          Standalone Simulator.
3548 346 jeremybenn
                                                              (line  95)
3549
* --verbose:                             Standalone Simulator.
3550
                                                              (line  33)
3551 19 jeremybenn
* --version:                             Standalone Simulator.
3552 346 jeremybenn
                                                              (line  17)
3553 19 jeremybenn
* --version (memory profiling utility):  Memory Profiling Utility.
3554
                                                              (line  17)
3555
* --version (profiling utility):         Profiling Utility.   (line  17)
3556
* -c:                                    Profiling Utility.   (line  26)
3557
* -d:                                    Standalone Simulator.
3558 346 jeremybenn
                                                              (line  81)
3559 19 jeremybenn
* -f <1>:                                Memory Profiling Utility.
3560
                                                              (line  51)
3561
* -f:                                    Standalone Simulator.
3562 346 jeremybenn
                                                              (line  39)
3563
* -g <1>:                                Memory Profiling Utility.
3564 19 jeremybenn
                                                              (line  47)
3565 346 jeremybenn
* -g:                                    Profiling Utility.   (line  34)
3566 19 jeremybenn
* -h:                                    Standalone Simulator.
3567 346 jeremybenn
                                                              (line  21)
3568 19 jeremybenn
* -h (memory profiling utility):         Memory Profiling Utility.
3569
                                                              (line  22)
3570
* -h (profiling utility):                Profiling Utility.   (line  22)
3571
* -i:                                    Standalone Simulator.
3572 346 jeremybenn
                                                              (line  25)
3573
* -m <1>:                                Memory Profiling Utility.
3574 19 jeremybenn
                                                              (line  26)
3575 346 jeremybenn
* -m:                                    Standalone Simulator.
3576
                                                              (line  65)
3577
* -q <1>:                                Profiling Utility.   (line  30)
3578
* -q:                                    Standalone Simulator.
3579
                                                              (line  29)
3580
* -V:                                    Standalone Simulator.
3581
                                                              (line  33)
3582 19 jeremybenn
* -v:                                    Standalone Simulator.
3583 346 jeremybenn
                                                              (line  17)
3584 19 jeremybenn
* -v (memory profiling utility):         Memory Profiling Utility.
3585
                                                              (line  17)
3586
* -v (profiling utility):                Profiling Utility.   (line  17)
3587
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3588
                                                              (line  49)
3589
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3590
                                                              (line  55)
3591
* 0x02 UART VAPI sub-command (UART verification): Verification API.
3592
                                                              (line  59)
3593
* 0x03 UART VAPI sub-command (UART verification): Verification API.
3594
                                                              (line  62)
3595
* 0x04 UART VAPI sub-command (UART verification): Verification API.
3596
                                                              (line  66)
3597
* 16550 (UART configuration):            UART Configuration.  (line  73)
3598 82 jeremybenn
* all tests enabled:                     Configuring the Build.
3599 127 jeremybenn
                                                              (line 105)
3600 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
3601 127 jeremybenn
                                                              (line  98)
3602 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
3603
                                                              (line   6)
3604
* ATA/ATAPI device configuration:        Disc Interface Configuration.
3605
                                                              (line  88)
3606
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
3607
                                                              (line  32)
3608
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
3609
                                                              (line  22)
3610
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
3611
* baseaddr (Ethernet configuration):     Ethernet Configuration.
3612
                                                              (line  22)
3613
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
3614
                                                              (line  20)
3615
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
3616
                                                              (line  22)
3617
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
3618
* baseaddr (keyboard configuration):     Keyboard Configuration.
3619
                                                              (line  36)
3620
* baseaddr (memory configuration):       Memory Configuration.
3621 240 julius
                                                              (line  88)
3622 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
3623 98 jeremybenn
                                                              (line  46)
3624 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
3625
* baseaddr (VGA configuration):          Display Interface Configuration.
3626
                                                              (line  26)
3627
* blocksize (cache configuration):       Cache Configuration. (line  29)
3628
* BPB configuration:                     Branch Prediction Configuration.
3629
                                                              (line   6)
3630
* branch prediction configuration:       Branch Prediction Configuration.
3631
                                                              (line   6)
3632
* break (Interactive CLI):               Interactive Command Line.
3633
                                                              (line  57)
3634
* breakpoint list (Interactive CLI):     Interactive Command Line.
3635
                                                              (line  60)
3636
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
3637
                                                              (line  57)
3638
* breaks (Interactive CLI):              Interactive Command Line.
3639
                                                              (line  60)
3640
* btic (branch prediction configuration): Branch Prediction Configuration.
3641
                                                              (line  19)
3642
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3643
                                                              (line  48)
3644
* cache configuration:                   Cache Configuration. (line   6)
3645 346 jeremybenn
* calling_convention (CUC configuration): CUC Configuration.  (line  37)
3646 19 jeremybenn
* ce (memory configuration):             Memory Configuration.
3647 240 julius
                                                              (line 118)
3648 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
3649
* channel (UART configuration):          UART Configuration.  (line  29)
3650
* clear breakpoint (Interactive CLI):    Interactive Command Line.
3651
                                                              (line  57)
3652 202 julius
* clkcycle (simulator configuration):    Simulator Behavior.  (line 115)
3653 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
3654
                                                              (line  54)
3655
* command line for Or1ksim standalone use: Standalone Simulator.
3656
                                                              (line   6)
3657
* complex model:                         Configuring the Build.
3658 104 jeremybenn
                                                              (line  37)
3659 19 jeremybenn
* config:                                Global Data Structures.
3660
                                                              (line   7)
3661
* config.bpb:                            Global Data Structures.
3662
                                                              (line  37)
3663
* config.cpu:                            Global Data Structures.
3664
                                                              (line  22)
3665
* config.cuc:                            Global Data Structures.
3666
                                                              (line  18)
3667
* config.dc:                             Global Data Structures.
3668
                                                              (line  25)
3669
* config.debug:                          Global Data Structures.
3670
                                                              (line  40)
3671
* config.pic:                            Global Data Structures.
3672
                                                              (line  33)
3673
* config.pm:                             Global Data Structures.
3674
                                                              (line  29)
3675
* config.sim:                            Global Data Structures.
3676
                                                              (line  11)
3677
* config.vapi:                           Global Data Structures.
3678
                                                              (line  14)
3679
* configuration dynamic structure:       Global Data Structures.
3680
                                                              (line  49)
3681
* configuration file structure:          Configuration File Format.
3682
                                                              (line   6)
3683
* configuration global structure:        Global Data Structures.
3684
                                                              (line   7)
3685
* configuration info (Interactive CLI):  Interactive Command Line.
3686
                                                              (line 119)
3687
* configuration of generic peripherals:  Generic Peripheral Configuration.
3688
                                                              (line   6)
3689
* configuration parameter setting (Interactive CLI): Interactive Command Line.
3690
                                                              (line 146)
3691
* configuring branch prediction:         Branch Prediction Configuration.
3692
                                                              (line   6)
3693
* configuring data & instruction caches: Cache Configuration. (line   6)
3694
* configuring data & instruction MMUs:   Memory Management Configuration.
3695
                                                              (line   6)
3696
* configuring DMA:                       DMA Configuration.   (line   6)
3697
* configuring memory:                    Memory Configuration.
3698
                                                              (line   6)
3699
* configuring Or1ksim:                   Configuration.       (line   6)
3700
* configuring power management:          Power Management Configuration.
3701
                                                              (line   6)
3702
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
3703
                                                              (line   6)
3704
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
3705
* configuring the CPU:                   CPU Configuration.   (line   6)
3706
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
3707
                                                              (line   6)
3708
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
3709
                                                              (line   6)
3710
* configuring the Ethernet interface:    Ethernet Configuration.
3711
                                                              (line   6)
3712
* configuring the frame buffer:          Frame Buffer Configuration.
3713
                                                              (line   6)
3714
* configuring the GPIO:                  GPIO Configuration.  (line   6)
3715
* configuring the interrupt controller:  Interrupt Configuration.
3716
                                                              (line   6)
3717
* configuring the keyboard interface:    Keyboard Configuration.
3718
                                                              (line   6)
3719
* configuring the memory controller:     Memory Controller Configuration.
3720
                                                              (line   6)
3721
* configuring the processor:             CPU Configuration.   (line   6)
3722
* configuring the PS2 interface:         Keyboard Configuration.
3723
                                                              (line   6)
3724
* configuring the UART:                  UART Configuration.  (line   6)
3725
* configuring the Verification API (VAPI): Verification API Configuration.
3726
                                                              (line   6)
3727
* configuring the VGA interface:         Display Interface Configuration.
3728
                                                              (line   6)
3729
* copying memory (Interactive CLI):      Interactive Command Line.
3730
                                                              (line  54)
3731
* CPU configuration:                     CPU Configuration.   (line   6)
3732
* CUC configuration:                     CUC Configuration.   (line   6)
3733
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
3734
                                                              (line 162)
3735
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
3736
* data cache configuration:              Cache Configuration. (line   6)
3737
* data MMU configuration:                Memory Management Configuration.
3738
                                                              (line   6)
3739
* DCGE (power management register):      Power Management Configuration.
3740
                                                              (line  21)
3741
* debug (Interactive CLI):               Interactive Command Line.
3742 346 jeremybenn
                                                              (line 151)
3743 19 jeremybenn
* debug (simulator configuration):       Simulator Behavior.  (line  13)
3744
* debug channel toggle (Interactive CLI): Interactive Command Line.
3745
                                                              (line 141)
3746
* debug interface configuration:         Debug Interface Configuration.
3747
                                                              (line   6)
3748
* debug mode toggle (Interactive CLI):   Interactive Command Line.
3749
                                                              (line 151)
3750
* debug unit configuration:              Debug Interface Configuration.
3751
                                                              (line   6)
3752
* Debug Unit verification (VAPI):        Verification API.    (line  34)
3753
* debugging enabled (Argtable2):         Configuring the Build.
3754 127 jeremybenn
                                                              (line  98)
3755 104 jeremybenn
* DejaGnu board configurations:          Regression Testing.  (line  35)
3756
* DejaGnu configuration:                 Regression Testing.  (line  21)
3757
* DejaGNU tests directories:             Regression Testing.  (line  50)
3758
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
3759 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
3760 240 julius
                                                              (line 138)
3761 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
3762 240 julius
                                                              (line 144)
3763 98 jeremybenn
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
3764 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
3765
                                                              (line  36)
3766
* disassemble (Interactive CLI):         Interactive Command Line.
3767
                                                              (line  41)
3768
* disc interface configuration:          Disc Interface Configuration.
3769
                                                              (line   6)
3770
* disc interface device configuration:   Disc Interface Configuration.
3771
                                                              (line  88)
3772
* display interface configuration:       Display Interface Configuration.
3773
                                                              (line   6)
3774
* displaying memory (Interactive CLI):   Interactive Command Line.
3775
                                                              (line  31)
3776
* displaying registers (Interactive CLI): Interactive Command Line.
3777
                                                              (line  14)
3778
* dm (Interactive CLI):                  Interactive Command Line.
3779
                                                              (line  31)
3780
* dma (Ethernet configuration):          Ethernet Configuration.
3781 346 jeremybenn
                                                              (line  33)
3782 19 jeremybenn
* DMA configuration:                     DMA Configuration.   (line   6)
3783
* DMA verification (VAPI):               Verification API.    (line  73)
3784
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
3785
                                                              (line  70)
3786
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3787
                                                              (line  71)
3788
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
3789
                                                              (line  69)
3790
* DME (power management register):       Power Management Configuration.
3791
                                                              (line  15)
3792
* DMMU configuration:                    Memory Management Configuration.
3793
                                                              (line   6)
3794
* doze mode (power management register): Power Management Configuration.
3795
                                                              (line  15)
3796
* dv (Interactive CLI):                  Interactive Command Line.
3797
                                                              (line 124)
3798
* dynamic clock gating (power management register): Power Management Configuration.
3799
                                                              (line  21)
3800
* dynamic model:                         Configuring the Build.
3801 104 jeremybenn
                                                              (line  37)
3802 19 jeremybenn
* dynamic ports, use of:                 Verification API Configuration.
3803
                                                              (line  23)
3804
* edge_trigger (interrupt controller):   Interrupt Configuration.
3805
                                                              (line  16)
3806 346 jeremybenn
* enable_bursts (CUC configuration):     CUC Configuration.   (line  41)
3807 19 jeremybenn
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
3808
                                                              (line  18)
3809
* enabled (branch prediction configuration): Branch Prediction Configuration.
3810
                                                              (line  15)
3811
* enabled (cache configuration):         Cache Configuration. (line  11)
3812
* enabled (debug interface configuration): Debug Interface Configuration.
3813
                                                              (line  11)
3814
* enabled (DMA configuration):           DMA Configuration.   (line  20)
3815
* enabled (Ethernet configuration):      Ethernet Configuration.
3816
                                                              (line  18)
3817
* enabled (frame buffer configuration):  Frame Buffer Configuration.
3818
                                                              (line  16)
3819
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
3820
                                                              (line  18)
3821
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
3822
* enabled (interrupt controller):        Interrupt Configuration.
3823
                                                              (line  12)
3824
* enabled (keyboard configuration):      Keyboard Configuration.
3825
                                                              (line  32)
3826
* enabled (memory controller configuration): Memory Controller Configuration.
3827 98 jeremybenn
                                                              (line  35)
3828 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
3829
                                                              (line  12)
3830
* enabled (power management configuration): Power Management Configuration.
3831
                                                              (line  35)
3832
* enabled (UART configuration):          UART Configuration.  (line  18)
3833
* enabled (verification API configuration): Verification API Configuration.
3834
                                                              (line  15)
3835
* enabled (VGA configuration):           Display Interface Configuration.
3836
                                                              (line  22)
3837
* enabling Ethernet via socket:          Configuring the Build.
3838 104 jeremybenn
                                                              (line  59)
3839 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
3840
                                                              (line  32)
3841
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
3842
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
3843
* Ethernet configuration:                Ethernet Configuration.
3844
                                                              (line   6)
3845
* Ethernet verification (VAPI):          Verification API.    (line  78)
3846
* Ethernet via socket, enabling:         Configuring the Build.
3847 104 jeremybenn
                                                              (line  59)
3848 127 jeremybenn
* exclusive-OR immediate operand:        Configuring the Build.
3849
                                                              (line  69)
3850 202 julius
* exe_bin_insn_log (simulator configuration): Simulator Behavior.
3851
                                                              (line 103)
3852
* exe_bin_insn_log_file (simulator configuration): Simulator Behavior.
3853
                                                              (line 111)
3854 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
3855
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
3856
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
3857 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
3858 82 jeremybenn
                                                              (line  97)
3859 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
3860 82 jeremybenn
                                                              (line  93)
3861 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
3862 82 jeremybenn
                                                              (line  86)
3863
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
3864 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
3865 82 jeremybenn
                                                              (line  58)
3866 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
3867 82 jeremybenn
                                                              (line  62)
3868 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
3869 82 jeremybenn
                                                              (line  69)
3870 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
3871 82 jeremybenn
                                                              (line  74)
3872 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
3873
                                                              (line  23)
3874
* execution history (Interactive CLI):   Interactive Command Line.
3875
                                                              (line  67)
3876
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
3877
                                                              (line 104)
3878
* file (keyboard configuration):         Keyboard Configuration.
3879
                                                              (line  51)
3880
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
3881 82 jeremybenn
                                                              (line  36)
3882 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
3883
                                                              (line  47)
3884
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
3885
                                                              (line 117)
3886
* flag setting by instructions:          Configuring the Build.
3887 127 jeremybenn
                                                              (line 118)
3888 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
3889
                                                              (line   6)
3890
* generic peripheral configuration:      Generic Peripheral Configuration.
3891
                                                              (line   6)
3892
* GPIO configuration:                    GPIO Configuration.  (line   6)
3893
* GPIO verification (VAPI):              Verification API.    (line  88)
3894
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
3895
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
3896
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
3897
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
3898
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
3899
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
3900
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
3901 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
3902 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
3903 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
3904
                                                              (line 121)
3905
* help (Interactive CLI):                Interactive Command Line.
3906
                                                              (line 170)
3907
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
3908
                                                              (line 133)
3909
* hide_device_id (verification API configuration): Verification API Configuration.
3910
                                                              (line  36)
3911
* hist (Interactive CLI):                Interactive Command Line.
3912
                                                              (line  67)
3913 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
3914 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
3915
                                                              (line  67)
3916
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
3917
                                                              (line  33)
3918
* hitdelay (instruction cache configuration): Cache Configuration.
3919
                                                              (line  38)
3920
* hitdelay (MMU configuration):          Memory Management Configuration.
3921
                                                              (line  51)
3922 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
3923 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3924
                                                              (line  49)
3925
* IMMU configuration:                    Memory Management Configuration.
3926
                                                              (line   6)
3927
* index (memory controller configuration): Memory Controller Configuration.
3928 98 jeremybenn
                                                              (line  68)
3929 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
3930
                                                              (line 119)
3931
* installing Or1ksim:                    Installation.        (line   6)
3932
* instruction cache configuration:       Cache Configuration. (line   6)
3933
* instruction MMU configuration:         Memory Management Configuration.
3934
                                                              (line   6)
3935
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
3936
* instruction profiling utility (Interactive CLI): Interactive Command Line.
3937
                                                              (line 178)
3938
* internal debugging:                    Internal Debugging.  (line   6)
3939
* interrupt controller configuration:    Interrupt Configuration.
3940
                                                              (line   6)
3941
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
3942
                                                              (line  32)
3943
* irq (DMA configuration):               DMA Configuration.   (line  34)
3944
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
3945
* irq (keyboard configuration):          Keyboard Configuration.
3946
                                                              (line  47)
3947
* irq (UART configuration):              UART Configuration.  (line  70)
3948
* irq (VGA configuration):               Display Interface Configuration.
3949
                                                              (line  37)
3950
* jitter (UART configuration):           UART Configuration.  (line  78)
3951
* keyboard configuration:                Keyboard Configuration.
3952
                                                              (line   6)
3953
* library version of Or1ksim:            Simulator Library.   (line   6)
3954
* license for Or1ksim:                   GNU Free Documentation License.
3955
                                                              (line   6)
3956
* list breakpoints (Interactive CLI):    Interactive Command Line.
3957
                                                              (line  60)
3958
* load_hitdelay (data cache configuration): Cache Configuration.
3959
                                                              (line  46)
3960
* load_missdelay (data cache configuration): Cache Configuration.
3961
                                                              (line  50)
3962
* log (memory configuration):            Memory Configuration.
3963 240 julius
                                                              (line 150)
3964 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
3965
                                                              (line  28)
3966 346 jeremybenn
* long:                                  Simulator Library.   (line  95)
3967 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
3968 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
3969 240 julius
                                                              (line 127)
3970 19 jeremybenn
* memory configuration:                  Memory Configuration.
3971
                                                              (line   6)
3972
* memory controller configuration:       Memory Controller Configuration.
3973
                                                              (line   6)
3974
* memory copying (Interactive CLI):      Interactive Command Line.
3975
                                                              (line  54)
3976
* memory display (Interactive CLI):      Interactive Command Line.
3977
                                                              (line  31)
3978
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
3979
                                                              (line 133)
3980
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
3981
                                                              (line 124)
3982
* memory patching (Interactive CLI):     Interactive Command Line.
3983
                                                              (line  48)
3984
* memory profiling end address:          Memory Profiling Utility.
3985
                                                              (line  56)
3986
* memory profiling start address:        Memory Profiling Utility.
3987
                                                              (line  56)
3988
* memory profiling utility (Interactive CLI): Interactive Command Line.
3989
                                                              (line 173)
3990
* memory profiling version of Or1ksim:   Memory Profiling Utility.
3991
                                                              (line   6)
3992
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
3993 346 jeremybenn
* memory_order=exact (CUC configuration): CUC Configuration.  (line  30)
3994 19 jeremybenn
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
3995 346 jeremybenn
* memory_order=strong (CUC configuration): CUC Configuration. (line  27)
3996
* memory_order=weak (CUC configuration): CUC Configuration.   (line  22)
3997 19 jeremybenn
* missdelay (branch prediction configuration): Branch Prediction Configuration.
3998
                                                              (line  37)
3999
* missdelay (instruction cache configuration): Cache Configuration.
4000
                                                              (line  42)
4001
* missdelay (MMU configuration):         Memory Management Configuration.
4002
                                                              (line  55)
4003
* MMU configuration:                     Memory Management Configuration.
4004
                                                              (line   6)
4005 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
4006 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
4007 82 jeremybenn
                                                              (line  34)
4008 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
4009 346 jeremybenn
                                                              (line 173)
4010 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
4011 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
4012
                                                              (line 128)
4013
* name (generic peripheral configuration): Generic Peripheral Configuration.
4014
                                                              (line  42)
4015
* name (memory configuration):           Memory Configuration.
4016 240 julius
                                                              (line 109)
4017 346 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  45)
4018 19 jeremybenn
* nsets (cache configuration):           Cache Configuration. (line  15)
4019
* nsets (MMU configuration):             Memory Management Configuration.
4020
                                                              (line  16)
4021
* nways (cache configuration):           Cache Configuration. (line  22)
4022
* nways (MMU configuration):             Memory Management Configuration.
4023
                                                              (line  22)
4024 346 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  85)
4025
* or1ksim_init:                          Simulator Library.   (line  15)
4026
* or1ksim_interrupt:                     Simulator Library.   (line 100)
4027
* or1ksim_interrupt_clear:               Simulator Library.   (line 118)
4028
* or1ksim_interrupt_set:                 Simulator Library.   (line 109)
4029
* or1ksim_is_le:                         Simulator Library.   (line  90)
4030
* or1ksim_jtag_reset:                    Simulator Library.   (line 127)
4031
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 149)
4032
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 135)
4033
* or1ksim_read_mem:                      Simulator Library.   (line 163)
4034
* or1ksim_read_reg:                      Simulator Library.   (line 199)
4035
* or1ksim_read_spr:                      Simulator Library.   (line 181)
4036
* or1ksim_reset_duration:                Simulator Library.   (line  70)
4037
* or1ksim_run:                           Simulator Library.   (line  59)
4038
* or1ksim_set_stall_state:               Simulator Library.   (line 217)
4039
* or1ksim_set_time_point:                Simulator Library.   (line  81)
4040
* or1ksim_write_mem:                     Simulator Library.   (line 172)
4041
* or1ksim_write_reg:                     Simulator Library.   (line 208)
4042
* or1ksim_write_spr:                     Simulator Library.   (line 190)
4043 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
4044
* overflow flag setting by instructions: Configuring the Build.
4045 127 jeremybenn
                                                              (line 133)
4046 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
4047
                                                              (line 113)
4048
* pagesize (MMU configuration):          Memory Management Configuration.
4049
                                                              (line  27)
4050
* patching memory (Interactive CLI):     Interactive Command Line.
4051
                                                              (line  48)
4052
* patching registers (Interactive CLI):  Interactive Command Line.
4053
                                                              (line  28)
4054
* patching the program counter (Interactive CLI): Interactive Command Line.
4055
                                                              (line  51)
4056
* pattern (memory configuration):        Memory Configuration.
4057 240 julius
                                                              (line  76)
4058 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
4059
                                                              (line  51)
4060
* PIC configuration:                     Interrupt Configuration.
4061
                                                              (line   6)
4062
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
4063
                                                              (line 132)
4064
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
4065
                                                              (line  51)
4066
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
4067
                                                              (line  52)
4068
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
4069
                                                              (line  53)
4070
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4071
                                                              (line  54)
4072
* pm (Interactive CLI):                  Interactive Command Line.
4073
                                                              (line  48)
4074
* PMR - DGCE:                            Power Management Configuration.
4075
                                                              (line  21)
4076
* PMR - DME:                             Power Management Configuration.
4077
                                                              (line  15)
4078
* PMR - SDF:                             Power Management Configuration.
4079
                                                              (line  12)
4080
* PMR - SME:                             Power Management Configuration.
4081
                                                              (line  16)
4082
* PMR - SUME:                            Power Management Configuration.
4083
                                                              (line  24)
4084
* PMU configuration:                     Power Management Configuration.
4085
                                                              (line   6)
4086
* poc (memory controller configuration): Memory Controller Configuration.
4087 98 jeremybenn
                                                              (line  55)
4088 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4089
                                                              (line  23)
4090
* power management configuration:        Power Management Configuration.
4091
                                                              (line   6)
4092
* power management register, DGCE:       Power Management Configuration.
4093
                                                              (line  21)
4094
* power management register, DME:        Power Management Configuration.
4095
                                                              (line  15)
4096
* power management register, SDF:        Power Management Configuration.
4097
                                                              (line  12)
4098
* power management register, SME:        Power Management Configuration.
4099
                                                              (line  16)
4100
* power management register, SUME:       Power Management Configuration.
4101
                                                              (line  24)
4102
* pr (Interactive CLI):                  Interactive Command Line.
4103
                                                              (line  28)
4104
* private ports, use of:                 Verification API Configuration.
4105
                                                              (line  23)
4106
* processor configuration:               CPU Configuration.   (line   6)
4107
* processor stall (Interactive CLI):     Interactive Command Line.
4108
                                                              (line  72)
4109
* processor unstall (Interactive CLI):   Interactive Command Line.
4110
                                                              (line  78)
4111
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4112
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4113
                                                              (line  23)
4114
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4115
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4116
* profiling utility (Interactive CLI):   Interactive Command Line.
4117
                                                              (line 178)
4118
* program counter patching (Interactive CLI): Interactive Command Line.
4119
                                                              (line  51)
4120
* programmable interrupt controller configuration: Interrupt Configuration.
4121
                                                              (line   6)
4122
* PS2 configuration:                     Keyboard Configuration.
4123
                                                              (line   6)
4124
* q (Interactive CLI):                   Interactive Command Line.
4125
                                                              (line  11)
4126
* quitting (Interactive CLI):            Interactive Command Line.
4127
                                                              (line  11)
4128
* r (Interactive CLI):                   Interactive Command Line.
4129
                                                              (line  14)
4130
* random_seed (memory configuration):    Memory Configuration.
4131 240 julius
                                                              (line  66)
4132 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4133 82 jeremybenn
                                                              (line  30)
4134 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4135
                                                              (line  41)
4136
* reg_sim_reset:                         Concepts.            (line  13)
4137
* register display (Interactive CLI):    Interactive Command Line.
4138
                                                              (line  14)
4139
* register over time statistics:         Configuring the Build.
4140 127 jeremybenn
                                                              (line  92)
4141 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4142
                                                              (line  28)
4143 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4144 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4145
                                                              (line  20)
4146 235 jeremybenn
* Remote Serial Protocol, --nosrv:       Standalone Simulator.
4147 346 jeremybenn
                                                              (line  47)
4148 235 jeremybenn
* Remote Serial Protocol, --srv:         Standalone Simulator.
4149 346 jeremybenn
                                                              (line  55)
4150 19 jeremybenn
* reset (Interactive CLI):               Interactive Command Line.
4151
                                                              (line  63)
4152
* reset hooks:                           Concepts.            (line  13)
4153
* reset the simulator (Interactive CLI): Interactive Command Line.
4154
                                                              (line  63)
4155
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4156
                                                              (line  44)
4157
* rev (CPU configuration):               CPU Configuration.   (line  15)
4158
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4159
                                                              (line  20)
4160
* rsp_port (debug interface configuration): Debug Interface Configuration.
4161 235 jeremybenn
                                                              (line  32)
4162 19 jeremybenn
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4163
                                                              (line  46)
4164
* run (Interactive CLI):                 Interactive Command Line.
4165
                                                              (line  23)
4166
* running code (Interactive CLI):        Interactive Command Line.
4167
                                                              (line  23)
4168
* running Or1ksim:                       Usage.               (line   6)
4169
* runtime:                               Global Data Structures.
4170
                                                              (line  58)
4171
* runtime global structure:              Global Data Structures.
4172
                                                              (line  58)
4173
* runtime.cpu:                           Global Data Structures.
4174
                                                              (line  62)
4175
* runtime.cpu.fout:                      Concepts.            (line   7)
4176
* runtime.cuc:                           Global Data Structures.
4177
                                                              (line  62)
4178
* runtime.vapi:                          Global Data Structures.
4179
                                                              (line  62)
4180
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4181
                                                              (line  59)
4182
* rxfile (Ethernet configuration):       Ethernet Configuration.
4183
                                                              (line  68)
4184
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4185
                                                              (line  23)
4186
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4187
                                                              (line  28)
4188 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4189 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4190
                                                              (line  12)
4191
* section ata:                           Disc Interface Configuration.
4192
                                                              (line   6)
4193
* section bpb:                           Branch Prediction Configuration.
4194
                                                              (line   6)
4195
* section cpio:                          GPIO Configuration.  (line   6)
4196
* section cpu:                           CPU Configuration.   (line   6)
4197
* section cuc:                           CUC Configuration.   (line   6)
4198
* section dc:                            Cache Configuration. (line   6)
4199
* section debug:                         Debug Interface Configuration.
4200
                                                              (line   6)
4201
* section dma:                           DMA Configuration.   (line   6)
4202
* section dmmu:                          Memory Management Configuration.
4203
                                                              (line   6)
4204
* section ethernet:                      Ethernet Configuration.
4205
                                                              (line   6)
4206
* section fb:                            Frame Buffer Configuration.
4207
                                                              (line   6)
4208
* section generic:                       Generic Peripheral Configuration.
4209
                                                              (line   6)
4210
* section ic:                            Cache Configuration. (line   6)
4211
* section immu:                          Memory Management Configuration.
4212
                                                              (line   6)
4213
* section kb:                            Keyboard Configuration.
4214
                                                              (line   6)
4215
* section mc:                            Memory Controller Configuration.
4216
                                                              (line   6)
4217
* section memory:                        Memory Configuration.
4218
                                                              (line   6)
4219
* section pic:                           Interrupt Configuration.
4220
                                                              (line   6)
4221
* section pmu:                           Power Management Configuration.
4222
                                                              (line   6)
4223
* section sim:                           Simulator Behavior.  (line   6)
4224
* section uart:                          UART Configuration.  (line   6)
4225
* section vapi:                          Verification API Configuration.
4226
                                                              (line   6)
4227
* section vga:                           Display Interface Configuration.
4228
                                                              (line   6)
4229
* sections:                              Global Data Structures.
4230
                                                              (line  49)
4231
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4232
                                                              (line 125)
4233
* server_port (verification API configuration): Verification API Configuration.
4234
                                                              (line  19)
4235
* set (Interactive CLI):                 Interactive Command Line.
4236
                                                              (line 146)
4237
* set breakpoint (Interactive CLI):      Interactive Command Line.
4238
                                                              (line  57)
4239
* setdbch (Interactive CLI):             Interactive Command Line.
4240
                                                              (line 141)
4241
* simple model:                          Configuring the Build.
4242 104 jeremybenn
                                                              (line  37)
4243 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4244
* simulator configuration info (Interactive CLI): Interactive Command Line.
4245
                                                              (line 119)
4246
* simulator reset (Interactive CLI):     Interactive Command Line.
4247
                                                              (line  63)
4248
* simulator statistics (Interactive CLI): Interactive Command Line.
4249
                                                              (line  83)
4250
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4251
                                                              (line 109)
4252
* size (generic peripheral configuration): Generic Peripheral Configuration.
4253
                                                              (line  30)
4254
* size (memory configuration):           Memory Configuration.
4255 240 julius
                                                              (line  93)
4256 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4257
                                                              (line  16)
4258
* slow down factor (power management register): Power Management Configuration.
4259
                                                              (line  12)
4260
* SME (power management register):       Power Management Configuration.
4261
                                                              (line  16)
4262
* sockif (Ethernet configuration):       Ethernet Configuration.
4263
                                                              (line  83)
4264
* sr (CPU configuration):                CPU Configuration.   (line  53)
4265
* stall (Interactive CLI):               Interactive Command Line.
4266
                                                              (line  72)
4267
* stall the processor (Interactive CLI): Interactive Command Line.
4268
                                                              (line  72)
4269
* statistics, register over time:        Configuring the Build.
4270 127 jeremybenn
                                                              (line  92)
4271 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4272
                                                              (line  83)
4273
* stats (Interactive CLI):               Interactive Command Line.
4274
                                                              (line  83)
4275
* stepping code (Interactive CLI):       Interactive Command Line.
4276
                                                              (line  19)
4277
* store_hitdelay (data cache configuration): Cache Configuration.
4278
                                                              (line  54)
4279
* store_missdelay (data cache configuration): Cache Configuration.
4280
                                                              (line  58)
4281
* SUME (power management register):      Power Management Configuration.
4282
                                                              (line  24)
4283 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4284 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4285
                                                              (line  24)
4286
* t (Interactive CLI):                   Interactive Command Line.
4287
                                                              (line  19)
4288 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4289 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4290
                                                              (line  23)
4291
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4292 235 jeremybenn
                                                              (line  37)
4293 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4294
* test code for target:                  Regression Testing.  (line  63)
4295
* test make file:                        Regression Testing.  (line  27)
4296
* test README:                           Regression Testing.  (line  32)
4297
* testing:                               Regression Testing.  (line   6)
4298 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4299 127 jeremybenn
                                                              (line 105)
4300 346 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  49)
4301 19 jeremybenn
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4302 346 jeremybenn
                                                              (line  49)
4303 19 jeremybenn
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4304
                                                              (line  57)
4305
* toggle debug channels (Interactive CLI): Interactive Command Line.
4306
                                                              (line 141)
4307
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4308
                                                              (line 151)
4309
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4310
                                                              (line  60)
4311
* txfile (Ethernet configuration):       Ethernet Configuration.
4312
                                                              (line  69)
4313
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4314 82 jeremybenn
                                                              (line  36)
4315 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4316
                                                              (line  47)
4317
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4318
                                                              (line  99)
4319
* type (memory configuration):           Memory Configuration.
4320 98 jeremybenn
                                                              (line  36)
4321 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4322 98 jeremybenn
                                                              (line  46)
4323 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4324 98 jeremybenn
                                                              (line  40)
4325 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4326 98 jeremybenn
                                                              (line  50)
4327 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4328 240 julius
                                                              (line  55)
4329 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4330
* UART I/O from/to a physical serial port: UART Configuration.
4331
                                                              (line  62)
4332
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4333
* UART I/O from/to files:                UART Configuration.  (line  33)
4334
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4335
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4336
* UART verification (VAPI):              Verification API.    (line  41)
4337
* unstall (Interactive CLI):             Interactive Command Line.
4338
                                                              (line  78)
4339
* unstall the processor (Interactive CLI): Interactive Command Line.
4340
                                                              (line  78)
4341
* upr (CPU configuration):               CPU Configuration.   (line  21)
4342
* ustates (cache configuration):         Cache Configuration. (line  33)
4343
* ustates (MMU configuration):           Memory Management Configuration.
4344
                                                              (line  41)
4345
* VAPI configuration:                    Verification API Configuration.
4346
                                                              (line   6)
4347
* VAPI for Debug Unit:                   Verification API.    (line  34)
4348
* VAPI for DMA:                          Verification API.    (line  73)
4349
* VAPI for Ethernet:                     Verification API.    (line  78)
4350
* VAPI for GPIO:                         Verification API.    (line  88)
4351
* VAPI for UART:                         Verification API.    (line  41)
4352
* vapi_id (debug interface configuration): Debug Interface Configuration.
4353 235 jeremybenn
                                                              (line  43)
4354 346 jeremybenn
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4355 19 jeremybenn
                                                              (line  88)
4356 346 jeremybenn
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4357 19 jeremybenn
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4358
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4359
* vapi_log_file (verification API configuration): Verification API Configuration.
4360
                                                              (line  41)
4361
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4362
                                                              (line  41)
4363
* ver (CPU configuration):               CPU Configuration.   (line  15)
4364
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4365
* Verification API configuration:        Verification API Configuration.
4366
                                                              (line   6)
4367
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4368
                                                              (line 124)
4369
* VGA configuration:                     Display Interface Configuration.
4370
 
4371
 
4372
                                                              (line  50)
4373
4374
4375

4376
Tag Table:
4377 346 jeremybenn
Node: Top814
4378
Node: Installation1224
4379
Node: Preparation1471
4380
Node: Configuring the Build1764
4381
Node: Build and Install7880
4382
Node: Known Issues8658
4383
Node: Usage9713
4384
Node: Standalone Simulator9927
4385
Node: Profiling Utility14342
4386
Node: Memory Profiling Utility15252
4387
Node: Simulator Library16617
4388
Node: Configuration26694
4389
Node: Configuration File Format27306
4390
Node: Configuration File Preprocessing27691
4391
Node: Configuration File Syntax27988
4392
Node: Simulator Configuration30773
4393
Node: Simulator Behavior31064
4394
Node: Verification API Configuration35645
4395
Node: CUC Configuration37585
4396
Node: Core OpenRISC Configuration39577
4397
Node: CPU Configuration40079
4398
Node: Memory Configuration44198
4399
Node: Memory Management Configuration50689
4400
Node: Cache Configuration53066
4401
Node: Interrupt Configuration55452
4402
Node: Power Management Configuration56188
4403
Node: Branch Prediction Configuration57465
4404
Node: Debug Interface Configuration58825
4405
Node: Peripheral Configuration61168
4406
Node: Memory Controller Configuration61794
4407
Node: UART Configuration65209
4408
Node: DMA Configuration68728
4409
Node: Ethernet Configuration70595
4410
Node: GPIO Configuration74571
4411
Node: Display Interface Configuration76204
4412
Node: Frame Buffer Configuration78513
4413
Node: Keyboard Configuration80377
4414
Node: Disc Interface Configuration82615
4415
Node: Generic Peripheral Configuration87558
4416
Node: Interactive Command Line89853
4417
Node: Verification API96827
4418
Node: Code Internals101257
4419
Node: Coding Conventions101840
4420
Node: Global Data Structures106267
4421
Node: Concepts108924
4422
Ref: Output Redirection109069
4423
Node: Internal Debugging109608
4424
Node: Regression Testing110132
4425
Node: GNU Free Documentation License113921

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