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This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
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../../doc/or1ksim.texi.
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4
INFO-DIR-SECTION Embedded development
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START-INFO-DIR-ENTRY
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* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
7
                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 420 jeremybenn
     tar jxf or1ksim-2010-11-11.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
82 19 jeremybenn
default to OpenRISC 1000 32-bit with a warning
83
 
84 420 jeremybenn
     ../or1ksim-2010-11-11/configure --target=or32-uclinux ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 385 jeremybenn
For testing (using `make check'), the `--target' parameter may be
92
specified, to allow the target tool chain to be selected.  If not
93
specified, it will default to `or32-elf', which is the same prefix used
94
with the standard OpenRISC toolchain installation script.
95 19 jeremybenn
 
96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
101 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
`--enable-execution=dynamic'
108
     Or1ksim has developed to improve functionality and performance.
109
     This feature allows three versions of Or1ksim to be built
110
 
111
    `--enable-execution=simple'
112
          Build the original simple interpreting simulator
113
 
114
    `--enable-execution=complex'
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          Build a more complex interpreting simulator.  Experiments
116
          suggest this is 50% faster than the simple simulator.  This
117
          is the default.
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119
    `--enable-execution=dynamic'
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          Build a dynamically compiling simulator.  This is the way
121
          many modern ISS are built.  This represents a work in
122
          progress.  Currently Or1ksim will compile, but segfaults if
123
          configured with this option.
124 19 jeremybenn
 
125
 
126
     The default is `--enable-execution=complex'.
127
 
128
`--enable-ethphy'
129
`--disable-ethphy'
130
     If enabled, this option allows the Ethernet to be simulated by
131
     connecting via a socket (the alternative reads and writes, from
132 82 jeremybenn
     and to files).  This must then be configured using the relevant
133
     fields in the `ethernet' section of the configuration file.  *Note
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     Ethernet Configuration: Ethernet Configuration.
135
 
136
     The default is for this to be disabled.
137
 
138 127 jeremybenn
`--enable-unsigned-xori'
139
`--disable-unsigned-xori'
140 346 jeremybenn
     Historically, `l.xori', has sign extended its operand.  This is
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     inconsistent with the other logical opcodes (`l.andi', `l.ori'),
142
     but in the absence of `l.not', it allows a register to be inverted
143
     in a single instruction using:
144
 
145
          `l.xori  rD,rA,-1'
146
 
147
     This flag causes Or1ksim to treat the immediate operand as
148
     unsigned (i.e to zero-extend rather than sign-extend).
149
 
150
     The default is to sign-extend, so that existing code will continue
151
     to work.
152
 
153
          Caution: The GNU compiler tool chain makes heavy use of this
154
          instruction.  Using unsigned behavior will require the
155
          compiler to be modified accordingly.
156
 
157
          This option is provided for experimentation.  A future
158
          version of OpenRISC may adopt this more consistent behavior
159
          and also provide a `l.not' opcode.
160
 
161 19 jeremybenn
`--enable-range-stats'
162
`--disable-range-stats'
163
     If enabled, this option allows statistics to be collected to
164 82 jeremybenn
     analyse register access over time.  The default is for this to be
165 19 jeremybenn
     disabled.
166
 
167
`--enable-debug'
168
`--disable-debug'
169
     This is a feature of the Argtable2 package used to process
170 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
171
     Argtable2.  It is provided for completeness, but there is no
172
     reason why this feature should ever be needed by any Or1ksim user.
173 19 jeremybenn
 
174 82 jeremybenn
`--enable-all-tests'
175
`--disable-all-tests'
176
     Some of the tests (at the time of writing just one) will not
177
     compile without error.  If enabled with this flag, all test
178
     programs will be compiled with `make check'.
179 19 jeremybenn
 
180 82 jeremybenn
     This flag is intended for those working on the test package, who
181
     wish to get the missing test(s) working.
182
 
183
 
184 112 jeremybenn
A number of configuration flags have been removed since version 0.3.0,
185 346 jeremybenn
because they led to invalid behavior of Or1ksim.  Those removed are:
186 112 jeremybenn
 
187 124 jeremybenn
`--enable-arith-flag'
188
`--disable-arith-flag'
189
     If enabled, this option caused certain instructions to set the flag
190
     (`F' bit) in the supervision register if the result were zero.
191
     The instructions affected by this were `l.add', `l.addc',
192
     `l.addi', `l.and' and `l.andi'.
193
 
194 346 jeremybenn
     If set, this caused incorrect behavior.  Whether or not flags are
195 124 jeremybenn
     set is part of the OpenRISC 1000 architectural specification.  The
196
     only flags which should set this are the "set flag" instructions:
197
     `l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
198
     `l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
199
     `l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
200
     `l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
201
 
202 112 jeremybenn
`--enable-ov-flag'
203
`--disable-ov-flag'
204 124 jeremybenn
     This flag caused certain instructions to set the overflow flag.
205
     If not, those instructions would not set the overflow flat.  The
206
     instructions affected by this were `l.add', `l.addc', `l.addi',
207
     `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
208
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
209
     `l.sub', `l.xor' and `l.xori'.
210 112 jeremybenn
 
211
     This guaranteed incorrect behavior.  The OpenRISC 1000 architecture
212
     specification defines which flags are set by which instructions.
213
 
214
     Within the above list, the arithmetic instructions (`l.add',
215
     `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
216
     `l.sub'), together with `l.addic' which is missed out, set the
217
     overflow flag.  All the others (`l.and', `l.andi', `l.or',
218
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
219
     `l.xor' and `l.xori') do not.
220
 
221
 
222 19 jeremybenn

223
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
224
 
225
1.3 Building and Installing
226
===========================
227
 
228 82 jeremybenn
Build the tool with:
229 19 jeremybenn
 
230
     make all
231 82 jeremybenn
 
232
If you have the OpenRISC tool chain and DejaGNU installed, you can
233
verify the tool as follows (otherwise omit this step):
234
 
235
     make check
236
 
237
Install the tool with:
238
 
239 19 jeremybenn
     make install
240
 
241
This will install the three variations of the Or1ksim tool,
242
`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the
243
Or1ksim library, `libsim', the header file, `or1ksim.h' and this
244
documentation in `info' format.
245
 
246
The documentation may be created and installed in alternative formats
247
(PDF, Postscript, DVI, HTML) with for example:
248
 
249
     make pdf
250
     make install-pdf
251
 
252

253
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
254
 
255
1.4 Known Problems and Issues
256
=============================
257
 
258 346 jeremybenn
Full details of outstanding issues may be found in the `NEWS' file in
259
the main directory of the distribution.  The OpenRISC tracker may be
260
used to see the current state of these issues and to raise new problems
261
and feature requests.  It may be found at bugtracker.
262 19 jeremybenn
 
263 346 jeremybenn
The following issues are long standing and unlikely to be fixed in
264
Or1ksim in the near future.
265
 
266 19 jeremybenn
   * The Supervision Register Little Endian Enable (LEE) bit is
267 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
268 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
269
 
270
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
271 82 jeremybenn
     instances using the library.  This is clearly a problem when
272
     considering multi-core applications.  However it stems from the
273
     original design, and can only be fixed by a complete rewrite.  The
274 19 jeremybenn
     entire source code uses static global constants liberally!
275
 
276
 
277

278
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
279
 
280
2 Usage
281
*******
282
 
283
* Menu:
284
 
285
* Standalone Simulator::
286
* Profiling Utility::
287
* Memory Profiling Utility::
288
* Simulator Library::
289
 
290

291
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
292
 
293
2.1 Standalone Simulator
294
========================
295
 
296
The general form the standalone command is:
297
 
298 385 jeremybenn
     or32-uclinux-sim [-vhiqVt] [-f FILE] [--nosrv] [--srv=[N]]
299 346 jeremybenn
                      [-m ][-d STR]
300 19 jeremybenn
                      [--enable-profile] [--enable-mprofile] [FILE]
301
 
302 82 jeremybenn
Many of the options have both a short and a long form.  For example
303
`-h' or `--help'.
304 19 jeremybenn
 
305
`-v'
306
`--version'
307
     Print out the version and copyright notice for Or1ksim and exit.
308
 
309
`-h'
310
`--help'
311
     Print out help about the command line options and what they mean.
312
 
313 346 jeremybenn
`-i'
314
`--interactive'
315
     After starting, drop into the Or1ksim interactive command shell.
316
 
317
`-q'
318
`--quiet'
319
     Do not generate any information messages, only error messages.
320
 
321
`-V'
322
`--verbose'
323
     Generate extra output messages (equivalent of specifying the
324
     "verbose" option in the simulator configuration section (see *note
325
     Simulator Behavior: Simulator Behavior.).
326
 
327 385 jeremybenn
`-t'
328
`--trace'
329 420 jeremybenn
     Dump instruction just executed and any register/memory location
330
     chaged after each instruction (one line per instruction).
331 385 jeremybenn
 
332 19 jeremybenn
`-f FILE'
333 385 jeremybenn
`--file=FILE'
334 19 jeremybenn
     Read configuration commands from the specified file, looking first
335
     in the current directory, and otherwise in the `$HOME/.or1k'
336 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
337
     in those two locations is used.  Failure to find the file is a
338
     fatal error.  *Note Configuration: Configuration, for detailed
339
     information on configuring Or1ksim.
340 19 jeremybenn
 
341
`--nosrv'
342 235 jeremybenn
     Do not start up the "Remote Serial Protocol" debug server.  This
343
     overrides any setting specified in the configuration file.  This
344
     option may not be specified with `--srv'.  If it is, a rude
345
     message is printed and the `--nosrv' option is ignored.
346 19 jeremybenn
 
347
`--srv'
348
 
349
`--srv=N'
350 235 jeremybenn
     Start up the "Remote Serial Protocol" debug server.  This
351
     overrides any setting specified in the configuration file.  If the
352
     parameter, N, is specified, use that as the TCP/IP port for the
353
     server, otherwise a random value from the private port range
354
     (41920-65535) will be used.  This option may not be specified with
355
     `--nosrv'.  If it is, a rude message is printed and the `--nosrv'
356
     option is ignored.
357 19 jeremybenn
 
358 385 jeremybenn
`-m SIZE'
359 346 jeremybenn
`--memory=SIZE'
360
     Configure a memory block of SIZE bytes, starting at address zero.
361
     The size may be followed by `k', `K', `m', `M', `g', `G', to
362
     indicate kilobytes (2^10 bytes), megabytes (2^20 bytes) and
363
     gigabytes (2^30 bytes).
364
 
365
     This is mainly intended for use when Or1ksim is used without a
366
     configuration file, to allow just the processor and memory to be
367
     set up.  This is the equivalent of specifying a configuration
368
     memory section with `baseaddr = 0' and `size = SIZE' and all other
369
     parameters taking their default value.
370
 
371
     If a configuration file is also used, it should be sure not to
372
     specify an overlapping memory block.
373
 
374 385 jeremybenn
`-d CONFIG_STRING'
375 19 jeremybenn
`--debug-config=CONFIG_STRING'
376 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
377
     use by developers only, and is not covered further here.  See the
378 19 jeremybenn
     source code for more details.
379
 
380 346 jeremybenn
`--report-memory-errors'
381
     By default all exceptions are now handled silently.  If this
382
     option is specified, bus exceptions will be reported with a
383
     message to standard error indicating the address at which the
384
     exception occurred.
385 19 jeremybenn
 
386 346 jeremybenn
     This was the default behaviour up to Or1ksim 0.4.0.  This flag is
387
     provided for those who wish to keep that behavior.
388
 
389 19 jeremybenn
`--strict-npc'
390
     In real hardware, setting the next program counter (NPC, SPR 16),
391 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
392
     until the pipeline refills, reading the NPC will return zero.
393
     This is typically the case when debugging, since the processor is
394 19 jeremybenn
     stalled.
395
 
396
     Historically, Or1ksim has always returned the value of the NPC,
397 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
398
     is used, then Or1ksim will mirror real hardware more accurately.
399
     If the NPC is changed while the processor is stalled, subsequent
400 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
401
 
402
     This is not currently the default behavior, since tools such as
403
     GDB have been implemented assuming the historic Or1ksim behavior.
404
     However at some time in the future it will become the default.
405
 
406
`--enable-profile'
407
     Enable instruction profiling.
408
 
409
`--enable-mprofile'
410
     Enable memory profiling.
411
 
412
 
413

414
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
415
 
416
2.2 Profiling Utility
417
=====================
418
 
419 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
420
It may be invoked as a standalone command, or from the Or1ksim CLI.
421
The general form the standalone command is:
422 19 jeremybenn
 
423
     or32-uclinux-profile [-vhcq] [-g=FILE]
424
 
425 82 jeremybenn
Many of the options have both a short and a long form.  For example
426
`-h' or `--help'.
427 19 jeremybenn
 
428
`-v'
429
`--version'
430
     Print out the version and copyright notice for the Or1ksim
431
     profiling utility and exit.
432
 
433
`-h'
434
`--help'
435
     Print out help about the command line options and what they mean.
436
 
437
`-c'
438
`--cumulative'
439
     Show cumulative sum of cycles in functions
440
 
441
`-q'
442
`--quiet'
443
     Suppress messages
444
 
445
`-g=FILE'
446
`--generate=FILE'
447 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
448 19 jeremybenn
     `sim.profile' is used.
449
 
450
 
451

452
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Simulator Library,  Prev: Profiling Utility,  Up: Usage
453
 
454
2.3 Memory Profiling Utility
455
============================
456
 
457 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
458
be invoked as a standalone command, or from the Or1ksim CLI.  The
459 19 jeremybenn
general form the standalone command is:
460
 
461
     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
462
 
463 82 jeremybenn
Many of the options have both a short and a long form.  For example
464
`-h' or `--help'.
465 19 jeremybenn
 
466
`-v'
467
`--version'
468
     Print out the version and copyright notice for the Or1ksim memory
469
     profiling utility and exit.
470
 
471
`-h'
472
`--help'
473
     Print out help about the command line options and what they mean.
474
 
475
`-m=M'
476
`--mode=M'
477 82 jeremybenn
     Specify the mode out output.  Permitted options are
478 19 jeremybenn
 
479
    `detailed'
480
    `d'
481 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
482 19 jeremybenn
 
483
    `pretty'
484
    `p'
485
          Pretty printed output.
486
 
487
    `access'
488
    `a'
489
          Memory accesses only.
490
 
491
    `width'
492
    `w'
493
          Access width only.
494
 
495
 
496
`-g=N'
497
`--group=N'
498
     Group 2^n bits of successive addresses together.
499
 
500
`-f=FILE'
501
`--filename=FILE'
502 82 jeremybenn
     The data file to analyse.  If not specified, the default,
503 19 jeremybenn
     `sim.profile' is used.
504
 
505
`FROM'
506
`TO'
507
     FROM and TO are respectively the start and end address of the
508
     region of memory to be analysed.
509
 
510
 
511

512
File: or1ksim.info,  Node: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
513
 
514
2.4 Simulator Library
515
=====================
516
 
517
Or1ksim may be used as a static of dynamic library, `libsim.a' or
518 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
519 19 jeremybenn
should be added to the link command.
520
 
521
The header file `or1ksim.h' contains appropriate declarations of the
522 82 jeremybenn
functions exported by the Or1ksim library.  These are:
523 19 jeremybenn
 
524 346 jeremybenn
 -- `or1ksim.h': int or1ksim_init (int ARGC, char *ARGV, void
525
          *CLASS_PTR,
526
     int (*UPR)(void *CLASS_PTR, unsigned long int ADDR, unsigned char
527 93 jeremybenn
     MASK[], unsigned char RDATA[], int DATA_LEN), int (*UPW)(void
528
     *CLASS_PTR, unsigned long int ADDR, unsigned char MASK[], unsigned
529
     char WDATA[], int DATA_LEN))
530
 
531 346 jeremybenn
     The initialization function is supplied with a vector of arguments,
532
     which are interpreted as arguments to the standalone version (see
533
     *note Standalone Simulator: Standalone Simulator.), a pointer to
534
     the calling class, CLASS_PTR (since the library may be used from
535
     C++) and two up-call functions, one for reads, UPR, and one for
536
     writes, UPW.
537 19 jeremybenn
 
538
     UPW is called for any write to an address external to the model
539 82 jeremybenn
     (determined by a `generic' section in the configuration file).
540
     UPR is called for any reads to an external address.  The CLASS_PTR
541
     is passed back with these upcalls, allowing the function to
542
     associate the call with the class which originally initialized the
543 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
544
     non-zero otherwise.  At the present time the meaning of non-zero
545
     values is not defined but this may change in the future.
546 19 jeremybenn
 
547 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
548 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
549 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
550
     address, since the upcall function must handle all generic
551
     devices, using the full address for decoding.
552 19 jeremybenn
 
553 346 jeremybenn
     Endianness is not a concern, since Or1ksim is transferring byte
554
     vectors, not multi-byte values.
555 19 jeremybenn
 
556 346 jeremybenn
     The result indicates whether the initialization was successful.
557
     The integer values are available as an `enum or1ksim', with
558
     possible values `OR1KSIM_RC_OK' and `OR1KSIM_RC_BADINIT'.
559 19 jeremybenn
 
560 346 jeremybenn
          Caution: This is a change from versions 0.3.0 and 0.4.0.  It
561
          further simplifies the interface, and makes Or1ksim more
562
          consistent with payload representation in SystemC TLM 2.0.
563
 
564 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
565
          single words (4 bytes), using masks if smaller values are
566
          required.  In this it mimcs the behavior of the WishBone bus.
567
 
568
 
569 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
570
     Run the simulator for the simulated duration specified (in
571 346 jeremybenn
     seconds).  A duration of -1 indicates `run forever'
572 19 jeremybenn
 
573 346 jeremybenn
     The result indicates how the run terminated.  The integer values
574
     are available as an `enum or1ksim', with possible values
575
     `OR1KSIM_RC_OK' (ran for the full duration), `OR1KSIM_RC_BRKPT'
576
     (terminated early due to hitting a breakpoint) and
577
     `OR1KSIM_RC_HALTED' (terminated early due to hitting `l.nop 1').
578 19 jeremybenn
 
579 346 jeremybenn
 
580 19 jeremybenn
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
581
     Change the duration of a run specified in an earlier call to
582 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
583 19 jeremybenn
     realizes it needs to change the duration of the run specified in
584
     the call to `or1ksim_run' that has been interrupted by the upcall.
585
 
586
     The time specified is the amount of time that the run must continue
587
     for (i.e the duration from _now_, not the duration from the
588
     original call to `or1ksim_run').
589
 
590
 
591
 -- `or1ksim.h': void or1ksim_set_time_point ()
592 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
593 19 jeremybenn
 
594
 
595
 -- `or1ksim.h': double or1ksim_get_time_period ()
596
     Return the simulated time (in seconds) that has elapsed since the
597
     last call to `or1ksim_set_time_point'.
598
 
599
 
600
 -- `or1ksim.h': int or1ksim_is_le ()
601
     Return 1 (logical true) if the Or1ksim simulation is
602
     little-endian, 0 otherwise.
603
 
604
 
605
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
606 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
607
     specified in the configuration file.
608 19 jeremybenn
 
609
 
610
 -- `or1ksim.h': void or1ksim_interrupt (int I)
611 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
612
     interrupt is then immediately cleared automatically.  A warning
613 19 jeremybenn
     will be generated and the interrupt request ignored if level
614
     sensitive interrupts have been configured with the programmable
615
     interrupt controller (*note Interrupt Configuration: Interrupt
616
     Configuration.).
617
 
618
 
619
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
620 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
621 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
622 82 jeremybenn
     `or1ksim_interrupt_clear'.  A warning will be generated, and the
623 19 jeremybenn
     interrupt request ignored if edge sensitive interrupts have been
624
     configured with the programmable interrupt controller (*note
625
     Interrupt Configuration: Interrupt Configuration.).
626
 
627
 
628
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
629
     Clear a level-triggered interrupt on interrupt line I, which was
630 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
631 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
632
     edge sensitive interrupts have been configured with the
633
     programmable interrupt controller (*note Interrupt Configuration:
634
     Interrupt Configuration.).
635
 
636
 
637 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
638 346 jeremybenn
     Drive a reset sequence through the JTAG interface.  Return the
639 104 jeremybenn
     (model) time taken for this action.  Remember that the JTAG has
640
     its own clock, which can be an order of magnitude slower than the
641
     main clock, so even a reset (5 JTAG cycles) could take 50
642
     processor clock cycles to complete.
643
 
644
 
645
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned
646
     char *JREG, int NUM_BITS)
647
 
648
     Shift the supplied register through the JTAG instruction register.
649 346 jeremybenn
     Return the (model) time taken for this action.  The register is
650 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
651
     least significant byte.  If the total number of bits is not an
652
     exact number of bytes, then the odd bits are found in the least
653
     significant end of the highest numbered byte.
654
 
655
     For example a 12-bit register would have bits 0-7 in byte 0 and
656
     bits 11-8 in the least significant 4 bits of byte 1.
657
 
658
 
659
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned
660
     char *JREG, int NUM_BITS)
661
 
662
     Shift the supplied register through the JTAG data register.
663 346 jeremybenn
     Return the (model) time taken for this action.  The register is
664 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
665
     least significant byte.  If the total number of bits is not an
666
     exact number of bytes, then the odd bits are found in the least
667
     significant end of the highest numbered byte.
668
 
669
     For example a 12-bit register would have bits 0-7 in byte 0 and
670
     bits 11-8 in the least significant 4 bits of byte 1.
671
 
672
 
673 346 jeremybenn
 -- `or1ksim.h': int or1ksim_read_mem (unsigned
674
     long int ADDR, unsigned char *BUF, int LEN)
675
 
676
     Read LEN bytes from ADDR, placing the result in BUF.  Return LEN
677
     on success and 0 on failure.
678
 
679
          Note: This function was added in Or1ksim 0.5.0.
680
 
681
 
682
 -- `or1ksim.h': int or1ksim_write_mem (unsigned
683 385 jeremybenn
     long int ADDR, const unsigned char *BUF, int LEN)
684 346 jeremybenn
 
685
     Write LEN bytes to ADDR, taking the data from BUF.  Return LEN on
686
     success and 0 on failure.
687
 
688
          Note: This function was added in Or1ksim 0.5.0.
689
 
690
 
691
 -- `or1ksim.h': int or1ksim_read_spr (int SPRNUM, unsigned
692
     long int *SPRVAL_PTR)
693
 
694
     Read the SPR specified by SPRNUM, placing the result in
695
     SPRVAL_PTR.  Return non-zero on success and 0 on failure.
696
 
697
          Note: This function was added in Or1ksim 0.5.0.
698
 
699
 
700
 -- `or1ksim.h': int or1ksim_write_spr (int SPRNUM, unsigned
701
     long int SPRVA)
702
 
703
     Write SPRVAL to the SPR specified by SPRNUM.  Return non-zero on
704
     success and 0 on failure.
705
 
706
          Note: This function was added in Or1ksim 0.5.0.
707
 
708
 
709
 -- `or1ksim.h': int or1ksim_read_reg (int REGNUM, unsigned
710
     long int *REGVAL_PTR)
711
 
712
     Read the general purpose register specified by REGNUM, placing the
713
     result in REGVAL_PTR.  Return non-zero on success and 0 on failure.
714
 
715
          Note: This function was added in Or1ksim 0.5.0.
716
 
717
 
718
 -- `or1ksim.h': int or1ksim_write_reg (int REGNUM, unsigned
719
     long int REGVA)
720
 
721
     Write REGVAL to the general purpose register specified by REGNUM.
722
     Return non-zero on success and 0 on failure.
723
 
724
          Note: This function was added in Or1ksim 0.5.0.
725
 
726
 
727
 -- `or1ksim.h': void or1ksim_set_stall_state (int
728
     STATE)
729
 
730
     Set the processor's state according to STATE (1 = stalled, 0 = not
731
     stalled).
732
 
733
          Note: This function was added in Or1ksim 0.5.0.
734
 
735
 
736 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
737
installation directory (as specified with the `--prefix' option to the
738
`configure' script).
739
 
740
For example if the main installation directory is `/opt/or1ksim', the
741 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
742 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
743
(`libsim.so').
744
 
745
To link against the library add the `-lsim' flag when linking and do
746
one of the following:
747
 
748
   * Add the library directory to the `LD_LIBRARY_PATH' environment
749 82 jeremybenn
     variable during execution.  For example:
750 19 jeremybenn
 
751
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
752
 
753
   * Add the library directory to the `LD_RUN_PATH' environment
754 82 jeremybenn
     variable during linking.  For example:
755 19 jeremybenn
 
756
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
757
 
758
   * Use the linker `--rpath' option and specify the library directory
759 82 jeremybenn
     when linking your program.  For example
760 19 jeremybenn
 
761 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
762 19 jeremybenn
 
763
   * Add the library directory to `/etc/ld.so.conf'
764
 
765
 
766

767
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
768
 
769
3 Configuration
770
***************
771
 
772 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
773 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
774 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
775
the default `sim.cfg' is used.  The file is looked for first in the
776 224 jeremybenn
current directory, then in the `$HOME/.or1ksim' directory of the user.
777 19 jeremybenn
 
778
* Menu:
779
 
780
* Configuration File Format::
781
* Simulator Configuration::
782
* Core OpenRISC Configuration::
783
* Peripheral Configuration::
784
 
785

786
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
787
 
788
3.1 Configuration File Format
789
=============================
790
 
791 346 jeremybenn
The configuration file is a plain text file.  A reference example,
792
`sim.cfg', is included in the top level directory of the distribution.
793 19 jeremybenn
 
794
* Menu:
795
 
796
* Configuration File Preprocessing::
797
* Configuration File Syntax::
798
 
799

800
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
801
 
802
3.1.1 Configuration File Preprocessing
803
--------------------------------------
804
 
805 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
806 19 jeremybenn
`/*' and `*/').
807
 
808

809
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
810
 
811
3.1.2 Configuration File Syntax
812
-------------------------------
813
 
814
The configuration file is divided into a series of sections, with the
815
general form:
816
 
817
     section SECTION_NAME
818
 
819
       ...
820
 
821
     end
822
 
823
Sections may also have sub-sections within them (currently only the
824
ATA/ATAPI disc interface uses this).
825
 
826
Within a section, or sub-section are a series of parameter assignments,
827
one per line, withe the general form
828
 
829
       PARAMETER = VALUE
830
 
831
Depending on the parameter, the value may be a named value (an
832
enumeration), an integer (specified in any format acceptable in C) or a
833 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
834
mean "true" or "on" and the value "0" to mean "false" or "off".  An
835 19 jeremybenn
example from a memory section shows each of these
836
 
837
     section memory
838
       type    = random
839
       pattern = 0x00
840
       name    = "FLASH"
841
       ...
842
     end
843
 
844
Many parameters are optional and take reasonable default values if not
845 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
846 19 jeremybenn
parameter in `section memory') _must_ be specified.
847
 
848
Subsections are introduced by a keyword, with a parameter value (no `='
849 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
850 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
851
 
852
     section ata
853
       ...
854
       device 0
855
         type    = 1
856
         file = "FILENAME"
857
         ...
858
       enddevice
859
       ...
860
     end
861
 
862
Some sections (for example `section sim') should appear only once.
863
Others (for example `section memory' may appear multiple times.
864
 
865
Sections may be omitted, _unless they contain parameters which are
866 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
867 19 jeremybenn
is optional (for example whether it has a UART), then that
868 82 jeremybenn
functionality will not be provided.  If the section describes a part of
869 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
870
parameters of that section will take their default values.
871
 
872
All optional parts of the functionality are always described by
873
sections including a `enabled' parameter, which can be set to 0 to
874
ensure that functionality is explicitly omitted.
875
 
876
Even if a section is disabled, all its parameters will be read and
877 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
878
the Or1ksim command line (*note Interactive Command Line: Interactive
879 19 jeremybenn
Command Line.).
880
 
881
     Tip: It generally clearer to have sections describing _all_
882
     components, with omitted functionality explicitly indicated by
883
     setting the `enabled' parameter to 0
884
 
885
The following sections describe the various configuration sections and
886
the parameters which may be set in each.
887
 
888

889
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
890
 
891
3.2 Simulator Configuration
892
===========================
893
 
894
* Menu:
895
 
896
* Simulator Behavior::
897
* Verification API Configuration::
898
* CUC Configuration::
899
 
900

901
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
902
 
903
3.2.1 Simulator Behavior
904
------------------------
905
 
906 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
907
appear only once.  The following parameters may be specified.
908 19 jeremybenn
 
909
`verbose = 0|1'
910 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
911 19 jeremybenn
 
912
`debug = 0-9'
913 82 jeremybenn
 
914
     higher the value the greater the number of messages.  Default 0.
915
     Negative values will be treated as 0 (with a warning).  Values
916
     that are too large will be treated as 9 (with a warning).
917 19 jeremybenn
 
918
`profile = 0|1'
919
     If 1 (true) generate a profiling file using the file specified in
920 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
921 19 jeremybenn
 
922
`prof_file = ``FILENAME'''
923 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
924
     Default `sim.profile'.  For backwards compatibility, the
925
     alternative name `prof_fn' is supported for this parameter, but
926 346 jeremybenn
     deprecated.  Default `sim.profile'.
927 19 jeremybenn
 
928
`mprofile = 0|1'
929
     If 1 (true) generate a memory profiling file using the file
930
     specified in the `mprof_file' parameter or otherwise
931 82 jeremybenn
     `sim.mprofile'.  Default 0.
932 19 jeremybenn
 
933 346 jeremybenn
`mprof_file = ``FILENAME'''
934 19 jeremybenn
     Specifies the file to be used with the `mprofile' parameter.
935 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
936 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
937 346 jeremybenn
     deprecated.  Default `sim.mprofile'.
938 19 jeremybenn
 
939
`history = 0|1'
940 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
941 19 jeremybenn
 
942
          Note: Setting this parameter seriously degrades performance.
943
 
944
          Note: If this execution flow tracking is enabled, then
945
          `dependstats' must be enabled in the CPU configuration
946
          section (*note CPU Configuration: CPU Configuration.).
947
 
948
`exe_log = 0|1'
949 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
950
     file specified in parameter `exe_log_file'.  Default 0.
951 19 jeremybenn
 
952
          Note: Setting this parameter seriously degrades performance.
953
 
954
`exe_log_type = default|hardware|simple|software'
955
     Type of execution log to produce.
956
 
957
    `default'
958 82 jeremybenn
          Produce default output for the execution log.  In the current
959 19 jeremybenn
          implementation this is the equivalent of `hardware'.
960
 
961
    `hardware'
962
          After each instruction execution, log the number of
963
          instructions executed so far, the next instruction to execute
964
          (in hex), the general purpose registers (GPRs), status
965
          register, exception program counter, exception, effective
966
          address register and exception status register.
967
 
968
    `simple'
969
          After each instruction execution, log the number of
970
          instructions executed so far and the next instruction to
971
          execute, symbolically disassembled.
972
 
973
    `software'
974
          After each instruction execution, log the number of
975
          instructions executed so far and the next instruction to
976 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
977 19 jeremybenn
          each operand to the instruction.
978
 
979
 
980 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
981 19 jeremybenn
     insensitive) will be treated as the default with a warning.
982
 
983
          Note: Execution logs can be _very_ big.
984
 
985
`exe_log_start = VALUE'
986 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
987 19 jeremybenn
 
988
`exe_log_end = VALUE'
989 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
990
     once started logging will continue until the simulator exits).
991 19 jeremybenn
 
992
`exe_log_marker = VALUE'
993
     Specifies the number of instructions between printing horizontal
994 82 jeremybenn
     markers.  Default is to produce no markers.
995 19 jeremybenn
 
996
`exe_log_file = FILENAME'
997
     Filename for the execution log filename if `exe_log' is enabled.
998 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
999 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
1000
     deprecated.
1001
 
1002 202 julius
`exe_bin_insn_log = 0|1'
1003 346 jeremybenn
     Enable logging of executed instructions to a file in binary format.
1004
     This is helpful for off-line dynamic execution analysis.
1005 202 julius
 
1006 346 jeremybenn
          Note: Execution logs can be _very_ big.  For example, while
1007 220 jeremybenn
          booting the Linux kernel, version 2.6.34, a log file 1.2GB in
1008
          size was generated.
1009 202 julius
 
1010
`exe_bin_insn_log_file = FILENAME'
1011
     Filename for the binary execution log filename if
1012
     `exe_bin_insn_log' is enabled.  Default `exe-insn.bin'.
1013
 
1014 19 jeremybenn
`clkcycle = VALUE[ps|ns|us|ms]'
1015 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
1016
     specified, `ps' is assumed.  Default 4000ps (250MHz).
1017 19 jeremybenn
 
1018
 
1019

1020
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
1021
 
1022
3.2.2 Verification API (VAPI) Configuration
1023
-------------------------------------------
1024
 
1025
The Verification API (VAPI) provides a TCP/IP interface to allow
1026 82 jeremybenn
components of the simulation to be controlled externally.  *Note
1027 19 jeremybenn
Verification API: Verification API, for more details.
1028
 
1029 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
1030
section may appear at most once.  The following parameters may be
1031 19 jeremybenn
specified.
1032
 
1033
`enabled = 0|1'
1034
     If 1 (true), verification API is enabled and its server started.
1035
     If 0 (the default), it is disabled.
1036
 
1037
`server_port = VALUE'
1038
     When VAPI is enabled, communication will be via TCP/IP on the port
1039 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
1040 19 jeremybenn
     The default value is 50000.
1041
 
1042 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
1043 19 jeremybenn
          practice suggests users should adopt port values in the
1044 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
1045 19 jeremybenn
 
1046
`log_enabled = 0|1'
1047
     If 1 (true), all VAPI requests and sent commands will be logged.
1048 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
1049 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
1050
 
1051
          Caution: This can generate a substantial amount of file I/O
1052
          and seriously degrade simulator performance.
1053
 
1054
`hide_device_id = 0|1'
1055 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
1056
     device ID.  This feature (when set to 1) is provided for backwards
1057 19 jeremybenn
     compatibility with an old version of VAPI.
1058
 
1059
`vapi_log_file = "FILENAME"'
1060
     Use `filename' as the file for logged data is logging is enabled
1061 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
1062 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
1063
     supported for this parameter, but deprecated.
1064
 
1065
 
1066

1067
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
1068
 
1069
3.2.3 Custom Unit Compiler (CUC) Configuration
1070
----------------------------------------------
1071
 
1072
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
1073 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
1074
beyond the initial prototype phase.  The configuration parameters are
1075 19 jeremybenn
described here for the record.
1076
 
1077 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
1078
appear at most once.  The following parameters may be specified.
1079 19 jeremybenn
 
1080
`memory_order = none|weak|strong|exact'
1081
     This parameter specifies the memory ordering required:
1082
 
1083
    `memory_order=none'
1084
          Different memory ordering, even if there are dependencies.
1085
          Bursts can be made, width can change.
1086
 
1087 346 jeremybenn
    `memory_order=weak'
1088 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
1089 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
1090
          change.
1091
 
1092 346 jeremybenn
    `memory_order=strong'
1093 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
1094 19 jeremybenn
 
1095 346 jeremybenn
    `memory_order=exact'
1096 19 jeremybenn
          Exactly the same memory ordering and widths.
1097
 
1098
 
1099 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1100 19 jeremybenn
     orderings are ignored with a warning.
1101
 
1102
`calling_convention = 0|1'
1103 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1104 19 jeremybenn
     (the default), they may use other convenitions.
1105
 
1106
`enable_bursts = 0 | 1'
1107 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1108 19 jeremybenn
     not detected.
1109
 
1110
`no_multicycle = 0 | 1'
1111 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1112
     (the default), multicycle logic paths will be generated.
1113 19 jeremybenn
 
1114
`timings_file = "FILENAME"'
1115 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1116
     default value is `"virtex.tim"'.  For backwards compatibility, the
1117 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1118
     deprecated.
1119
 
1120
 
1121

1122
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1123
 
1124
3.3 Configuring the OpenRISC Architectural Components
1125
=====================================================
1126
 
1127
* Menu:
1128
 
1129
* CPU Configuration::
1130
* Memory Configuration::
1131
* Memory Management Configuration::
1132
* Cache Configuration::
1133
* Interrupt Configuration::
1134
* Power Management Configuration::
1135
* Branch Prediction Configuration::
1136
* Debug Interface Configuration::
1137
 
1138

1139
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1140
 
1141
3.3.1 CPU Configuration
1142
-----------------------
1143
 
1144 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1145
appear only once.  At present Or1ksim does not model multi-CPU systems.
1146 19 jeremybenn
The following parameters may be specified.
1147
 
1148
`ver = VALUE'
1149
 
1150
`cfg = VALUE'
1151
 
1152
`rev = VALUE'
1153
     The values are used to form the corresponding fields in the `VR'
1154 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1155 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1156
     and `cfg', 6 bits for `rev').
1157
 
1158
`upr = VALUE'
1159
     Used as the value of the Unit Present Register (UPR) Special
1160 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1161 19 jeremybenn
     i.e.
1162
        * UPR present (0x00000001)
1163
 
1164
        * Data cache present (0x00000002)
1165
 
1166
        * Instruction cache present (0x00000004)
1167
 
1168
        * Data MMY present (0x00000008)
1169
 
1170
        * Instruction MMU present (0x00000010)
1171
 
1172
        * Debug unit present (0x00000040)
1173
 
1174
        * Power management unit present (0x00000100)
1175
 
1176
        * Programmable interrupt controller present (0x00000200)
1177
 
1178
        * Tick timer present (0x00000400)
1179
 
1180
     However, with the exection of the UPR present (0x00000001) and tick
1181
     timer present, the various fields will be modified with the values
1182
     specified in their corresponding configuration sections.
1183
 
1184
`cfgr = VALUE'
1185
     Sets the CPU configuration register (Special Purpose Register 2) to
1186 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1187
     instruction set.  Attempts to set any other value are accepted, but
1188 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1189
 
1190
`sr = VALUE'
1191
     Sets the supervision register Special Purpose Register (SPR 0x11)
1192 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1193 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1194
 
1195 98 jeremybenn
          Note: This is particularly useful when an image is held in
1196
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1197
          so that interrupt vectors are basedf at 0xf0000000, rather
1198
          than 0x0.
1199
 
1200 19 jeremybenn
`superscalar = 0|1'
1201 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1202 19 jeremybenn
     0.
1203
 
1204
     In the current simulator, the only functional effect of superscalar
1205
     mode is to affect the calculation of the number of cycles taken to
1206
     execute an instruction.
1207
 
1208
          Caution: The code for this does not appear to be complete or
1209
          well tested, so users are advised not to use this option.
1210
 
1211
`hazards = 0|1'
1212 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1213
     value is 0.
1214 19 jeremybenn
 
1215
     In the current simulator, the only functional effect is to cause
1216
     logging of hazard waiting information if the CPU is superscalar.
1217
     However nowhere in the simulator is this data actually computed,
1218
     so the net result is probably to have no effect.
1219
 
1220
     if harzards are tracked, current hazards can be displayed using the
1221
     simulator's `r' command.
1222
 
1223
          Caution: The code for this does not appear to be complete or
1224
          well tested, so users are advised not to use this option.
1225
 
1226
`dependstats = 0|1'
1227 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1228
     value 0.
1229 19 jeremybenn
 
1230
     If these values are calculated, the depencies can be displayed
1231
     using the simulator's `stat' command.
1232
 
1233
          Note: This field must be enabled, if execution execution flow
1234
          tracking (field `history') has been requested in the simulator
1235
          configuration section (*note Simulator Behavior: Simulator
1236
          Behavior.).
1237
 
1238
`sbuf_len = VALUE'
1239
     The length of the store buffer is set to VALUE, which must be no
1240 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1241
     warning.  Negative values will be treated as 0 with a warning.
1242
     Use 0 to disable the store buffer.
1243 19 jeremybenn
 
1244
     When the store buffer is active, stores are accumulated and
1245
     committed when I/O is idle.
1246
 
1247 100 julius
`hardfloat = 0|1'
1248 346 jeremybenn
     If 1, hardfloat instructions are enabled.  Default value 0.
1249 19 jeremybenn
 
1250 104 jeremybenn
 
1251 19 jeremybenn

1252
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1253
 
1254
3.3.2 Memory Configuration
1255
--------------------------
1256
 
1257 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1258 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1259 19 jeremybenn
 
1260 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1261 385 jeremybenn
     controller.  If a memory controller is enabled, then appropriate
1262
     initalization code must be provided.  The section describing
1263
     memory controller configuration describes the steps necessary for
1264
     using smaller or larger memory sections (*note Memory Controller
1265
     Configuration: Memory Controller Configuration.).
1266 98 jeremybenn
 
1267 385 jeremybenn
     The "uClibc" startup code initalizes a memory controller, assumed
1268
     to be mapped at 0x93000000.  If a memory controller is _not_
1269
     enabled, then the standard C library code will generate memory
1270
     access errors.  The solution is to declare an additional writable
1271
     memory block, mimicing the memory controller's register bank as
1272
     follows.
1273 98 jeremybenn
 
1274
          section memory
1275
            pattern = 0x00
1276
            type = unknown
1277
            name = "MC shadow"
1278
            baseaddr = 0x93000000
1279
            size     = 0x00000080
1280
            delayr = 2
1281
            delayw = 4
1282
          end
1283
 
1284
 
1285
The following parameters may be specified.
1286
 
1287 418 julius
`type=random|pattern|unknown|zero|exitnops'
1288 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1289 19 jeremybenn
     default value is `unknown'.
1290
 
1291
    `random'
1292 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1293 19 jeremybenn
          random generator may be set using the `random_seed' field in
1294
          this section (see below), thus ensuring the same "random"
1295
          values are used each time.
1296
 
1297
    `pattern'
1298
          Set the memory values to be a pattern value, which is set
1299
          using the `pattern' field in this section (see below).
1300
 
1301
    `unknown'
1302 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1303 240 julius
          This option will yield faster initialization of the
1304 346 jeremybenn
          simulator.  This is the default.
1305 19 jeremybenn
 
1306
    `zero'
1307 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1308 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1309
          such.
1310
 
1311 420 jeremybenn
               Note: As a consequence, if the `pattern' field is
1312
               _subsequently_ specified in this section, the value in
1313
               that field will be used instead of zero to initialize
1314
               the memory.
1315
 
1316 418 julius
    `exitnops'
1317
          Set the memory values to be an instruction used to signal end
1318
          of simulation. This is useful for causing immediate end of
1319
          simulation when PC corruption occurs.
1320
 
1321 19 jeremybenn
 
1322
`random_seed = VALUE'
1323 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1324 19 jeremybenn
     has any effect for memory type `random'.
1325
 
1326
     The default value is -1, which means the seed will be set from a
1327
     call to the `time' function, thus ensuring different random values
1328 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1329 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1330
     values used in any particular run.
1331
 
1332
`pattern = VALUE'
1333 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1334
     default value is 0.  This only has any effect for memory type
1335
     `pattern'.  The least significant 8 bits of this value is used to
1336
     initialize each byte.  More than 8 bits can be specified, but will
1337 19 jeremybenn
     ignored with a warning.
1338
 
1339
          Tip: The default value, is equivalent to setting the memory
1340 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1341 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1342
          and not specifying a value for `pattern'.
1343
 
1344
`baseaddr = VALUE'
1345 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1346 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1347
     The default value is 0.
1348
 
1349
`size = VALUE'
1350 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1351
     be a multiple of 4 (i.e.  word aligned).  The default value is
1352
     1024.
1353 19 jeremybenn
 
1354
          Note: When allocating memory, the simulator will allocate the
1355
          nearest 2^n bytes greater than or equal to VALUE, and will not
1356
          notice memory misses in any part of the memory between VALUE
1357
          and the amount allocated.
1358
 
1359
          As a consequence users are strongly recommended to specify
1360 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1361 19 jeremybenn
          amount of memory is required, it should be specified as
1362
          separate, contiguous blocks, each of which is a power of 2 in
1363
          size.
1364
 
1365
`name = "TEXT"'
1366 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1367
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1368 19 jeremybenn
     `"anonymous memory block"'.
1369
 
1370
          Note: It is not clear that this information is currently ever
1371 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1372 19 jeremybenn
          command of the simulator ignores it.
1373
 
1374
`ce = VALUE'
1375 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1376 19 jeremybenn
     instance should have a unique chip enable index, which should be
1377 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1378 19 jeremybenn
     controller when identifying different memory instances.
1379
 
1380 346 jeremybenn
     There is no requirement to set `ce' if a memory controller is not
1381
     enabled.  The default value is -1 (invalid).
1382 19 jeremybenn
 
1383
`mc = VALUE'
1384 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1385 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1386
     for a memory controller (*note Memory Controller Configuration:
1387
     Memory Controller Configuration.).
1388
 
1389 346 jeremybenn
     There is no requirement to set `mc' if a memory controller is not
1390
     enabled.  Default value is 0, which is also the default value of a
1391 98 jeremybenn
     memory controller `index' field.  This is suitable therefore for
1392
     designs with just one memory controller.
1393 19 jeremybenn
 
1394
`delayr = VALUE'
1395 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1396
     memory does not support reading.  Default value 1.  The simulator
1397 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1398
     count when reading from main memory.
1399
 
1400
`delayw = VALUE'
1401 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1402
     memory does not support writing.  Default value 1.  The simulator
1403 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1404
     count when writing to main memory.
1405
 
1406
`log = "FILE"'
1407
     If specified, `file' names a file for all memory accesses to be
1408 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1409 19 jeremybenn
     that the memory is not logged.
1410
 
1411
 
1412

1413
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1414
 
1415
3.3.3 Memory Management Configuration
1416
-------------------------------------
1417
 
1418
Memory Management Unit (MMU) configuration is described in `section
1419
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1420 82 jeremybenn
Each section should appear at most once.  The following parameters may
1421 19 jeremybenn
be specified.
1422
 
1423
`enabled = 0|1'
1424
     If 1 (true), the data or instruction (as appropriate) MMU is
1425 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1426 19 jeremybenn
 
1427
`nsets = VALUE'
1428
     Sets the number of data or instruction (as appropriate) TLB sets to
1429 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1430
     which do not fit these criteria are ignored with a warning.  The
1431 19 jeremybenn
     default value is 1.
1432
 
1433
`nways = VALUE'
1434
     Sets the number of data or instruction (as appropriate) TLB ways to
1435 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1436
     this range are ignored with a warning.  The default value is 1.
1437 19 jeremybenn
 
1438
`pagesize = VALUE'
1439
     The data or instruction (as appropriate) MMU page size is set to
1440 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1441
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1442 19 jeremybenn
 
1443
`entrysize = VALUE'
1444
     The data or instruction (as appropriate) MMU entry size is set to
1445 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1446
     of 2 are ignored with a warning.  The default value is 1.
1447 19 jeremybenn
 
1448
          Note: Or1ksim does not appear to use the `entrysize' parameter
1449 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1450 19 jeremybenn
          not seem to matter.
1451
 
1452
`ustates = VALUE'
1453
     The number of instruction usage states for the data or instruction
1454
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1455 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1456 19 jeremybenn
     value is 2.
1457
 
1458
          Note: Or1ksim does not appear to use the `ustates' parameter
1459 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1460 19 jeremybenn
          not seem to matter.
1461
 
1462
`hitdelay = VALUE'
1463
     Set the number of cycles a data or instruction (as appropriate) MMU
1464 82 jeremybenn
     hit costs.  Default value 1.
1465 19 jeremybenn
 
1466
`missdelay = VALUE'
1467
     Set the number of cycles a data or instruction (as appropriate) MMU
1468 82 jeremybenn
     miss costs.  Default value 1.
1469 19 jeremybenn
 
1470
 
1471

1472
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1473
 
1474
3.3.4 Cache Configuration
1475
-------------------------
1476
 
1477
Cache configuration is described in `section dc' (for the data cache)
1478 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1479
appear at most once.  The following parameters may be specified.
1480 19 jeremybenn
 
1481
`enabled = 0|1'
1482
     If 1 (true), the data or instruction (as appropriate) cache is
1483 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1484 19 jeremybenn
 
1485
`nsets = VALUE'
1486
     Sets the number of data or instruction (as appropriate) cache sets
1487
     to VALUE, which must be a power of two, not exceeding
1488
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1489 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1490
     both defined in the code to be 1024).  The default value is 1.
1491 19 jeremybenn
 
1492
`nways = VALUE'
1493
     Sets the number of data or instruction (as appropriate) cache ways
1494
     to VALUE, which must be a power of two, not exceeding
1495
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1496 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1497
     both defined in the code to be 32).  The default value is 1.
1498 19 jeremybenn
 
1499
`blocksize = VALUE'
1500
     The data or instruction (as appropriate) cache block size is set to
1501 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1502 19 jeremybenn
 
1503
`ustates = VALUE'
1504
     The number of instruction usage states for the data or instruction
1505
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1506
     The default value is 2.
1507
 
1508
`hitdelay = VALUE'
1509 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1510
     cache hit costs.  Default value 1.
1511 19 jeremybenn
 
1512
`missdelay = VALUE'
1513 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1514
     cache miss costs.  Default value 1.
1515 19 jeremybenn
 
1516
`load_hitdelay = VALUE'
1517 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1518
     costs.  Default value 2.
1519 19 jeremybenn
 
1520
`load_missdelay = VALUE'
1521 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1522
     miss costs.  Default value 2.
1523 19 jeremybenn
 
1524
`store_hitdelay = VALUE'
1525 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1526
     costs.  Default value 0.
1527 19 jeremybenn
 
1528
`store_missdelay = VALUE'
1529 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1530
     miss costs.  Default value 0.
1531 19 jeremybenn
 
1532
 
1533

1534
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1535
 
1536
3.3.5 Interrupt Configuration
1537
-----------------------------
1538
 
1539
Programmable Interrupt Controller (PIC) configuration is described in
1540 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1541
mechanism for handling multiple interrupt controllers.  The following
1542 19 jeremybenn
parameters may be specified.
1543
 
1544
`enabled = 0|1'
1545 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1546
 
1547 19 jeremybenn
 
1548
`edge_trigger = 0|1'
1549
     If 1 (true, the default), the programmable interrupt controller is
1550 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1551 19 jeremybenn
 
1552
 
1553

1554
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1555
 
1556
3.3.6 Power Management Configuration
1557
------------------------------------
1558
 
1559 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1560 19 jeremybenn
(which only happens when the power management unit is enabled) of
1561
setting the different bits in the power management Special Purpose
1562
Register (PMR, SPR 0x4000) is
1563
 
1564
`SDF (bit mask 0x0000000f)'
1565
     No effect - these bits are ignored
1566
 
1567
`DME (bit mask 0x00000010)'
1568
`SME (bit mask 0x00000020)'
1569
     Both these bits cause the processor to stop executing
1570 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1571 19 jeremybenn
     VAPI etc) carry on as normal.
1572
 
1573
`DCGE (bit mask 0x00000004)'
1574
     No effect - this bit is ignored
1575
 
1576
`SUME (bit mask 0x00000008)'
1577
     Enabling this bit causes a message to be printed, advising that the
1578
     processor is suspending and the simulator exits.
1579
 
1580
 
1581
On reset all bits are cleared.
1582
 
1583 82 jeremybenn
Power management configuration is described in `section pm'.  This
1584
section may appear at most once.  The following parameter may be
1585 19 jeremybenn
specified.
1586
 
1587
`enabled = 0|1'
1588 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1589
     is disabled.
1590 19 jeremybenn
 
1591
 
1592

1593
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1594
 
1595
3.3.7 Branch Prediction Configuration
1596
-------------------------------------
1597
 
1598
From examining the code base, it seems the branch prediction function
1599 82 jeremybenn
is not fully implemented.  At present the functionality seems
1600
restricted to collection of statistics.
1601 19 jeremybenn
 
1602 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1603
section may appear at most once.  The following parameters may be
1604 19 jeremybenn
specified.
1605
 
1606
`enabled = 0|1'
1607 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1608 19 jeremybenn
     is disabled.
1609
 
1610
`btic = 0|1'
1611
     If 1 (true), the branch target instruction cache model is enabled.
1612
     If 0 (the default), it is disabled.
1613
 
1614
`sbp_bf_fwd = 0|1'
1615 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1616 19 jeremybenn
 
1617
     instruction.
1618
 
1619
`sbp_bnf_fwd = 0|1'
1620 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1621
     If 0 (the default), do not use forward prediction for this
1622 19 jeremybenn
     instruction.
1623
 
1624
`hitdelay = VALUE'
1625 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1626 19 jeremybenn
     value 0.
1627
 
1628
`missdelay = VALUE'
1629 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1630 19 jeremybenn
     value 0.
1631
 
1632
 
1633

1634
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1635
 
1636
3.3.8 Debug Interface Configuration
1637
-----------------------------------
1638
 
1639
The debug unit and debug interface configuration is described in
1640 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1641 19 jeremybenn
parameters may be specified.
1642
 
1643
`enabled = 0|1'
1644 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1645 19 jeremybenn
     disabled.
1646
 
1647
          Note: This enables the functionality of the debug unit (its
1648 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1649
          external interface to the debug unit.  For that, see
1650 235 jeremybenn
          `rsp_enabled' below.
1651 19 jeremybenn
 
1652
`rsp_enabled = 0|1'
1653
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1654
     provding an interface to an external GNU debugger, using the port
1655
     specified in the `rsp_port' field (see below), or the
1656 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1657 19 jeremybenn
     not started, and no external interface is provided.
1658
 
1659
     For more detailed information on the interface to the GNU Debugger
1660
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1661
     Practical Experience with the OpenRISC 1000 Architecture', by
1662
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1663
 
1664
`rsp_port = VALUE'
1665
     VALUE specifies the port to be used for the GDB "Remote Serial
1666 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1667
     51000.  If the value 0 is specified, Or1ksim will instead look for
1668 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1669
 
1670
          Tip: There is no registered port for Or1ksim "Remote Serial
1671 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1672
          users should adopt port values in the "Dynamic" or "Private"
1673
          port range, i.e.  49152-65535.
1674 19 jeremybenn
 
1675
`vapi_id = VALUE'
1676
     VALUE specifies the value of the Verification API (VAPI) base
1677 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1678 19 jeremybenn
     Verification API, for more details.
1679
 
1680
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1681
     JTAG protocol transactions will be logged to the VAPI log file, if
1682 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
1683
     the debug unit.  No VAPI commands are sent, nor requests handled.
1684 19 jeremybenn
 
1685
 
1686

1687
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
1688
 
1689
3.4 Configuring Memory Mapped Peripherals
1690
=========================================
1691
 
1692 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1693 19 jeremybenn
(unlike other components) by default they are enabled.
1694
 
1695
* Menu:
1696
 
1697
* Memory Controller Configuration::
1698
* UART Configuration::
1699
* DMA Configuration::
1700
* Ethernet Configuration::
1701
* GPIO Configuration::
1702
* Display Interface Configuration::
1703
* Frame Buffer Configuration::
1704
* Keyboard Configuration::
1705
* Disc Interface Configuration::
1706
* Generic Peripheral Configuration::
1707
 
1708

1709
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
1710
 
1711
3.4.1 Memory Controller Configuration
1712
-------------------------------------
1713
 
1714
The memory controller used in Or1ksim is the component implemented at
1715 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
1716 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
1717 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1718
memory mapped component, which resides on the main OpenRISC Wishbone
1719
data bus.
1720 19 jeremybenn
 
1721 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
1722 19 jeremybenn
section may appear multiple times, specifying multiple memory
1723 98 jeremybenn
controllers.
1724 19 jeremybenn
 
1725 385 jeremybenn
     Warning: There are known to be problems with the current memory
1726
     controller, which currently is not included in the regression test
1727
     suite. Users are advised not to use the memory controller in the
1728
     current release.
1729 98 jeremybenn
 
1730 385 jeremybenn
     Caution: There is no initialization code in the standard "newlib"
1731
     library.
1732
 
1733
     The standard "uClibc" library assumes a memory controller mapped
1734
     at 0x93000000 and will initialize the memory controller to expect
1735
     64MB memory blocks, and any memory declarations _must_ reflect
1736
     this.
1737
 
1738 98 jeremybenn
     If smaller memory blocks are declared with a memory controller,
1739
     then sufficient memory will not be allocated by Or1ksim, but out of
1740 346 jeremybenn
     range memory accesses will not be trapped.  For example declaring a
1741 98 jeremybenn
     memory section from 0-4MB with a memory controller enabled would
1742
     mean that accesses between 4MB and 64MB would be permitted, but
1743
     having no allocated memory would likely cause a segmentation fault.
1744
 
1745
     If the user is determined to use smaller memories with the memory
1746
     controller, then custom initialization code must be provided, to
1747
     ensure the memory controller traps out-of-memory accesses.
1748
 
1749
The following parameters may be specified.
1750
 
1751 19 jeremybenn
`enabled = 0|1'
1752 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
1753
     0, it is disabled.
1754 19 jeremybenn
 
1755
          Note: The memory controller can effectively also be disabled
1756
          by setting an appropriate power on control register value
1757 82 jeremybenn
          (see below).  However this should only be used if it is
1758 19 jeremybenn
          desired to specifically model this behavior of the memory
1759
          controller, not as a way of disabling the memory controller
1760
          in general.
1761
 
1762
`baseaddr = VALUE'
1763
     Set the base address of the memory controller's memory mapped
1764 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
1765 19 jeremybenn
     sensible value.
1766
 
1767
     The memory controller has a 7 bit address bus, with a total of 19
1768
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1769
     addresses 0x50 through 0x7c are not used).
1770
 
1771
`poc = VALUE'
1772
     Specifies the value of the power on control register, The least
1773
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
1774
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
1775
     the type of memory connected (use 0 for a disabled interface, 1
1776
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
1777
     devices).
1778
 
1779
     If other bits are specified, they are ignored with a warning.
1780
 
1781
          Caution: The default value, 0, corresponds to a disabled
1782
          8-bit bus, and is likely not the most suitable value
1783
 
1784
`index = VALUE'
1785
     Specify the index of this memory controller amongst all the memory
1786 82 jeremybenn
     controllers.  This value should be unique for each memory
1787 19 jeremybenn
     controller, and is used to associate specific memories with the
1788
     controller, through the `mc' field in the `section memory'
1789
     configuration (*note Memory Configuration: Memory Configuration.).
1790
 
1791
     The default value, 0, is suitable when there is only one memory
1792
     controller.
1793
 
1794
 
1795

1796
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
1797
 
1798
3.4.2 UART Configuration
1799
------------------------
1800
 
1801
The UART implemented in Or1ksim follows the specification of the
1802 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
1803 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
1804
 
1805
The component provides a number of interfaces to emulate the behavior
1806
of an external terminal connected to the UART.
1807
 
1808 82 jeremybenn
UART configuration is described in `section uart'.  This section may
1809
appear multiple times, specifying multiple UARTs.  The following
1810 19 jeremybenn
parameters may be specified.
1811
 
1812
`enabled = 0|1'
1813 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
1814 19 jeremybenn
     disabled.
1815
 
1816
`baseaddr = VALUE'
1817
     Set the base address of the UART's memory mapped registers to
1818 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1819 19 jeremybenn
 
1820
     The UART has a 3 bit address bus, with a total of 8 8-bit
1821
     registers, at addresses 0x0 through 0x7.
1822
 
1823
`channel = "TYPE:ARGS"'
1824
     Specify the channel representing the terminal connected to the UART
1825
     Rx & Tx pins.
1826
 
1827
    `channel="file:`rxfile',`txfile'"'
1828
          Read input characters from the file `rxfile' and write output
1829
          characters to the file `txfile' (which will be created if
1830
          required).
1831
 
1832
    `channel="xterm:ARGS"'
1833
          Create an xterm on startup, write UART Tx traffic to the
1834
          xterm and take Rx traffic from the keyboard when the xterm
1835 82 jeremybenn
          window is selected.  Additional arguments to the xterm
1836
          command (for example specifying window size may be specified
1837
          in ARGS, or this may be left blank.
1838 19 jeremybenn
 
1839
    `channel="tcp:VALUE"'
1840
          Open the TCP/IP port specified by VALUE and read and write
1841
          UART traffic from and to it.
1842
 
1843
          Typically a telnet session is connected to the other end of
1844
          this port.
1845
 
1846
               Tip: There is no registered port for Or1ksim telnet UART
1847 82 jeremybenn
               connection.  Priviledged access is required to read
1848 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
1849 346 jeremybenn
               Instead users should use port values in the "Dynamic" or
1850
               "Private" port range, i.e.  49152-65535.
1851 19 jeremybenn
 
1852
    `channel="fd:`rxfd',`txfd'"'
1853
          Read and write characters from and to the existing open
1854
          numerical file descriptors, file `rxfd' and `txfd'.
1855
 
1856
    `channel="tty:device=/dev/ttyS0,baud=9600"'
1857
          Read and write characters from and to a physical serial port.
1858 346 jeremybenn
          The precise device (shown here as `/dev/ttyS0') may vary from
1859
          machine to machine.
1860 19 jeremybenn
 
1861
 
1862
     The default value for this field is `"xterm:"'.
1863
 
1864
`irq = VALUE'
1865 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
1866 19 jeremybenn
 
1867
`16550 = 0|1'
1868 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
1869
     default), it has the functionality of a 16450.  The principal
1870 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
1871
 
1872
`jitter = VALUE'
1873
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
1874 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
1875 19 jeremybenn
 
1876
          Note: This functionality has yet to be implemented, so this
1877
          parameter has no effect.
1878
 
1879
`vapi_id = VALUE'
1880
     VALUE specifies the value of the Verification API (VAPI) base
1881 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
1882 19 jeremybenn
     Verification API, for more details, which details the use of the
1883
     VAPI with the UART.
1884
 
1885
 
1886

1887
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
1888
 
1889
3.4.3 DMA Configuration
1890
-----------------------
1891
 
1892
The DMA controller used in Or1ksim is the component implemented at
1893 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
1894 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
1895 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1896
memory mapped component, which resides on the main OpenRISC Wishbone
1897
data bus.  The present implementation is incomplete, intended only to
1898
support the Ethernet interface (*note Ethernet Configuration::),
1899
although the Ethernet interface is not yet completed.
1900 19 jeremybenn
 
1901 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
1902
appear multiple times, specifying multiple DMA controllers.  The
1903 19 jeremybenn
following parameters may be specified.
1904
 
1905
`enabled = 0|1'
1906 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
1907
     it is disabled.
1908 19 jeremybenn
 
1909
`baseaddr = VALUE'
1910
     Set the base address of the DMA's memory mapped registers to
1911 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1912 19 jeremybenn
 
1913
     The DMA controller has a 10 bit address bus, with a total of 253
1914 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
1915
     0x010 control the overall behavior of the DMA controller.  There
1916
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
1917
     channels available.  Addresses 0x014 through 0x01c are not used.
1918 19 jeremybenn
 
1919
`irq = VALUE'
1920 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
1921 19 jeremybenn
     0.
1922
 
1923
`vapi_id = VALUE'
1924
     VALUE specifies the value of the Verification API (VAPI) base
1925 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
1926 19 jeremybenn
     API: Verification API, for more details, which details the use of
1927
     the VAPI with the DMA controller.
1928
 
1929
 
1930

1931
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
1932
 
1933
3.4.4 Ethernet Configuration
1934
----------------------------
1935
 
1936
The Ethernet MAC used in Or1ksim is the component implemented at
1937 98 jeremybenn
OpenCores, and found in the top level SVN directory, `ethmac'.  It also
1938
forms part of the OpenRISC SoC, ORPSoC.  It is described in the
1939 19 jeremybenn
document `Ethernet IP Core Specification' by Igor Mohor, which can be
1940 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1941
which resides on the main OpenRISC Wishbone data bus.
1942 19 jeremybenn
 
1943 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
1944
section may appear multiple times, specifying multiple Ethernet
1945
interfaces.  The following parameters may be specified.
1946 19 jeremybenn
 
1947
`enabled = 0|1'
1948 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
1949
     is disabled.
1950 19 jeremybenn
 
1951
`baseaddr = VALUE'
1952
     Set the base address of the MAC's memory mapped registers to
1953 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1954 19 jeremybenn
 
1955
     The Ethernet MAC has a 7-bit address bus, with a total of 21
1956 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
1957 19 jeremybenn
 
1958
          Note: The Ethernet specification describes a Tx control
1959 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
1960
          is not implemented in the Or1ksim model.
1961 19 jeremybenn
 
1962
`dma = VALUE'
1963
     VALUE specifies the DMA controller with which this Ethernet is
1964 82 jeremybenn
     associated.  The default value is 0.
1965 19 jeremybenn
 
1966
          Note: Support for external DMA is not provided in the current
1967 82 jeremybenn
          implementation, and this value is ignored.  In any case there
1968 19 jeremybenn
          is no equivalent field to which this can be matched in the
1969
          current DMA component implementation (*note DMA
1970
          Configuration: DMA Configuration.).
1971
 
1972
`irq = VALUE'
1973 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
1974 19 jeremybenn
 
1975
`rtx_type = 0|1'
1976
     If 1 (true) use a socket interface to the Ethernet (see parameter
1977 82 jeremybenn
     `sockif' below).  If 0 (the default), use a file interface,
1978
     reading and writing from and to the files specified in the
1979
     `rxfile' and `txfile' parameters (see below).
1980 19 jeremybenn
 
1981
          Note: By default the socket interface is not provided in
1982 82 jeremybenn
          Or1ksim.  If it is required, this must be requested when
1983 19 jeremybenn
          configuring, by use of the `--enable-ethphy' option to
1984
          `configure'.
1985
 
1986
               configure --target=or32-uclinux --enable-ethphy ...
1987
 
1988
`rx_channel = RXVALUE'
1989
`tx_channel = TXVALUE'
1990
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
1991 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
1992 19 jeremybenn
 
1993
          Note: As noted above, support for external DMA is not
1994
          provided in the current implementation, and so these values
1995
          are ignored.
1996
 
1997
`rxfile = "RXFILE"'
1998
`txfile = "TXFILE"'
1999
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
2000
     as input and TXFILE specifies the fie to use as output.
2001
 
2002 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
2003
     packet length (32 bits), followed by that many bytes of data.
2004
     Once the input file is empty, the Ethernet MAC behaves as though
2005
     there were no data on the Ethernet.  The default values of these
2006 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
2007
 
2008 82 jeremybenn
     The input file must exist and be readable.  The output file must be
2009
     writable and will be created if necessary.  If either of these
2010 19 jeremybenn
     conditions is not met, a warning will be given.
2011
 
2012
`sockif = "SERVICE"'
2013
     When `rtx_type' is 1 (see above), SERVICE specifies the service to
2014 82 jeremybenn
     use for communication.  This may be TCP/IP or UDP/IP.  The default
2015 19 jeremybenn
     value of this parameter is `"or1ksim_eth"'.
2016
 
2017
`vapi_id = VALUE'
2018
     VALUE specifies the value of the Verification API (VAPI) base
2019 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
2020 19 jeremybenn
     Verification API, for more details, which details the use of the
2021
     VAPI with the DMA controller.
2022
 
2023
 
2024

2025
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
2026
 
2027
3.4.5 GPIO Configuration
2028
------------------------
2029
 
2030
The GPIO used in Or1ksim is the component implemented at OpenCores, and
2031 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
2032 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
2033 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
2034 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
2035
 
2036 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
2037
appear multiple times, specifying multiple GPIO devices.  The following
2038 19 jeremybenn
parameters may be specified.
2039
 
2040
`enabled = 0|1'
2041 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
2042 19 jeremybenn
     disabled.
2043
 
2044
`baseaddr = VALUE'
2045
     Set the base address of the GPIO's memory mapped registers to
2046 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2047 19 jeremybenn
 
2048
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
2049
     registers, although the number of bits that are actively used
2050 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
2051 19 jeremybenn
 
2052
`irq = VALUE'
2053 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
2054 19 jeremybenn
 
2055
`vapi_id = VALUE'
2056
     VALUE specifies the value of the Verification API (VAPI) base
2057 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
2058 19 jeremybenn
     Verification API, for more details, which details the use of the
2059 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
2060 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
2061
     but deprecated.
2062
 
2063
 
2064

2065
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
2066
 
2067
3.4.6 Display Interface Configuration
2068
-------------------------------------
2069
 
2070
Or1ksim models a VGA interface to an external monitor.  The VGA
2071
controller used in Or1ksim is the component implemented at OpenCores,
2072 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
2073 82 jeremybenn
for the optional hardware cursors.  It is described in the document
2074 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
2075 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2076
which resides on the main OpenRISC Wishbone data bus.
2077 19 jeremybenn
 
2078
The current implementation provides only functionality to dump the
2079
screen to a file at intervals.
2080
 
2081 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
2082 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
2083
The following parameters may be specified.
2084
 
2085
`enabled = 0|1'
2086 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
2087 19 jeremybenn
     disabled.
2088
 
2089
`baseaddr = VALUE'
2090
     Set the base address of the VGA controller's memory mapped
2091 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2092 19 jeremybenn
     sensible value.
2093
 
2094
     The VGA controller has a 12-bit address bus, with 7 32-bit
2095
     registers, at addresses 0x000 through 0x018, and two color lookup
2096 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2097 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2098
     are not used.
2099
 
2100
`irq = VALUE'
2101 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2102 19 jeremybenn
     0.
2103
 
2104
`refresh_rate = VALUE'
2105 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2106 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2107
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2108
     50 times per simulated second.
2109
 
2110
`txfile = "FILE"'
2111
     FILE specifies the base of the filename for screen dumps.
2112
     Successive screen dumps will be in BMP format, in files with the
2113
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2114 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2115 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2116
     supported for this parameter, but deprecated.
2117
 
2118
 
2119

2120
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2121
 
2122
3.4.7 Frame Buffer Configuration
2123
--------------------------------
2124
 
2125 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2126 19 jeremybenn
     configuration fields are described here, but the component should
2127 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2128 19 jeremybenn
     to make screen dumps to file.
2129
 
2130 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2131
may appear multiple times, specifying multiple frame buffers.  The
2132 19 jeremybenn
following parameters may be specified.
2133
 
2134
`enabled = 0|1'
2135 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2136 19 jeremybenn
     is disabled.
2137
 
2138
`baseaddr = VALUE'
2139
     Set the base address of the frame buffer's memory mapped registers
2140 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2141
     value.
2142 19 jeremybenn
 
2143
     The frame buffer has an 121-bit address bus, with 4 32-bit
2144
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2145 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2146 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2147
 
2148
`refresh_rate = VALUE'
2149 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2150 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2151
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2152
     50 times per simulated second.
2153
 
2154
`txfile = "FILE"'
2155
     FILE specifies the base of the filename for screen dumps.
2156
     Successive screen dumps will be in BMP format, in files with the
2157
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2158 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2159 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2160
     supported for this parameter, but deprecated.
2161
 
2162
 
2163

2164
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2165
 
2166
3.4.8 Keyboard Configuration (PS2)
2167
----------------------------------
2168
 
2169 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2170 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2171 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2172
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2173 19 jeremybenn
standard, this is presumably what is expected with this device.
2174
 
2175
The implementation only provides for keyboard support, which is
2176 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2177 19 jeremybenn
 
2178
     Caution: A standard i8042 device has two registers at addresses
2179 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2180
     suggests that the Or1ksim component places these registers at
2181
     addresses 0x00 and 0x04.
2182 19 jeremybenn
 
2183
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2184
     implements the i8042 device driver, anticipating these registers
2185 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2186 19 jeremybenn
     code will work.
2187
 
2188
     This component should be used with caution.
2189
 
2190 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2191
appear multiple times, specifying multiple keyboard interfaces.  The
2192 19 jeremybenn
following parameters may be specified.
2193
 
2194
`enabled = 0|1'
2195 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2196 19 jeremybenn
     disabled.
2197
 
2198
`baseaddr = VALUE'
2199
     Set the base address of the keyboard's memory mapped registers to
2200 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2201 19 jeremybenn
 
2202
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2203
     registers, at addresses 0x000 and 0x004.
2204
 
2205
          Caution: As noted above, a standard Intel 8042 interface
2206
          would expect to find these registers at locations 0x60 and
2207
          0x64, thus requiring at least a 7-bit bus.
2208
 
2209
`irq = VALUE'
2210 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2211 19 jeremybenn
     value 0.
2212
 
2213
`rxfile = "FILE"'
2214
     `file' specifies a file containing raw key stroke data, which
2215 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2216 19 jeremybenn
     `"kbd_in"'.
2217
 
2218
 
2219

2220
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2221
 
2222
3.4.9 Disc Interface Configuration
2223
----------------------------------
2224
 
2225
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2226
IDE Controller) component implemented at OpenCores, and found in the
2227 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2228 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2229 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2230
which resides on the main OpenRISC Wishbone data bus.
2231 19 jeremybenn
 
2232 385 jeremybenn
     Warning: In the current release of Or1ksim, parsing of the ATA
2233
     section is broken. Users should not configure the disc interface
2234
     in this release.
2235
 
2236 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2237
may appear multiple times, specifying multiple disc controllers.  The
2238 19 jeremybenn
following parameters may be specified.
2239
 
2240
`enabled = 0|1'
2241 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2242 19 jeremybenn
     0, it is disabled.
2243
 
2244
`baseaddr = VALUE'
2245
     Set the base address of the ATA/ATAPI interface's memory mapped
2246 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2247 19 jeremybenn
     sensible value.
2248
 
2249
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2250 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2251
     ATA/ATAPI interface selected (see `dev_id' below), not all
2252
     registers will be available.
2253 19 jeremybenn
 
2254
`irq = VALUE'
2255 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2256 19 jeremybenn
     value 0.
2257
 
2258
`dev_id = 1|2|3'
2259
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2260 82 jeremybenn
     interface to model.  The default value is 1.
2261 19 jeremybenn
 
2262
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2263
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2264
     registers and the `RXD'/`TXD' registers.
2265
 
2266
`rev = VALUE'
2267
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2268 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2269
     be in the range 0-15.  Larger values are truncated with a warning.
2270 346 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2271
     forms bits 24-27.
2272 19 jeremybenn
 
2273
`pio_mode0_t1 = VALUE'
2274
`pio_mode0_t2 = VALUE'
2275
`pio_mode0_t4 = VALUE'
2276
`pio_mode0_teoc = VALUE'
2277
     These parameters specify the timings for use with Programmed
2278 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2279 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2280 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2281 19 jeremybenn
     they do, they will be ignored with a warning.
2282
 
2283
     See the ATA/ATAPI-5 specification for explanations of each of these
2284 82 jeremybenn
     timing parameters.  The default values are:
2285 19 jeremybenn
 
2286
          pio_mode0_t1   =  6
2287
          pio_mode0_t2   = 28
2288
          pio_mode0_t4   =  2
2289
          pio_mode0_teoc = 23
2290
 
2291
`dma_mode0_tm = VALUE'
2292
`dma_mode0_td = VALUE'
2293
`dma_mode0_teoc = VALUE'
2294
     These parameters specify the timings for use with DMA transfers.
2295
     They are specified as the number of clock cycles - 2, rounded up
2296
     to the next highest integer, or zero if that would be negative.
2297 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2298
     ignored with a warning.
2299 19 jeremybenn
 
2300
     See the ATA/ATAPI-5 specification for explanations of each of these
2301 82 jeremybenn
     timing parameters.  The default values are:
2302 19 jeremybenn
 
2303
          dma_mode0_tm   =  4
2304
          dma_mode0_td   = 21
2305
          dma_mode0_teoc = 21
2306
 
2307
 
2308
3.4.9.1 ATA/ATAPI Device Configuration
2309
......................................
2310
 
2311 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2312 19 jeremybenn
device subsection is introduced by
2313
 
2314
     device VALUE
2315
 
2316 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2317
ends with `enddevice'.  Note that if the same device number is
2318
specified more than once, the previous values will be overwritten.
2319
Within the `device' subsection, the following parameters may appear:
2320 19 jeremybenn
 
2321
`type = VALUE'
2322
     VALUEspecifies the type of device: 0 (the default) for "not
2323
     connected", 1 for hard disk simulated in a file and 2 for local
2324
     system hard disk.
2325
 
2326
`file = "FILENAME"'
2327
     `filename' specifies the file to be used for a simulated ATA
2328 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2329 346 jeremybenn
     `"ata_fileN"', where N is the device number.
2330 19 jeremybenn
 
2331
`size = VALUE'
2332
     VALUE specifies the size of a simulated ATA device if the file
2333 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2334 19 jeremybenn
 
2335
`packet = 0|1'
2336 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2337 19 jeremybenn
     default), do not implement the PACKET command feature set.
2338
 
2339
`firmware = "STR"'
2340
     Firmware to report in response to the "Identify Device" command.
2341
     Default `"02207031"'.
2342
 
2343
`heads = VALUE'
2344 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2345 19 jeremybenn
     heads.
2346
 
2347
`sectors = VALUE'
2348 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2349 19 jeremybenn
 
2350
`mwdma = 0|1|2|-1'
2351 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2352 19 jeremybenn
     disable.
2353
 
2354
`pio = 0|1|2|3|4'
2355 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2356 19 jeremybenn
 
2357
 
2358

2359
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2360
 
2361
3.4.10 Generic Peripheral Configuration
2362
---------------------------------------
2363
 
2364
When used as a library (*note Simulator Library: Simulator Library.),
2365
Or1ksim makes provision for any additional peripheral to be implemented
2366 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2367
generates "upcall"s to an external handler.  This interface can support
2368 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2369
for OSCI SystemC (see `http://www.systemc.org').
2370
 
2371
Generic peripheral configuration is described in `section generic'.
2372
This section may appear multiple times, specifying multiple external
2373 82 jeremybenn
peripherals.  The following parameters may be specified.
2374 19 jeremybenn
 
2375
`enabled = 0|1'
2376 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2377 19 jeremybenn
     0, it is disabled.
2378
 
2379
`baseaddr = VALUE'
2380
     Set the base address of the generic peripheral's memory mapped
2381 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2382 19 jeremybenn
     sensible value.
2383
 
2384
     The size of the memory mapped register space is controlled by the
2385
     `size' paramter, described below.
2386
 
2387
`size = VALUE'
2388
     Set the size of the generic peripheral's memory mapped register
2389 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2390 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2391
     parameter `baseaddr' (see above) will be directed to the external
2392
     interface.
2393
 
2394 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2395
     value is zero.  If VALUE is not an exact power of two, accesses to
2396 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2397
     generate a warning, and have no effect (reads will return zero).
2398
 
2399
`name = "STR"'
2400 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2401 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2402 82 jeremybenn
     reporting its status.  The default value is
2403 19 jeremybenn
     `"anonymous external peripheral"'.
2404
 
2405
`byte_enabled = 0|1'
2406
`hw_enabled = 0|1'
2407
`word_enabled = 0|1'
2408
     If 1 (true, the default), these parameters respectively enable the
2409 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2410 19 jeremybenn
     accesses of that width will fail.
2411
 
2412
 
2413

2414
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2415
 
2416
4 Interactive Command Line
2417
**************************
2418
 
2419
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2420 82 jeremybenn
provides the user with an interactive command line.  The commands
2421 19 jeremybenn
available, which may not be abbreviated, are:
2422
 
2423
`q'
2424
     Exit the simulator
2425
 
2426
`r'
2427 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2428 19 jeremybenn
     just executed and next to be executed instructions symbolically
2429
     and the state of the flag in the Supervision Register.
2430
 
2431
`t'
2432
     Execute the next instruction and then display register/instruction
2433
     information as with the `r' command (see above).
2434
 
2435
`run NUM [ hush ]'
2436 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2437 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2438
     above) _unless_ `hush' is specified.
2439
 
2440
`pr REG VALUE'
2441
     Patch register REG with VALUE.
2442
 
2443
`dm FROMADDR [ TOADDR ]'
2444 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2445
     not given, 64 bytes are displayed, starting at FROMADDR.
2446 19 jeremybenn
 
2447
          Caution: The output from this command is broken (a bug).
2448 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2449 19 jeremybenn
          instead of printing out the address at the start of each row,
2450
          it prints the address (of the first of the 16 bytes) before
2451
          _each_ byte.
2452
 
2453
`de FROMADDR [ TOADDR ]'
2454 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2455 19 jeremybenn
     given, 16 instructions are disassembled.
2456
 
2457
     The disassembly is entirely numerical, and gives no symbolic
2458
     information.
2459
 
2460
`pm ADDR VALUE'
2461
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2462
 
2463
`pc VALUE'
2464
     Patch the program counter with VALUE.
2465
 
2466
`cm FROMADDR TOADDR SIZE'
2467
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2468
 
2469
`break ADDR'
2470
     Toggle the breakpoint set at ADDR.
2471
 
2472
`breaks'
2473
     List all set breakpoints
2474
 
2475
`reset'
2476 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2477
     so execution will restart from the reset vector location, 0x100.
2478 19 jeremybenn
 
2479
`hist'
2480
     If saving the execution history has been configured (*note
2481
     Simulator Behavior: Simulator Behavior.), display the execution
2482
     history.
2483
 
2484
`stall'
2485
     Stall the processor, so that control is passed to the debug unit.
2486 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2487 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2488
     debuggers such as GDB.
2489
 
2490
`unstall'
2491 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2492
     This command is useful when debugging the JTAG interface, used by
2493 19 jeremybenn
     debuggers such as GDB.
2494
 
2495
`stats CATEGORY | clear'
2496
     Print the statistics for the given CATEGORY, if available, or
2497 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2498 19 jeremybenn
 
2499
    1
2500
          Miscellaneous statistics: branch predictions (if branch
2501
          predictions are enabled), branch target cache model (if
2502
          enabled), cache (if enbaled), MMU (if enabled) and number of
2503
          addtional load & store cycles.
2504
 
2505
          *Note Configuring the OpenRisc Achitectural Components: Core
2506
          OpenRISC Configuration, for details of how to enable these
2507
          various features.
2508
 
2509
    2
2510 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2511 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2512
 
2513
    3
2514 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2515 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2516
 
2517
    4
2518 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2519 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2520
          Configuration.).
2521
 
2522
    5
2523 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2524 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2525
 
2526
    6
2527 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2528 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2529
 
2530
 
2531
`info'
2532
     Display detailed information about the simulator configuration.
2533
     This is quite a lengthy about, because all MMU TLB information is
2534
     displayed.
2535
 
2536
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2537
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2538 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2539 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2540 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2541 19 jeremybenn
 
2542
     To save to a file, use the redirection function (described after
2543
     this table, below).
2544
 
2545
`dh FROMADDR [ TOADDR ]'
2546
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2547 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2548 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2549
 
2550
     To save to a file, use the redirection function (described after
2551
     this table, below).
2552
 
2553
`setdbch'
2554 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2555 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2556
     channels on the command line.
2557
 
2558
`set SECTION PARAM = VALUE'
2559
     Set the configuration parameter PARA in section SECTION to VALUE.
2560
     *Note Configuration: Configuration, for details of configuration
2561
     parameters and their settings.
2562
 
2563
`debug'
2564 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2565 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2566
     this parameter.
2567
 
2568
          Caution: This is effectively enabling or disabling the debug
2569 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2570 19 jeremybenn
          However using the remote debug interface while the debug unit
2571
          is disabled will lead to undefined behavior and likely crash
2572
          Or1ksim
2573
 
2574
`cuc'
2575
     Enter the the Custom Unit Compiler command prompt (*note CUC
2576
     Configuration: CUC Configuration.).
2577
 
2578
          Caution: The CUC must be properly configured, for this to
2579 82 jeremybenn
          succeed.  In particular a timing file must be available and
2580
          readable.  Otherwise Or1ksim will crash.
2581 19 jeremybenn
 
2582
`help'
2583
     Print out brief information about each command available.
2584
 
2585
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2586 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2587 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2588
     Profiling Utility.).
2589
 
2590
`profile [-vhcq] [-g FILE]'
2591 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2592
     usage as the standalone command (*note Profiling Utility:
2593
     Profiling Utility.).
2594 19 jeremybenn
 
2595
 
2596
For all commands, it is possible to redirect the output to a file, by
2597
using the redirection operator, `>'.
2598
 
2599
     COMMAND > FILENAME
2600
 
2601
This is particularly useful for commands dumping a large amount of
2602
output, such as `dv'.
2603
 
2604
     Caution: Unfortunately there is a serious bug with the redirection
2605 82 jeremybenn
     operator.  It does not return output to standard output after the
2606
     command completes.  Until this bug is fixed, file redirection
2607 19 jeremybenn
     should not be used.
2608
 
2609

2610
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2611
 
2612
5 Verification API (VAPI)
2613
*************************
2614
 
2615
The Verification API (VAPI) provides a TCP/IP interface to allow
2616 82 jeremybenn
components of the simulation to be controlled externally.  The
2617
interface is polled for new requests on each simulated clock cycle.
2618
Components within the simulator may send responses to such requests.
2619 19 jeremybenn
 
2620 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2621
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2622
with a single piece of data (also a 32 bit integer).  On the send side,
2623
it provides for sending a single VAPI ID and data.  However there is no
2624
explicit command-response structure.  Some components just accept
2625
requests (e.g.  to set values), some just generate sends (to report
2626 19 jeremybenn
values), and some do both.
2627
 
2628
Each component has a base ID (32 bit) and its commands will start from
2629 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2630
amongst components.  Request commands will be directed to the component
2631 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2632
 
2633
Thus if there are two components with base IDs of 0x200 and 0x300, and
2634
a request with VAPI ID of 0x203 is received, it will be directed to the
2635
first component as its command #3.
2636
 
2637
The results of VAPI interactions are logged (by default in `vapi.log'
2638
unless an alternative is specified in `section vapi').
2639
 
2640
Currently the following components support VAPI:
2641
 
2642
Debug Unit
2643
     Although the Debug Unit can specify a base VAPI ID, it is not used
2644
     to send commands or receive requests.
2645
 
2646
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2647
     exchanges are logged in the VAPI log file.
2648
 
2649
UART
2650
     If a base VAPI ID is specified, the UART sends details of any
2651
     chars or break characters sent, with dteails of the line control
2652
     register etc encoded in the data packet sent.
2653
 
2654
     This supports a single VAPI command request, but encodes a
2655
     sub-command in the top 8 bits of the associated data.
2656
 
2657
    `0x00'
2658
          This stuffs the least significant 8 bits of the data into the
2659
          serial register of the UART and the next 8 bits into the line
2660
          control register, effectively providing control of the next
2661
          character to be sent or received.
2662
 
2663
    `0x01'
2664
          The divisor latch bytes are set from the least significant 16
2665
          bits of the data.
2666
 
2667
    `0x02'
2668
          The line control register is set from bits 15-8 of the data.
2669
 
2670
    `0x03'
2671
          The UART skew is set from the least significant 16 bits of
2672
          the data
2673
 
2674
    `0x04'
2675
          If the 16th most significant bit of the data is 1, start
2676 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
2677
          are sent or cleared after the number of UART clock divider
2678
          ticks specified by the data (immediately if the data is zero).
2679 19 jeremybenn
 
2680
 
2681
DMA
2682
     Although the DMA unit supports a base VAPI ID in its configuration
2683
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
2684
     implemented.
2685
 
2686
Ethernet
2687 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
2688 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
2689 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
2690 19 jeremybenn
     VAPI requests.
2691
 
2692
    `ETH_VAPI_DATA (0)'
2693
 
2694
    `ETH_VAPI_CTRL (0)'
2695
 
2696
GPIO
2697
     If a base VAPI ID is specified, the GPIO sends out on its base
2698
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
2699
     VAPI ID) any changes in outputs.
2700
 
2701 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
2702 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
2703
     GPIO.
2704
 
2705
    `GPIO_VAPI_DATA (0)'
2706
          Set the next input to the commands data field
2707
 
2708
    `GPIO_VAPI_AUX (1)'
2709
          Set the GPIO auxiliary inputs to the data field
2710
 
2711
    `GPIO_VAPI_CLOCK (2)'
2712
          Add an external GPIO clock trigger of period specified in the
2713
          data field.
2714
 
2715
    `GPIO_VAPI_RGPIO_OE (3)'
2716
          Set the GPIO output enable to the data field
2717
 
2718
    `GPIO_VAPI_RGPIO_INTE (4)'
2719
          Set the next interrupt to the data field
2720
 
2721
    `GPIO_VAPI_RGPIO_PTRIG (5)'
2722
          Set the next trigger to the data field
2723
 
2724
    `GPIO_VAPI_RGPIO_AUX (6)'
2725
          Set the next auxiliary input to the data field
2726
 
2727
    `GPIO_VAPI_RGPIO_CTRL (7)'
2728
          Set th next control input to the data field
2729
 
2730
 
2731
 
2732

2733
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
2734
 
2735
6 A Guide to Or1ksim Internals
2736
******************************
2737
 
2738 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
2739 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
2740 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
2741
Linux manual page for `etags'.  A tag file can be created with:
2742 19 jeremybenn
 
2743
     make tags
2744
 
2745
* Menu:
2746
 
2747
* Coding Conventions::
2748
* Global Data Structures::
2749
* Concepts::
2750
* Internal Debugging::
2751 104 jeremybenn
* Regression Testing::
2752 19 jeremybenn
 
2753

2754
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
2755
 
2756
6.1 Coding Conventions for Or1ksim
2757
==================================
2758
 
2759
This chapter provides some guidelines for coding, to facilitate
2760
extensions to Or1ksim
2761
 
2762
_GNU Coding Standard_
2763
     Code should follow the GNU coding standard for C
2764 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
2765 19 jeremybenn
     through the `indent' program.
2766
 
2767
_`#include' headers_
2768
     All C source code files should include `config.h' before any other
2769
     file.
2770
 
2771
     This should be followed by inclusion of any system headers (but see
2772
     the comments about portability and `port.h' below) and then by any
2773
     Or1ksim package headers.
2774
 
2775
     If `port.h' is required, it should be the first package header to
2776
     be included after the system headers.
2777
 
2778
     All C source code and header files should directly include any
2779 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
2780
     other header having already included it.  The two exceptions are
2781 19 jeremybenn
 
2782
       1. All header files may assume that `config.h' has already been
2783
          included.
2784
 
2785
       2. System headers which impose portability problems should be
2786
          included by using the package header `port.h', rather than
2787 82 jeremybenn
          the system headers themselves.  This is the case for code
2788 19 jeremybenn
          requiring
2789
 
2790
             * `strndup' (from `string.h')
2791
 
2792
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
2793
 
2794
             * `isblank' (from `ctype.h')
2795
 
2796
 
2797
 
2798
_`#include' files once only_
2799
     All include files should be protected by `#ifndef' to ensure their
2800 82 jeremybenn
     definitions are only included once.  For instance a header file
2801 19 jeremybenn
     `X-Y.H' should surround its contents with:
2802
 
2803
          #ifndef X_Y__H
2804
          #define X_Y__H
2805
 
2806
          
2807
 
2808
          #endif  /* X_Y__H */
2809
 
2810
_Avoid `typedef'_
2811
     The GNU coding style for C does not have a clear way to distinguish
2812 82 jeremybenn
     between user type name and user variables.  For this reason
2813 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
2814 82 jeremybenn
     defined types.  This makes the code much easier to read.
2815 19 jeremybenn
 
2816
     There are some `typedef' declarations in the `argtable2' library
2817
     and the ELF and COFF headers, because this code is taken from
2818
     other places.
2819
 
2820
     Within Or1ksim legacy uses of `typedef' have largely been purged,
2821
     except in the Custom Unit Compiler (*note Custom Unit Compiler
2822
     (CUC) Configuration: CUC Configuration.).
2823
 
2824
     The remaining uses of `typedef' occur in two places:
2825
 
2826
        * `port/port.h' defines types to replace those in header files
2827
          that are not available (character functions, string
2828
          duplication, integer types).
2829
 
2830
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
2831
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
2832
          and signed register (`orreg_t') values.
2833
 
2834
 
2835
     Where new types are defined, they should appear in one of these two
2836 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
2837
     `arch.h' should always have the suffix `_h'.
2838 19 jeremybenn
 
2839
_Don't begin names with underscore_
2840
     Names beginning with `_' are intended to be part of the C
2841 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
2842 19 jeremybenn
 
2843
_Keep Non-global top level entities static_
2844
     All top level entities (functions, variables), which are not
2845
     explicitly part of a global interface should be declared static.
2846
     This ensures that unwanted connections are not inadvertently built
2847
     across the program.
2848
 
2849
_Use of `inline'_
2850 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
2851 19 jeremybenn
     out for themselves what is best in this respect.
2852
 
2853
_Initialization_
2854 82 jeremybenn
     All data structures should be explicitly initialized.  In
2855
     particular code should not rely on static data structures being
2856
     initialized to zero.
2857 19 jeremybenn
 
2858
     The rationale is that in future static data structures may become
2859 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
2860 19 jeremybenn
     historically.
2861
 
2862
     A specific case is with new peripherals, which should always
2863
     include a `start' function to pre-initialize all configuration
2864
     parameters to sensible defaults
2865
 
2866
_Configuration Validation_
2867
     All configuration values should be validated, preferably when
2868
     encountered, if not when the `section' is closed, or otherwise at
2869
     run time when the parameter is first used.
2870
 
2871
 
2872

2873
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
2874
 
2875
6.2 Global Data Structures
2876
==========================
2877
 
2878
`config'
2879
     The global variable `config' of type `struct config' holds the
2880
     configuration data for some of the Or1ksim components which are
2881 82 jeremybenn
     always present.  At present the components are:
2882 19 jeremybenn
 
2883
        * The simulator defined in `section sim' (*note Simulator
2884
          Configuration: Simulator Configuration.).
2885
 
2886
        * The Verification API (VAPI) defined  in `section vapi' (*note
2887
          Verification API (VAPI) Configuration: Verification API
2888
          Configuration.).
2889
 
2890
        * The Custom Unit Compiler (CUC), defined in `section cuc'
2891
          (*note Custom Unit Compiler (CUC) Configuration: CUC
2892
          Configuration.).
2893
 
2894
        * The CPU, defined in `section cpu' (*note CPU Configuration:
2895
          CPU Configuration.).
2896
 
2897
        * The data cache (but not the instruction cache), defined in
2898
          `section dc' (*note Cache Configuration: Cache
2899
          Configuration.).
2900
 
2901
        * The power management unit, defined in `section pm' (*note
2902
          Power Management Configuration: Power Management
2903
          Configuration.).
2904
 
2905
        * The programmable interrupt controller, defined in
2906
          `section pic' (*note Interrupt Configuration: Interrupt
2907
          Configuration.).
2908
 
2909
        * Branch prediciton, defined in `section bpb' (*note Branch
2910
          Prediction Configuration: Branch Prediction Configuration.).
2911
 
2912
        * The debug unit, defined in `section debug' (*note Debug
2913
          Interface Configuration: Debug Interface Configuration.).
2914
 
2915
 
2916
     This struct is made of a collection of structs, one for each
2917 82 jeremybenn
     component.  For example the simulator configuration is held in
2918 19 jeremybenn
     `config.sim'.
2919
 
2920
`config'
2921
     This is a linked list of data structures holding configuration data
2922
     for all sections which are not held in the main `config' data
2923 82 jeremybenn
     structure.  In general these are components (such as peripherals
2924
     and memory) which may occur multiple times.  However it also
2925
     handles some architectural components which may occur only once,
2926
     such as the memory management units, the instruction cache, the
2927
     interrupt controller and branch prediction.
2928 19 jeremybenn
 
2929
`runtime'
2930
     The global variable `runtime' of type `struct runtime' holds all
2931 82 jeremybenn
     the runtime information about the simulation.  To access this
2932 19 jeremybenn
     variable, `sim-config.h' must be included.
2933
 
2934
     This struct is itself made of 3 other structs, `cpu' (for CPU run
2935
     time state), `vapi' (for Verification API state) and `cuc' (for
2936
     Custom Unit Compiler state).
2937
 
2938
 
2939

2940
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
2941
 
2942
6.3 Concepts
2943
============
2944
 
2945
_Output Redirection_
2946 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
2947 19 jeremybenn
     should be explicitly written to this stream, or may use the
2948
     `PRINTF' macro, which will write its arguments to this output
2949
     stream.
2950
 
2951
_Reset Hooks_
2952
     Any peripheral may register a routine to be called when the the
2953
     processor is reset by calling `reg_sim_reset', providing a
2954 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
2955 19 jeremybenn
     that function will be called with the data stucture pointer as
2956
     argument.
2957
 
2958
 
2959

2960 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
2961 19 jeremybenn
 
2962
6.4 Internal Debugging
2963
======================
2964
 
2965
The function `debug' is like `printf', but with an extra first
2966 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
2967
the simulator configuration (*note Simulator Behavior: Simulator
2968
Behavior.) is greater than or equal to this value, the remaining
2969
arguments are printed to the current output stream (*note Output
2970
Redirection: Output Redirection.).
2971 19 jeremybenn
 
2972

2973 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
2974
 
2975
6.5 Regression Testing
2976
======================
2977
 
2978
Or1ksim now includes a regression test suite for both standalone and
2979
library usage as described earlier (*note Building and Installing:
2980
Build and Install.).  Running the tests requires that the OpenRISC
2981
toolchain and DejaGNU are both installed.
2982
 
2983
Tests are written using `expect', a derivative of TCL.  Documentation
2984
of DejaGnu, `expect' and TCL are freely available on the Web.  The
2985
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
2986
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
2987
provides a concise introduction.
2988
 
2989
All test code is found in the `testsuite' directory.  The key files and
2990
directories used are as follows.
2991
 
2992
`global-conf.exp'
2993
     This is the global DejaGNU configuration file used to set up
2994
     parameters common to all tests.  If the user has the environment
2995
     varialbe `DEJAGNU' defined, it will be used instead, but this is
2996
     not recommended.
2997
 
2998
`Makefile.am'
2999
     This is the top level `automake' file for the testsuite.  The only
3000
     changes likely to be needed here is additional local cleanup of
3001
     files created by new tests.
3002
 
3003
`README'
3004
     This contains details of all the tests
3005
 
3006
`config'
3007
     This contains DejaGnu board configurations.  Since the tests are
3008
     generally run on a Unix host, this should just contain `Unix.exp'.
3009
 
3010
`lib'
3011
     This contains DejaGnu tool specific configurations.  "Tool" has a
3012
     specific meaning in DejaGNU, referring just to a grouping of
3013
     tests.  In this case there are two such "tools", "or1ksim" and
3014
     "libsim" for tests of the standalone tool and tests of the library.
3015
 
3016
     Corresponding to this, there are two tool specific configuration
3017
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
3018
     procedures for common use among the tests.
3019
 
3020
`libsim.tests'
3021
`or1ksim.tests'
3022
     These are the directories of tests of the Or1ksim library.  They
3023
     also include Or1ksim configuration files and each has a
3024
     `Makefile.am' file.  `Makefile.am' should be updated whenever
3025
     files are added to this directory, to ensure they are included in
3026
     the distribution.
3027
 
3028
`test-code'
3029
     These are all the test programs to be compiled on the host (each
3030
     in its own directory).  In general these are programs to support
3031
     testing of the library, and build various programs linking in the
3032
     library.
3033
 
3034
`test-code'
3035
     These are all the test programs to be compiled with the OpenRISC
3036
     tool chain to run with either standalone Or1ksim or the library.
3037
     This directory includes its own `configure.ac', since it must set
3038
     up a separate tool chain based on the target, not the host.
3039
 
3040
 
3041
To add a new test needs the following steps.
3042
 
3043 346 jeremybenn
   * Put new host C code in its own directory within `test-code'.  Add
3044 104 jeremybenn
     the directory to the existing `Makefile.am' in the `test-code'
3045
     directory and create a `Makefile.am' in the new directory to drive
3046 346 jeremybenn
     building the test program(s).  Don't forget to add the new
3047 104 jeremybenn
     `Makefile' to the top level `configure.ac' so it gets generated.
3048
     Not all tests require code here.
3049
 
3050 346 jeremybenn
   * Put new target C code in its own directory within `test-code-or1k'.
3051
     Once again modify & create `Makefile.am'.  This time modify the
3052
     `configure.ac' in the `test-code-or1k' so the `Makefile' gets
3053
     generated.  The existing programs provide examples to start from,
3054
     including custom linker scripts where needed.
3055 104 jeremybenn
 
3056
   * Add one or more tests and configuration files to the relevant
3057 346 jeremybenn
     "tool" test directory.  Use the existing tests as templates.  They
3058 104 jeremybenn
     make heavy use of the `expect'/TCL procedures in the `config'
3059
     directory to facilitate driving the tests.
3060
 
3061
 
3062

3063 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
3064
 
3065
7 GNU Free Documentation License
3066
********************************
3067
 
3068
                      Version 1.2, November 2002
3069
 
3070
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
3071
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
3072
 
3073
     Everyone is permitted to copy and distribute verbatim copies
3074
     of this license document, but changing it is not allowed.
3075
 
3076
  0. PREAMBLE
3077
 
3078
     The purpose of this License is to make a manual, textbook, or other
3079
     functional and useful document "free" in the sense of freedom: to
3080
     assure everyone the effective freedom to copy and redistribute it,
3081
     with or without modifying it, either commercially or
3082
     noncommercially.  Secondarily, this License preserves for the
3083
     author and publisher a way to get credit for their work, while not
3084
     being considered responsible for modifications made by others.
3085
 
3086
     This License is a kind of "copyleft", which means that derivative
3087
     works of the document must themselves be free in the same sense.
3088
     It complements the GNU General Public License, which is a copyleft
3089
     license designed for free software.
3090
 
3091
     We have designed this License in order to use it for manuals for
3092
     free software, because free software needs free documentation: a
3093
     free program should come with manuals providing the same freedoms
3094
     that the software does.  But this License is not limited to
3095
     software manuals; it can be used for any textual work, regardless
3096
     of subject matter or whether it is published as a printed book.
3097
     We recommend this License principally for works whose purpose is
3098
     instruction or reference.
3099
 
3100
  1. APPLICABILITY AND DEFINITIONS
3101
 
3102
     This License applies to any manual or other work, in any medium,
3103
     that contains a notice placed by the copyright holder saying it
3104
     can be distributed under the terms of this License.  Such a notice
3105
     grants a world-wide, royalty-free license, unlimited in duration,
3106
     to use that work under the conditions stated herein.  The
3107
     "Document", below, refers to any such manual or work.  Any member
3108
     of the public is a licensee, and is addressed as "you".  You
3109
     accept the license if you copy, modify or distribute the work in a
3110
     way requiring permission under copyright law.
3111
 
3112
     A "Modified Version" of the Document means any work containing the
3113
     Document or a portion of it, either copied verbatim, or with
3114
     modifications and/or translated into another language.
3115
 
3116
     A "Secondary Section" is a named appendix or a front-matter section
3117
     of the Document that deals exclusively with the relationship of the
3118
     publishers or authors of the Document to the Document's overall
3119
     subject (or to related matters) and contains nothing that could
3120
     fall directly within that overall subject.  (Thus, if the Document
3121
     is in part a textbook of mathematics, a Secondary Section may not
3122
     explain any mathematics.)  The relationship could be a matter of
3123
     historical connection with the subject or with related matters, or
3124
     of legal, commercial, philosophical, ethical or political position
3125
     regarding them.
3126
 
3127
     The "Invariant Sections" are certain Secondary Sections whose
3128
     titles are designated, as being those of Invariant Sections, in
3129
     the notice that says that the Document is released under this
3130
     License.  If a section does not fit the above definition of
3131
     Secondary then it is not allowed to be designated as Invariant.
3132
     The Document may contain zero Invariant Sections.  If the Document
3133
     does not identify any Invariant Sections then there are none.
3134
 
3135
     The "Cover Texts" are certain short passages of text that are
3136
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3137
     that says that the Document is released under this License.  A
3138
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3139
     be at most 25 words.
3140
 
3141
     A "Transparent" copy of the Document means a machine-readable copy,
3142
     represented in a format whose specification is available to the
3143
     general public, that is suitable for revising the document
3144
     straightforwardly with generic text editors or (for images
3145
     composed of pixels) generic paint programs or (for drawings) some
3146
     widely available drawing editor, and that is suitable for input to
3147
     text formatters or for automatic translation to a variety of
3148
     formats suitable for input to text formatters.  A copy made in an
3149
     otherwise Transparent file format whose markup, or absence of
3150
     markup, has been arranged to thwart or discourage subsequent
3151
     modification by readers is not Transparent.  An image format is
3152
     not Transparent if used for any substantial amount of text.  A
3153
     copy that is not "Transparent" is called "Opaque".
3154
 
3155
     Examples of suitable formats for Transparent copies include plain
3156
     ASCII without markup, Texinfo input format, LaTeX input format,
3157
     SGML or XML using a publicly available DTD, and
3158
     standard-conforming simple HTML, PostScript or PDF designed for
3159
     human modification.  Examples of transparent image formats include
3160
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3161
     can be read and edited only by proprietary word processors, SGML or
3162
     XML for which the DTD and/or processing tools are not generally
3163
     available, and the machine-generated HTML, PostScript or PDF
3164
     produced by some word processors for output purposes only.
3165
 
3166
     The "Title Page" means, for a printed book, the title page itself,
3167
     plus such following pages as are needed to hold, legibly, the
3168
     material this License requires to appear in the title page.  For
3169
     works in formats which do not have any title page as such, "Title
3170
     Page" means the text near the most prominent appearance of the
3171
     work's title, preceding the beginning of the body of the text.
3172
 
3173
     A section "Entitled XYZ" means a named subunit of the Document
3174
     whose title either is precisely XYZ or contains XYZ in parentheses
3175
     following text that translates XYZ in another language.  (Here XYZ
3176
     stands for a specific section name mentioned below, such as
3177
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3178
     To "Preserve the Title" of such a section when you modify the
3179
     Document means that it remains a section "Entitled XYZ" according
3180
     to this definition.
3181
 
3182
     The Document may include Warranty Disclaimers next to the notice
3183
     which states that this License applies to the Document.  These
3184
     Warranty Disclaimers are considered to be included by reference in
3185
     this License, but only as regards disclaiming warranties: any other
3186
     implication that these Warranty Disclaimers may have is void and
3187
     has no effect on the meaning of this License.
3188
 
3189
  2. VERBATIM COPYING
3190
 
3191
     You may copy and distribute the Document in any medium, either
3192
     commercially or noncommercially, provided that this License, the
3193
     copyright notices, and the license notice saying this License
3194
     applies to the Document are reproduced in all copies, and that you
3195
     add no other conditions whatsoever to those of this License.  You
3196
     may not use technical measures to obstruct or control the reading
3197
     or further copying of the copies you make or distribute.  However,
3198
     you may accept compensation in exchange for copies.  If you
3199
     distribute a large enough number of copies you must also follow
3200
     the conditions in section 3.
3201
 
3202
     You may also lend copies, under the same conditions stated above,
3203
     and you may publicly display copies.
3204
 
3205
  3. COPYING IN QUANTITY
3206
 
3207
     If you publish printed copies (or copies in media that commonly
3208
     have printed covers) of the Document, numbering more than 100, and
3209
     the Document's license notice requires Cover Texts, you must
3210
     enclose the copies in covers that carry, clearly and legibly, all
3211
     these Cover Texts: Front-Cover Texts on the front cover, and
3212
     Back-Cover Texts on the back cover.  Both covers must also clearly
3213
     and legibly identify you as the publisher of these copies.  The
3214
     front cover must present the full title with all words of the
3215
     title equally prominent and visible.  You may add other material
3216
     on the covers in addition.  Copying with changes limited to the
3217
     covers, as long as they preserve the title of the Document and
3218
     satisfy these conditions, can be treated as verbatim copying in
3219
     other respects.
3220
 
3221
     If the required texts for either cover are too voluminous to fit
3222
     legibly, you should put the first ones listed (as many as fit
3223
     reasonably) on the actual cover, and continue the rest onto
3224
     adjacent pages.
3225
 
3226
     If you publish or distribute Opaque copies of the Document
3227
     numbering more than 100, you must either include a
3228
     machine-readable Transparent copy along with each Opaque copy, or
3229
     state in or with each Opaque copy a computer-network location from
3230
     which the general network-using public has access to download
3231
     using public-standard network protocols a complete Transparent
3232
     copy of the Document, free of added material.  If you use the
3233
     latter option, you must take reasonably prudent steps, when you
3234
     begin distribution of Opaque copies in quantity, to ensure that
3235
     this Transparent copy will remain thus accessible at the stated
3236
     location until at least one year after the last time you
3237
     distribute an Opaque copy (directly or through your agents or
3238
     retailers) of that edition to the public.
3239
 
3240
     It is requested, but not required, that you contact the authors of
3241
     the Document well before redistributing any large number of
3242
     copies, to give them a chance to provide you with an updated
3243
     version of the Document.
3244
 
3245
  4. MODIFICATIONS
3246
 
3247
     You may copy and distribute a Modified Version of the Document
3248
     under the conditions of sections 2 and 3 above, provided that you
3249
     release the Modified Version under precisely this License, with
3250
     the Modified Version filling the role of the Document, thus
3251
     licensing distribution and modification of the Modified Version to
3252
     whoever possesses a copy of it.  In addition, you must do these
3253
     things in the Modified Version:
3254
 
3255
       A. Use in the Title Page (and on the covers, if any) a title
3256
          distinct from that of the Document, and from those of
3257
          previous versions (which should, if there were any, be listed
3258
          in the History section of the Document).  You may use the
3259
          same title as a previous version if the original publisher of
3260
          that version gives permission.
3261
 
3262
       B. List on the Title Page, as authors, one or more persons or
3263
          entities responsible for authorship of the modifications in
3264
          the Modified Version, together with at least five of the
3265
          principal authors of the Document (all of its principal
3266
          authors, if it has fewer than five), unless they release you
3267
          from this requirement.
3268
 
3269
       C. State on the Title page the name of the publisher of the
3270
          Modified Version, as the publisher.
3271
 
3272
       D. Preserve all the copyright notices of the Document.
3273
 
3274
       E. Add an appropriate copyright notice for your modifications
3275
          adjacent to the other copyright notices.
3276
 
3277
       F. Include, immediately after the copyright notices, a license
3278
          notice giving the public permission to use the Modified
3279
          Version under the terms of this License, in the form shown in
3280
          the Addendum below.
3281
 
3282
       G. Preserve in that license notice the full lists of Invariant
3283
          Sections and required Cover Texts given in the Document's
3284
          license notice.
3285
 
3286
       H. Include an unaltered copy of this License.
3287
 
3288
       I. Preserve the section Entitled "History", Preserve its Title,
3289
          and add to it an item stating at least the title, year, new
3290
          authors, and publisher of the Modified Version as given on
3291
          the Title Page.  If there is no section Entitled "History" in
3292
          the Document, create one stating the title, year, authors,
3293
          and publisher of the Document as given on its Title Page,
3294
          then add an item describing the Modified Version as stated in
3295
          the previous sentence.
3296
 
3297
       J. Preserve the network location, if any, given in the Document
3298
          for public access to a Transparent copy of the Document, and
3299
          likewise the network locations given in the Document for
3300
          previous versions it was based on.  These may be placed in
3301
          the "History" section.  You may omit a network location for a
3302
          work that was published at least four years before the
3303
          Document itself, or if the original publisher of the version
3304
          it refers to gives permission.
3305
 
3306
       K. For any section Entitled "Acknowledgements" or "Dedications",
3307
          Preserve the Title of the section, and preserve in the
3308
          section all the substance and tone of each of the contributor
3309
          acknowledgements and/or dedications given therein.
3310
 
3311
       L. Preserve all the Invariant Sections of the Document,
3312
          unaltered in their text and in their titles.  Section numbers
3313
          or the equivalent are not considered part of the section
3314
          titles.
3315
 
3316
       M. Delete any section Entitled "Endorsements".  Such a section
3317
          may not be included in the Modified Version.
3318
 
3319
       N. Do not retitle any existing section to be Entitled
3320
          "Endorsements" or to conflict in title with any Invariant
3321
          Section.
3322
 
3323
       O. Preserve any Warranty Disclaimers.
3324
 
3325
     If the Modified Version includes new front-matter sections or
3326
     appendices that qualify as Secondary Sections and contain no
3327
     material copied from the Document, you may at your option
3328
     designate some or all of these sections as invariant.  To do this,
3329
     add their titles to the list of Invariant Sections in the Modified
3330
     Version's license notice.  These titles must be distinct from any
3331
     other section titles.
3332
 
3333
     You may add a section Entitled "Endorsements", provided it contains
3334
     nothing but endorsements of your Modified Version by various
3335
     parties--for example, statements of peer review or that the text
3336
     has been approved by an organization as the authoritative
3337
     definition of a standard.
3338
 
3339
     You may add a passage of up to five words as a Front-Cover Text,
3340
     and a passage of up to 25 words as a Back-Cover Text, to the end
3341
     of the list of Cover Texts in the Modified Version.  Only one
3342
     passage of Front-Cover Text and one of Back-Cover Text may be
3343
     added by (or through arrangements made by) any one entity.  If the
3344
     Document already includes a cover text for the same cover,
3345
     previously added by you or by arrangement made by the same entity
3346
     you are acting on behalf of, you may not add another; but you may
3347
     replace the old one, on explicit permission from the previous
3348
     publisher that added the old one.
3349
 
3350
     The author(s) and publisher(s) of the Document do not by this
3351
     License give permission to use their names for publicity for or to
3352
     assert or imply endorsement of any Modified Version.
3353
 
3354
  5. COMBINING DOCUMENTS
3355
 
3356
     You may combine the Document with other documents released under
3357
     this License, under the terms defined in section 4 above for
3358
     modified versions, provided that you include in the combination
3359
     all of the Invariant Sections of all of the original documents,
3360
     unmodified, and list them all as Invariant Sections of your
3361
     combined work in its license notice, and that you preserve all
3362
     their Warranty Disclaimers.
3363
 
3364
     The combined work need only contain one copy of this License, and
3365
     multiple identical Invariant Sections may be replaced with a single
3366
     copy.  If there are multiple Invariant Sections with the same name
3367
     but different contents, make the title of each such section unique
3368
     by adding at the end of it, in parentheses, the name of the
3369
     original author or publisher of that section if known, or else a
3370
     unique number.  Make the same adjustment to the section titles in
3371
     the list of Invariant Sections in the license notice of the
3372
     combined work.
3373
 
3374
     In the combination, you must combine any sections Entitled
3375
     "History" in the various original documents, forming one section
3376
     Entitled "History"; likewise combine any sections Entitled
3377
     "Acknowledgements", and any sections Entitled "Dedications".  You
3378
     must delete all sections Entitled "Endorsements."
3379
 
3380
  6. COLLECTIONS OF DOCUMENTS
3381
 
3382
     You may make a collection consisting of the Document and other
3383
     documents released under this License, and replace the individual
3384
     copies of this License in the various documents with a single copy
3385
     that is included in the collection, provided that you follow the
3386
     rules of this License for verbatim copying of each of the
3387
     documents in all other respects.
3388
 
3389
     You may extract a single document from such a collection, and
3390
     distribute it individually under this License, provided you insert
3391
     a copy of this License into the extracted document, and follow
3392
     this License in all other respects regarding verbatim copying of
3393
     that document.
3394
 
3395
  7. AGGREGATION WITH INDEPENDENT WORKS
3396
 
3397
     A compilation of the Document or its derivatives with other
3398
     separate and independent documents or works, in or on a volume of
3399
     a storage or distribution medium, is called an "aggregate" if the
3400
     copyright resulting from the compilation is not used to limit the
3401
     legal rights of the compilation's users beyond what the individual
3402
     works permit.  When the Document is included in an aggregate, this
3403
     License does not apply to the other works in the aggregate which
3404
     are not themselves derivative works of the Document.
3405
 
3406
     If the Cover Text requirement of section 3 is applicable to these
3407
     copies of the Document, then if the Document is less than one half
3408
     of the entire aggregate, the Document's Cover Texts may be placed
3409
     on covers that bracket the Document within the aggregate, or the
3410
     electronic equivalent of covers if the Document is in electronic
3411
     form.  Otherwise they must appear on printed covers that bracket
3412
     the whole aggregate.
3413
 
3414
  8. TRANSLATION
3415
 
3416
     Translation is considered a kind of modification, so you may
3417
     distribute translations of the Document under the terms of section
3418
     4.  Replacing Invariant Sections with translations requires special
3419
     permission from their copyright holders, but you may include
3420
     translations of some or all Invariant Sections in addition to the
3421
     original versions of these Invariant Sections.  You may include a
3422
     translation of this License, and all the license notices in the
3423
     Document, and any Warranty Disclaimers, provided that you also
3424
     include the original English version of this License and the
3425
     original versions of those notices and disclaimers.  In case of a
3426
     disagreement between the translation and the original version of
3427
     this License or a notice or disclaimer, the original version will
3428
     prevail.
3429
 
3430
     If a section in the Document is Entitled "Acknowledgements",
3431
     "Dedications", or "History", the requirement (section 4) to
3432
     Preserve its Title (section 1) will typically require changing the
3433
     actual title.
3434
 
3435
  9. TERMINATION
3436
 
3437
     You may not copy, modify, sublicense, or distribute the Document
3438
     except as expressly provided for under this License.  Any other
3439
     attempt to copy, modify, sublicense or distribute the Document is
3440
     void, and will automatically terminate your rights under this
3441
     License.  However, parties who have received copies, or rights,
3442
     from you under this License will not have their licenses
3443
     terminated so long as such parties remain in full compliance.
3444
 
3445
 10. FUTURE REVISIONS OF THIS LICENSE
3446
 
3447
     The Free Software Foundation may publish new, revised versions of
3448
     the GNU Free Documentation License from time to time.  Such new
3449
     versions will be similar in spirit to the present version, but may
3450
     differ in detail to address new problems or concerns.  See
3451
     `http://www.gnu.org/copyleft/'.
3452
 
3453
     Each version of the License is given a distinguishing version
3454
     number.  If the Document specifies that a particular numbered
3455
     version of this License "or any later version" applies to it, you
3456
     have the option of following the terms and conditions either of
3457
     that specified version or of any later version that has been
3458
     published (not as a draft) by the Free Software Foundation.  If
3459
     the Document does not specify a version number of this License,
3460
     you may choose any version ever published (not as a draft) by the
3461
     Free Software Foundation.
3462
 
3463
ADDENDUM: How to use this License for your documents
3464
====================================================
3465
 
3466
To use this License in a document you have written, include a copy of
3467
the License in the document and put the following copyright and license
3468
notices just after the title page:
3469
 
3470
       Copyright (C)  YEAR  YOUR NAME.
3471
       Permission is granted to copy, distribute and/or modify this document
3472
       under the terms of the GNU Free Documentation License, Version 1.2
3473
       or any later version published by the Free Software Foundation;
3474
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3475
       Texts.  A copy of the license is included in the section entitled ``GNU
3476
       Free Documentation License''.
3477
 
3478
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3479
replace the "with...Texts." line with this:
3480
 
3481
         with the Invariant Sections being LIST THEIR TITLES, with
3482
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3483
         being LIST.
3484
 
3485
If you have Invariant Sections without Cover Texts, or some other
3486
combination of the three, merge those two alternatives to suit the
3487
situation.
3488
 
3489
If your document contains nontrivial examples of program code, we
3490
recommend releasing these examples in parallel under your choice of
3491
free software license, such as the GNU General Public License, to
3492
permit their use in free software.
3493
 
3494

3495
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3496
 
3497
Index
3498
*****
3499
 
3500
 
3501
* Menu:
3502
3503
* --cumulative:                          Profiling Utility.   (line  26)
3504
* --debug-config:                        Standalone Simulator.
3505 385 jeremybenn
                                                              (line  86)
3506 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3507 127 jeremybenn
                                                              (line 105)
3508 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3509 127 jeremybenn
                                                              (line 118)
3510 124 jeremybenn
* --disable-debug:                       Configuring the Build.
3511 127 jeremybenn
                                                              (line  98)
3512 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3513 104 jeremybenn
                                                              (line  59)
3514 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3515 127 jeremybenn
                                                              (line 133)
3516 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3517 104 jeremybenn
                                                              (line  30)
3518 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3519 127 jeremybenn
                                                              (line  92)
3520
* --disable-unsigned-xori:               Configuring the Build.
3521 104 jeremybenn
                                                              (line  69)
3522 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3523 127 jeremybenn
                                                              (line 104)
3524 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3525 127 jeremybenn
                                                              (line 117)
3526 124 jeremybenn
* --enable-debug:                        Configuring the Build.
3527 127 jeremybenn
                                                              (line  97)
3528 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3529 104 jeremybenn
                                                              (line  58)
3530 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3531 104 jeremybenn
                                                              (line  37)
3532 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3533 385 jeremybenn
                                                              (line 120)
3534 19 jeremybenn
* --enable-ov-flag:                      Configuring the Build.
3535 127 jeremybenn
                                                              (line 132)
3536 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3537 385 jeremybenn
                                                              (line 117)
3538 19 jeremybenn
* --enable-profiling:                    Configuring the Build.
3539 104 jeremybenn
                                                              (line  29)
3540 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3541 127 jeremybenn
                                                              (line  91)
3542
* --enable-unsigned-xori:                Configuring the Build.
3543 104 jeremybenn
                                                              (line  68)
3544 19 jeremybenn
* --file:                                Standalone Simulator.
3545 385 jeremybenn
                                                              (line  44)
3546 19 jeremybenn
* --filename:                            Memory Profiling Utility.
3547
                                                              (line  51)
3548
* --generate:                            Profiling Utility.   (line  34)
3549
* --group:                               Memory Profiling Utility.
3550
                                                              (line  47)
3551
* --help:                                Standalone Simulator.
3552 346 jeremybenn
                                                              (line  21)
3553 19 jeremybenn
* --help (memory profiling utility):     Memory Profiling Utility.
3554
                                                              (line  22)
3555
* --help (profiling utility):            Profiling Utility.   (line  22)
3556
* --interactive:                         Standalone Simulator.
3557 346 jeremybenn
                                                              (line  25)
3558
* --memory:                              Standalone Simulator.
3559 385 jeremybenn
                                                              (line  70)
3560 19 jeremybenn
* --mode:                                Memory Profiling Utility.
3561
                                                              (line  26)
3562
* --nosrv:                               Standalone Simulator.
3563 385 jeremybenn
                                                              (line  52)
3564 346 jeremybenn
* --quiet <1>:                           Profiling Utility.   (line  30)
3565
* --quiet:                               Standalone Simulator.
3566
                                                              (line  29)
3567
* --report-memory-errors:                Standalone Simulator.
3568 385 jeremybenn
                                                              (line  91)
3569 19 jeremybenn
* --srv:                                 Standalone Simulator.
3570 385 jeremybenn
                                                              (line  60)
3571 19 jeremybenn
* --strict-npc:                          Standalone Simulator.
3572 385 jeremybenn
                                                              (line 100)
3573 420 jeremybenn
* --trace:                               Standalone Simulator.
3574
                                                              (line  39)
3575 346 jeremybenn
* --verbose:                             Standalone Simulator.
3576
                                                              (line  33)
3577 19 jeremybenn
* --version:                             Standalone Simulator.
3578 346 jeremybenn
                                                              (line  17)
3579 19 jeremybenn
* --version (memory profiling utility):  Memory Profiling Utility.
3580
                                                              (line  17)
3581
* --version (profiling utility):         Profiling Utility.   (line  17)
3582
* -c:                                    Profiling Utility.   (line  26)
3583
* -d:                                    Standalone Simulator.
3584 385 jeremybenn
                                                              (line  86)
3585 19 jeremybenn
* -f <1>:                                Memory Profiling Utility.
3586
                                                              (line  51)
3587
* -f:                                    Standalone Simulator.
3588 385 jeremybenn
                                                              (line  44)
3589 346 jeremybenn
* -g <1>:                                Memory Profiling Utility.
3590 19 jeremybenn
                                                              (line  47)
3591 346 jeremybenn
* -g:                                    Profiling Utility.   (line  34)
3592 19 jeremybenn
* -h:                                    Standalone Simulator.
3593 346 jeremybenn
                                                              (line  21)
3594 19 jeremybenn
* -h (memory profiling utility):         Memory Profiling Utility.
3595
                                                              (line  22)
3596
* -h (profiling utility):                Profiling Utility.   (line  22)
3597
* -i:                                    Standalone Simulator.
3598 346 jeremybenn
                                                              (line  25)
3599
* -m <1>:                                Memory Profiling Utility.
3600 19 jeremybenn
                                                              (line  26)
3601 346 jeremybenn
* -m:                                    Standalone Simulator.
3602 385 jeremybenn
                                                              (line  70)
3603 346 jeremybenn
* -q <1>:                                Profiling Utility.   (line  30)
3604
* -q:                                    Standalone Simulator.
3605
                                                              (line  29)
3606 420 jeremybenn
* -t:                                    Standalone Simulator.
3607
                                                              (line  39)
3608 346 jeremybenn
* -V:                                    Standalone Simulator.
3609
                                                              (line  33)
3610 19 jeremybenn
* -v:                                    Standalone Simulator.
3611 346 jeremybenn
                                                              (line  17)
3612 19 jeremybenn
* -v (memory profiling utility):         Memory Profiling Utility.
3613
                                                              (line  17)
3614
* -v (profiling utility):                Profiling Utility.   (line  17)
3615
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3616
                                                              (line  49)
3617
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3618
                                                              (line  55)
3619
* 0x02 UART VAPI sub-command (UART verification): Verification API.
3620
                                                              (line  59)
3621
* 0x03 UART VAPI sub-command (UART verification): Verification API.
3622
                                                              (line  62)
3623
* 0x04 UART VAPI sub-command (UART verification): Verification API.
3624
                                                              (line  66)
3625
* 16550 (UART configuration):            UART Configuration.  (line  73)
3626 82 jeremybenn
* all tests enabled:                     Configuring the Build.
3627 127 jeremybenn
                                                              (line 105)
3628 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
3629 127 jeremybenn
                                                              (line  98)
3630 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
3631
                                                              (line   6)
3632
* ATA/ATAPI device configuration:        Disc Interface Configuration.
3633 385 jeremybenn
                                                              (line  92)
3634 19 jeremybenn
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
3635
                                                              (line  32)
3636
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
3637 385 jeremybenn
                                                              (line  26)
3638 19 jeremybenn
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
3639
* baseaddr (Ethernet configuration):     Ethernet Configuration.
3640
                                                              (line  22)
3641
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
3642
                                                              (line  20)
3643
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
3644
                                                              (line  22)
3645
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
3646
* baseaddr (keyboard configuration):     Keyboard Configuration.
3647
                                                              (line  36)
3648
* baseaddr (memory configuration):       Memory Configuration.
3649 418 julius
                                                              (line  94)
3650 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
3651 385 jeremybenn
                                                              (line  55)
3652 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
3653
* baseaddr (VGA configuration):          Display Interface Configuration.
3654
                                                              (line  26)
3655
* blocksize (cache configuration):       Cache Configuration. (line  29)
3656
* BPB configuration:                     Branch Prediction Configuration.
3657
                                                              (line   6)
3658
* branch prediction configuration:       Branch Prediction Configuration.
3659
                                                              (line   6)
3660
* break (Interactive CLI):               Interactive Command Line.
3661
                                                              (line  57)
3662
* breakpoint list (Interactive CLI):     Interactive Command Line.
3663
                                                              (line  60)
3664
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
3665
                                                              (line  57)
3666
* breaks (Interactive CLI):              Interactive Command Line.
3667
                                                              (line  60)
3668
* btic (branch prediction configuration): Branch Prediction Configuration.
3669
                                                              (line  19)
3670
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3671
                                                              (line  48)
3672
* cache configuration:                   Cache Configuration. (line   6)
3673 346 jeremybenn
* calling_convention (CUC configuration): CUC Configuration.  (line  37)
3674 19 jeremybenn
* ce (memory configuration):             Memory Configuration.
3675 418 julius
                                                              (line 124)
3676 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
3677
* channel (UART configuration):          UART Configuration.  (line  29)
3678
* clear breakpoint (Interactive CLI):    Interactive Command Line.
3679
                                                              (line  57)
3680 202 julius
* clkcycle (simulator configuration):    Simulator Behavior.  (line 115)
3681 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
3682
                                                              (line  54)
3683
* command line for Or1ksim standalone use: Standalone Simulator.
3684
                                                              (line   6)
3685
* complex model:                         Configuring the Build.
3686 104 jeremybenn
                                                              (line  37)
3687 19 jeremybenn
* config:                                Global Data Structures.
3688
                                                              (line   7)
3689
* config.bpb:                            Global Data Structures.
3690
                                                              (line  37)
3691
* config.cpu:                            Global Data Structures.
3692
                                                              (line  22)
3693
* config.cuc:                            Global Data Structures.
3694
                                                              (line  18)
3695
* config.dc:                             Global Data Structures.
3696
                                                              (line  25)
3697
* config.debug:                          Global Data Structures.
3698
                                                              (line  40)
3699
* config.pic:                            Global Data Structures.
3700
                                                              (line  33)
3701
* config.pm:                             Global Data Structures.
3702
                                                              (line  29)
3703
* config.sim:                            Global Data Structures.
3704
                                                              (line  11)
3705
* config.vapi:                           Global Data Structures.
3706
                                                              (line  14)
3707
* configuration dynamic structure:       Global Data Structures.
3708
                                                              (line  49)
3709
* configuration file structure:          Configuration File Format.
3710
                                                              (line   6)
3711
* configuration global structure:        Global Data Structures.
3712
                                                              (line   7)
3713
* configuration info (Interactive CLI):  Interactive Command Line.
3714
                                                              (line 119)
3715
* configuration of generic peripherals:  Generic Peripheral Configuration.
3716
                                                              (line   6)
3717
* configuration parameter setting (Interactive CLI): Interactive Command Line.
3718
                                                              (line 146)
3719
* configuring branch prediction:         Branch Prediction Configuration.
3720
                                                              (line   6)
3721
* configuring data & instruction caches: Cache Configuration. (line   6)
3722
* configuring data & instruction MMUs:   Memory Management Configuration.
3723
                                                              (line   6)
3724
* configuring DMA:                       DMA Configuration.   (line   6)
3725
* configuring memory:                    Memory Configuration.
3726
                                                              (line   6)
3727
* configuring Or1ksim:                   Configuration.       (line   6)
3728
* configuring power management:          Power Management Configuration.
3729
                                                              (line   6)
3730
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
3731
                                                              (line   6)
3732
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
3733
* configuring the CPU:                   CPU Configuration.   (line   6)
3734
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
3735
                                                              (line   6)
3736
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
3737
                                                              (line   6)
3738
* configuring the Ethernet interface:    Ethernet Configuration.
3739
                                                              (line   6)
3740
* configuring the frame buffer:          Frame Buffer Configuration.
3741
                                                              (line   6)
3742
* configuring the GPIO:                  GPIO Configuration.  (line   6)
3743
* configuring the interrupt controller:  Interrupt Configuration.
3744
                                                              (line   6)
3745
* configuring the keyboard interface:    Keyboard Configuration.
3746
                                                              (line   6)
3747
* configuring the memory controller:     Memory Controller Configuration.
3748
                                                              (line   6)
3749
* configuring the processor:             CPU Configuration.   (line   6)
3750
* configuring the PS2 interface:         Keyboard Configuration.
3751
                                                              (line   6)
3752
* configuring the UART:                  UART Configuration.  (line   6)
3753
* configuring the Verification API (VAPI): Verification API Configuration.
3754
                                                              (line   6)
3755
* configuring the VGA interface:         Display Interface Configuration.
3756
                                                              (line   6)
3757
* copying memory (Interactive CLI):      Interactive Command Line.
3758
                                                              (line  54)
3759
* CPU configuration:                     CPU Configuration.   (line   6)
3760
* CUC configuration:                     CUC Configuration.   (line   6)
3761
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
3762
                                                              (line 162)
3763
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
3764
* data cache configuration:              Cache Configuration. (line   6)
3765
* data MMU configuration:                Memory Management Configuration.
3766
                                                              (line   6)
3767
* DCGE (power management register):      Power Management Configuration.
3768
                                                              (line  21)
3769
* debug (Interactive CLI):               Interactive Command Line.
3770 346 jeremybenn
                                                              (line 151)
3771 19 jeremybenn
* debug (simulator configuration):       Simulator Behavior.  (line  13)
3772
* debug channel toggle (Interactive CLI): Interactive Command Line.
3773
                                                              (line 141)
3774
* debug interface configuration:         Debug Interface Configuration.
3775
                                                              (line   6)
3776
* debug mode toggle (Interactive CLI):   Interactive Command Line.
3777
                                                              (line 151)
3778
* debug unit configuration:              Debug Interface Configuration.
3779
                                                              (line   6)
3780
* Debug Unit verification (VAPI):        Verification API.    (line  34)
3781
* debugging enabled (Argtable2):         Configuring the Build.
3782 127 jeremybenn
                                                              (line  98)
3783 104 jeremybenn
* DejaGnu board configurations:          Regression Testing.  (line  35)
3784
* DejaGnu configuration:                 Regression Testing.  (line  21)
3785
* DejaGNU tests directories:             Regression Testing.  (line  50)
3786
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
3787 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
3788 418 julius
                                                              (line 144)
3789 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
3790 418 julius
                                                              (line 150)
3791 98 jeremybenn
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
3792 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
3793 385 jeremybenn
                                                              (line  40)
3794 19 jeremybenn
* disassemble (Interactive CLI):         Interactive Command Line.
3795
                                                              (line  41)
3796
* disc interface configuration:          Disc Interface Configuration.
3797
                                                              (line   6)
3798
* disc interface device configuration:   Disc Interface Configuration.
3799 385 jeremybenn
                                                              (line  92)
3800 19 jeremybenn
* display interface configuration:       Display Interface Configuration.
3801
                                                              (line   6)
3802
* displaying memory (Interactive CLI):   Interactive Command Line.
3803
                                                              (line  31)
3804
* displaying registers (Interactive CLI): Interactive Command Line.
3805
                                                              (line  14)
3806
* dm (Interactive CLI):                  Interactive Command Line.
3807
                                                              (line  31)
3808
* dma (Ethernet configuration):          Ethernet Configuration.
3809 346 jeremybenn
                                                              (line  33)
3810 19 jeremybenn
* DMA configuration:                     DMA Configuration.   (line   6)
3811
* DMA verification (VAPI):               Verification API.    (line  73)
3812
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
3813 385 jeremybenn
                                                              (line  74)
3814 19 jeremybenn
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3815 385 jeremybenn
                                                              (line  75)
3816 19 jeremybenn
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
3817 385 jeremybenn
                                                              (line  73)
3818 19 jeremybenn
* DME (power management register):       Power Management Configuration.
3819
                                                              (line  15)
3820
* DMMU configuration:                    Memory Management Configuration.
3821
                                                              (line   6)
3822
* doze mode (power management register): Power Management Configuration.
3823
                                                              (line  15)
3824
* dv (Interactive CLI):                  Interactive Command Line.
3825
                                                              (line 124)
3826
* dynamic clock gating (power management register): Power Management Configuration.
3827
                                                              (line  21)
3828
* dynamic model:                         Configuring the Build.
3829 104 jeremybenn
                                                              (line  37)
3830 19 jeremybenn
* dynamic ports, use of:                 Verification API Configuration.
3831
                                                              (line  23)
3832
* edge_trigger (interrupt controller):   Interrupt Configuration.
3833
                                                              (line  16)
3834 346 jeremybenn
* enable_bursts (CUC configuration):     CUC Configuration.   (line  41)
3835 19 jeremybenn
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
3836 385 jeremybenn
                                                              (line  22)
3837 19 jeremybenn
* enabled (branch prediction configuration): Branch Prediction Configuration.
3838
                                                              (line  15)
3839
* enabled (cache configuration):         Cache Configuration. (line  11)
3840
* enabled (debug interface configuration): Debug Interface Configuration.
3841
                                                              (line  11)
3842
* enabled (DMA configuration):           DMA Configuration.   (line  20)
3843
* enabled (Ethernet configuration):      Ethernet Configuration.
3844
                                                              (line  18)
3845
* enabled (frame buffer configuration):  Frame Buffer Configuration.
3846
                                                              (line  16)
3847
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
3848
                                                              (line  18)
3849
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
3850
* enabled (interrupt controller):        Interrupt Configuration.
3851
                                                              (line  12)
3852
* enabled (keyboard configuration):      Keyboard Configuration.
3853
                                                              (line  32)
3854
* enabled (memory controller configuration): Memory Controller Configuration.
3855 385 jeremybenn
                                                              (line  44)
3856 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
3857
                                                              (line  12)
3858
* enabled (power management configuration): Power Management Configuration.
3859
                                                              (line  35)
3860
* enabled (UART configuration):          UART Configuration.  (line  18)
3861
* enabled (verification API configuration): Verification API Configuration.
3862
                                                              (line  15)
3863
* enabled (VGA configuration):           Display Interface Configuration.
3864
                                                              (line  22)
3865
* enabling Ethernet via socket:          Configuring the Build.
3866 104 jeremybenn
                                                              (line  59)
3867 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
3868
                                                              (line  32)
3869
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
3870
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
3871
* Ethernet configuration:                Ethernet Configuration.
3872
                                                              (line   6)
3873
* Ethernet verification (VAPI):          Verification API.    (line  78)
3874
* Ethernet via socket, enabling:         Configuring the Build.
3875 104 jeremybenn
                                                              (line  59)
3876 127 jeremybenn
* exclusive-OR immediate operand:        Configuring the Build.
3877
                                                              (line  69)
3878 202 julius
* exe_bin_insn_log (simulator configuration): Simulator Behavior.
3879
                                                              (line 103)
3880
* exe_bin_insn_log_file (simulator configuration): Simulator Behavior.
3881
                                                              (line 111)
3882 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
3883
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
3884
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
3885 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
3886 82 jeremybenn
                                                              (line  97)
3887 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
3888 82 jeremybenn
                                                              (line  93)
3889 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
3890 82 jeremybenn
                                                              (line  86)
3891
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
3892 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
3893 82 jeremybenn
                                                              (line  58)
3894 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
3895 82 jeremybenn
                                                              (line  62)
3896 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
3897 82 jeremybenn
                                                              (line  69)
3898 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
3899 82 jeremybenn
                                                              (line  74)
3900 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
3901
                                                              (line  23)
3902
* execution history (Interactive CLI):   Interactive Command Line.
3903
                                                              (line  67)
3904
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
3905 385 jeremybenn
                                                              (line 108)
3906 19 jeremybenn
* file (keyboard configuration):         Keyboard Configuration.
3907
                                                              (line  51)
3908
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
3909 82 jeremybenn
                                                              (line  36)
3910 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
3911
                                                              (line  47)
3912
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
3913 385 jeremybenn
                                                              (line 121)
3914 19 jeremybenn
* flag setting by instructions:          Configuring the Build.
3915 127 jeremybenn
                                                              (line 118)
3916 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
3917
                                                              (line   6)
3918
* generic peripheral configuration:      Generic Peripheral Configuration.
3919
                                                              (line   6)
3920
* GPIO configuration:                    GPIO Configuration.  (line   6)
3921
* GPIO verification (VAPI):              Verification API.    (line  88)
3922
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
3923
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
3924
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
3925
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
3926
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
3927
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
3928
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
3929 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
3930 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
3931 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
3932 385 jeremybenn
                                                              (line 125)
3933 19 jeremybenn
* help (Interactive CLI):                Interactive Command Line.
3934
                                                              (line 170)
3935
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
3936
                                                              (line 133)
3937
* hide_device_id (verification API configuration): Verification API Configuration.
3938
                                                              (line  36)
3939
* hist (Interactive CLI):                Interactive Command Line.
3940
                                                              (line  67)
3941 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
3942 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
3943
                                                              (line  67)
3944
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
3945
                                                              (line  33)
3946
* hitdelay (instruction cache configuration): Cache Configuration.
3947
                                                              (line  38)
3948
* hitdelay (MMU configuration):          Memory Management Configuration.
3949
                                                              (line  51)
3950 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
3951 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3952
                                                              (line  49)
3953
* IMMU configuration:                    Memory Management Configuration.
3954
                                                              (line   6)
3955
* index (memory controller configuration): Memory Controller Configuration.
3956 385 jeremybenn
                                                              (line  77)
3957 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
3958
                                                              (line 119)
3959
* installing Or1ksim:                    Installation.        (line   6)
3960
* instruction cache configuration:       Cache Configuration. (line   6)
3961
* instruction MMU configuration:         Memory Management Configuration.
3962
                                                              (line   6)
3963
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
3964
* instruction profiling utility (Interactive CLI): Interactive Command Line.
3965
                                                              (line 178)
3966
* internal debugging:                    Internal Debugging.  (line   6)
3967
* interrupt controller configuration:    Interrupt Configuration.
3968
                                                              (line   6)
3969
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
3970 385 jeremybenn
                                                              (line  36)
3971 19 jeremybenn
* irq (DMA configuration):               DMA Configuration.   (line  34)
3972
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
3973
* irq (keyboard configuration):          Keyboard Configuration.
3974
                                                              (line  47)
3975
* irq (UART configuration):              UART Configuration.  (line  70)
3976
* irq (VGA configuration):               Display Interface Configuration.
3977
                                                              (line  37)
3978
* jitter (UART configuration):           UART Configuration.  (line  78)
3979
* keyboard configuration:                Keyboard Configuration.
3980
                                                              (line   6)
3981
* library version of Or1ksim:            Simulator Library.   (line   6)
3982
* license for Or1ksim:                   GNU Free Documentation License.
3983
                                                              (line   6)
3984
* list breakpoints (Interactive CLI):    Interactive Command Line.
3985
                                                              (line  60)
3986
* load_hitdelay (data cache configuration): Cache Configuration.
3987
                                                              (line  46)
3988
* load_missdelay (data cache configuration): Cache Configuration.
3989
                                                              (line  50)
3990
* log (memory configuration):            Memory Configuration.
3991 418 julius
                                                              (line 156)
3992 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
3993
                                                              (line  28)
3994 346 jeremybenn
* long:                                  Simulator Library.   (line  95)
3995 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
3996 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
3997 418 julius
                                                              (line 133)
3998 19 jeremybenn
* memory configuration:                  Memory Configuration.
3999
                                                              (line   6)
4000
* memory controller configuration:       Memory Controller Configuration.
4001
                                                              (line   6)
4002
* memory copying (Interactive CLI):      Interactive Command Line.
4003
                                                              (line  54)
4004
* memory display (Interactive CLI):      Interactive Command Line.
4005
                                                              (line  31)
4006
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
4007
                                                              (line 133)
4008
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
4009
                                                              (line 124)
4010
* memory patching (Interactive CLI):     Interactive Command Line.
4011
                                                              (line  48)
4012
* memory profiling end address:          Memory Profiling Utility.
4013
                                                              (line  56)
4014
* memory profiling start address:        Memory Profiling Utility.
4015
                                                              (line  56)
4016
* memory profiling utility (Interactive CLI): Interactive Command Line.
4017
                                                              (line 173)
4018
* memory profiling version of Or1ksim:   Memory Profiling Utility.
4019
                                                              (line   6)
4020
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
4021 346 jeremybenn
* memory_order=exact (CUC configuration): CUC Configuration.  (line  30)
4022 19 jeremybenn
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
4023 346 jeremybenn
* memory_order=strong (CUC configuration): CUC Configuration. (line  27)
4024
* memory_order=weak (CUC configuration): CUC Configuration.   (line  22)
4025 19 jeremybenn
* missdelay (branch prediction configuration): Branch Prediction Configuration.
4026
                                                              (line  37)
4027
* missdelay (instruction cache configuration): Cache Configuration.
4028
                                                              (line  42)
4029
* missdelay (MMU configuration):         Memory Management Configuration.
4030
                                                              (line  55)
4031
* MMU configuration:                     Memory Management Configuration.
4032
                                                              (line   6)
4033 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
4034 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
4035 82 jeremybenn
                                                              (line  34)
4036 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
4037 346 jeremybenn
                                                              (line 173)
4038 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
4039 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
4040 385 jeremybenn
                                                              (line 132)
4041 19 jeremybenn
* name (generic peripheral configuration): Generic Peripheral Configuration.
4042
                                                              (line  42)
4043
* name (memory configuration):           Memory Configuration.
4044 418 julius
                                                              (line 115)
4045 346 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  45)
4046 19 jeremybenn
* nsets (cache configuration):           Cache Configuration. (line  15)
4047
* nsets (MMU configuration):             Memory Management Configuration.
4048
                                                              (line  16)
4049
* nways (cache configuration):           Cache Configuration. (line  22)
4050
* nways (MMU configuration):             Memory Management Configuration.
4051
                                                              (line  22)
4052 346 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  85)
4053
* or1ksim_init:                          Simulator Library.   (line  15)
4054
* or1ksim_interrupt:                     Simulator Library.   (line 100)
4055
* or1ksim_interrupt_clear:               Simulator Library.   (line 118)
4056
* or1ksim_interrupt_set:                 Simulator Library.   (line 109)
4057
* or1ksim_is_le:                         Simulator Library.   (line  90)
4058
* or1ksim_jtag_reset:                    Simulator Library.   (line 127)
4059
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 149)
4060
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 135)
4061
* or1ksim_read_mem:                      Simulator Library.   (line 163)
4062
* or1ksim_read_reg:                      Simulator Library.   (line 199)
4063
* or1ksim_read_spr:                      Simulator Library.   (line 181)
4064
* or1ksim_reset_duration:                Simulator Library.   (line  70)
4065
* or1ksim_run:                           Simulator Library.   (line  59)
4066
* or1ksim_set_stall_state:               Simulator Library.   (line 217)
4067
* or1ksim_set_time_point:                Simulator Library.   (line  81)
4068
* or1ksim_write_mem:                     Simulator Library.   (line 172)
4069
* or1ksim_write_reg:                     Simulator Library.   (line 208)
4070
* or1ksim_write_spr:                     Simulator Library.   (line 190)
4071 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
4072
* overflow flag setting by instructions: Configuring the Build.
4073 127 jeremybenn
                                                              (line 133)
4074 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
4075 385 jeremybenn
                                                              (line 117)
4076 19 jeremybenn
* pagesize (MMU configuration):          Memory Management Configuration.
4077
                                                              (line  27)
4078
* patching memory (Interactive CLI):     Interactive Command Line.
4079
                                                              (line  48)
4080
* patching registers (Interactive CLI):  Interactive Command Line.
4081
                                                              (line  28)
4082
* patching the program counter (Interactive CLI): Interactive Command Line.
4083
                                                              (line  51)
4084
* pattern (memory configuration):        Memory Configuration.
4085 418 julius
                                                              (line  82)
4086 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
4087
                                                              (line  51)
4088
* PIC configuration:                     Interrupt Configuration.
4089
                                                              (line   6)
4090
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
4091 385 jeremybenn
                                                              (line 136)
4092 19 jeremybenn
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
4093 385 jeremybenn
                                                              (line  55)
4094 19 jeremybenn
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
4095 385 jeremybenn
                                                              (line  56)
4096 19 jeremybenn
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
4097 385 jeremybenn
                                                              (line  57)
4098 19 jeremybenn
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4099 385 jeremybenn
                                                              (line  58)
4100 19 jeremybenn
* pm (Interactive CLI):                  Interactive Command Line.
4101
                                                              (line  48)
4102
* PMR - DGCE:                            Power Management Configuration.
4103
                                                              (line  21)
4104
* PMR - DME:                             Power Management Configuration.
4105
                                                              (line  15)
4106
* PMR - SDF:                             Power Management Configuration.
4107
                                                              (line  12)
4108
* PMR - SME:                             Power Management Configuration.
4109
                                                              (line  16)
4110
* PMR - SUME:                            Power Management Configuration.
4111
                                                              (line  24)
4112
* PMU configuration:                     Power Management Configuration.
4113
                                                              (line   6)
4114
* poc (memory controller configuration): Memory Controller Configuration.
4115 385 jeremybenn
                                                              (line  64)
4116 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4117
                                                              (line  23)
4118
* power management configuration:        Power Management Configuration.
4119
                                                              (line   6)
4120
* power management register, DGCE:       Power Management Configuration.
4121
                                                              (line  21)
4122
* power management register, DME:        Power Management Configuration.
4123
                                                              (line  15)
4124
* power management register, SDF:        Power Management Configuration.
4125
                                                              (line  12)
4126
* power management register, SME:        Power Management Configuration.
4127
                                                              (line  16)
4128
* power management register, SUME:       Power Management Configuration.
4129
                                                              (line  24)
4130
* pr (Interactive CLI):                  Interactive Command Line.
4131
                                                              (line  28)
4132
* private ports, use of:                 Verification API Configuration.
4133
                                                              (line  23)
4134
* processor configuration:               CPU Configuration.   (line   6)
4135
* processor stall (Interactive CLI):     Interactive Command Line.
4136
                                                              (line  72)
4137
* processor unstall (Interactive CLI):   Interactive Command Line.
4138
                                                              (line  78)
4139
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4140
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4141
                                                              (line  23)
4142
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4143
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4144
* profiling utility (Interactive CLI):   Interactive Command Line.
4145
                                                              (line 178)
4146
* program counter patching (Interactive CLI): Interactive Command Line.
4147
                                                              (line  51)
4148
* programmable interrupt controller configuration: Interrupt Configuration.
4149
                                                              (line   6)
4150
* PS2 configuration:                     Keyboard Configuration.
4151
                                                              (line   6)
4152
* q (Interactive CLI):                   Interactive Command Line.
4153
                                                              (line  11)
4154
* quitting (Interactive CLI):            Interactive Command Line.
4155
                                                              (line  11)
4156
* r (Interactive CLI):                   Interactive Command Line.
4157
                                                              (line  14)
4158
* random_seed (memory configuration):    Memory Configuration.
4159 418 julius
                                                              (line  72)
4160 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4161 82 jeremybenn
                                                              (line  30)
4162 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4163
                                                              (line  41)
4164
* reg_sim_reset:                         Concepts.            (line  13)
4165
* register display (Interactive CLI):    Interactive Command Line.
4166
                                                              (line  14)
4167
* register over time statistics:         Configuring the Build.
4168 127 jeremybenn
                                                              (line  92)
4169 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4170
                                                              (line  28)
4171 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4172 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4173
                                                              (line  20)
4174 235 jeremybenn
* Remote Serial Protocol, --nosrv:       Standalone Simulator.
4175 385 jeremybenn
                                                              (line  52)
4176 235 jeremybenn
* Remote Serial Protocol, --srv:         Standalone Simulator.
4177 385 jeremybenn
                                                              (line  60)
4178 19 jeremybenn
* reset (Interactive CLI):               Interactive Command Line.
4179
                                                              (line  63)
4180
* reset hooks:                           Concepts.            (line  13)
4181
* reset the simulator (Interactive CLI): Interactive Command Line.
4182
                                                              (line  63)
4183
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4184 385 jeremybenn
                                                              (line  48)
4185 19 jeremybenn
* rev (CPU configuration):               CPU Configuration.   (line  15)
4186
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4187
                                                              (line  20)
4188
* rsp_port (debug interface configuration): Debug Interface Configuration.
4189 235 jeremybenn
                                                              (line  32)
4190 19 jeremybenn
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4191
                                                              (line  46)
4192
* run (Interactive CLI):                 Interactive Command Line.
4193
                                                              (line  23)
4194
* running code (Interactive CLI):        Interactive Command Line.
4195
                                                              (line  23)
4196
* running Or1ksim:                       Usage.               (line   6)
4197
* runtime:                               Global Data Structures.
4198
                                                              (line  58)
4199
* runtime global structure:              Global Data Structures.
4200
                                                              (line  58)
4201
* runtime.cpu:                           Global Data Structures.
4202
                                                              (line  62)
4203
* runtime.cpu.fout:                      Concepts.            (line   7)
4204
* runtime.cuc:                           Global Data Structures.
4205
                                                              (line  62)
4206
* runtime.vapi:                          Global Data Structures.
4207
                                                              (line  62)
4208
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4209
                                                              (line  59)
4210
* rxfile (Ethernet configuration):       Ethernet Configuration.
4211
                                                              (line  68)
4212
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4213
                                                              (line  23)
4214
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4215
                                                              (line  28)
4216 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4217 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4218
                                                              (line  12)
4219
* section ata:                           Disc Interface Configuration.
4220
                                                              (line   6)
4221
* section bpb:                           Branch Prediction Configuration.
4222
                                                              (line   6)
4223
* section cpio:                          GPIO Configuration.  (line   6)
4224
* section cpu:                           CPU Configuration.   (line   6)
4225
* section cuc:                           CUC Configuration.   (line   6)
4226
* section dc:                            Cache Configuration. (line   6)
4227
* section debug:                         Debug Interface Configuration.
4228
                                                              (line   6)
4229
* section dma:                           DMA Configuration.   (line   6)
4230
* section dmmu:                          Memory Management Configuration.
4231
                                                              (line   6)
4232
* section ethernet:                      Ethernet Configuration.
4233
                                                              (line   6)
4234
* section fb:                            Frame Buffer Configuration.
4235
                                                              (line   6)
4236
* section generic:                       Generic Peripheral Configuration.
4237
                                                              (line   6)
4238
* section ic:                            Cache Configuration. (line   6)
4239
* section immu:                          Memory Management Configuration.
4240
                                                              (line   6)
4241
* section kb:                            Keyboard Configuration.
4242
                                                              (line   6)
4243
* section mc:                            Memory Controller Configuration.
4244
                                                              (line   6)
4245
* section memory:                        Memory Configuration.
4246
                                                              (line   6)
4247
* section pic:                           Interrupt Configuration.
4248
                                                              (line   6)
4249
* section pmu:                           Power Management Configuration.
4250
                                                              (line   6)
4251
* section sim:                           Simulator Behavior.  (line   6)
4252
* section uart:                          UART Configuration.  (line   6)
4253
* section vapi:                          Verification API Configuration.
4254
                                                              (line   6)
4255
* section vga:                           Display Interface Configuration.
4256
                                                              (line   6)
4257
* sections:                              Global Data Structures.
4258
                                                              (line  49)
4259
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4260 385 jeremybenn
                                                              (line 129)
4261 19 jeremybenn
* server_port (verification API configuration): Verification API Configuration.
4262
                                                              (line  19)
4263
* set (Interactive CLI):                 Interactive Command Line.
4264
                                                              (line 146)
4265
* set breakpoint (Interactive CLI):      Interactive Command Line.
4266
                                                              (line  57)
4267
* setdbch (Interactive CLI):             Interactive Command Line.
4268
                                                              (line 141)
4269
* simple model:                          Configuring the Build.
4270 104 jeremybenn
                                                              (line  37)
4271 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4272
* simulator configuration info (Interactive CLI): Interactive Command Line.
4273
                                                              (line 119)
4274
* simulator reset (Interactive CLI):     Interactive Command Line.
4275
                                                              (line  63)
4276
* simulator statistics (Interactive CLI): Interactive Command Line.
4277
                                                              (line  83)
4278
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4279 385 jeremybenn
                                                              (line 113)
4280 19 jeremybenn
* size (generic peripheral configuration): Generic Peripheral Configuration.
4281
                                                              (line  30)
4282
* size (memory configuration):           Memory Configuration.
4283 418 julius
                                                              (line  99)
4284 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4285
                                                              (line  16)
4286
* slow down factor (power management register): Power Management Configuration.
4287
                                                              (line  12)
4288
* SME (power management register):       Power Management Configuration.
4289
                                                              (line  16)
4290
* sockif (Ethernet configuration):       Ethernet Configuration.
4291
                                                              (line  83)
4292
* sr (CPU configuration):                CPU Configuration.   (line  53)
4293
* stall (Interactive CLI):               Interactive Command Line.
4294
                                                              (line  72)
4295
* stall the processor (Interactive CLI): Interactive Command Line.
4296
                                                              (line  72)
4297
* statistics, register over time:        Configuring the Build.
4298 127 jeremybenn
                                                              (line  92)
4299 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4300
                                                              (line  83)
4301
* stats (Interactive CLI):               Interactive Command Line.
4302
                                                              (line  83)
4303
* stepping code (Interactive CLI):       Interactive Command Line.
4304
                                                              (line  19)
4305
* store_hitdelay (data cache configuration): Cache Configuration.
4306
                                                              (line  54)
4307
* store_missdelay (data cache configuration): Cache Configuration.
4308
                                                              (line  58)
4309
* SUME (power management register):      Power Management Configuration.
4310
                                                              (line  24)
4311 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4312 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4313
                                                              (line  24)
4314
* t (Interactive CLI):                   Interactive Command Line.
4315
                                                              (line  19)
4316 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4317 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4318
                                                              (line  23)
4319
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4320 235 jeremybenn
                                                              (line  37)
4321 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4322
* test code for target:                  Regression Testing.  (line  63)
4323
* test make file:                        Regression Testing.  (line  27)
4324
* test README:                           Regression Testing.  (line  32)
4325
* testing:                               Regression Testing.  (line   6)
4326 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4327 127 jeremybenn
                                                              (line 105)
4328 346 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  49)
4329 19 jeremybenn
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4330 346 jeremybenn
                                                              (line  49)
4331 19 jeremybenn
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4332
                                                              (line  57)
4333
* toggle debug channels (Interactive CLI): Interactive Command Line.
4334
                                                              (line 141)
4335
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4336
                                                              (line 151)
4337
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4338
                                                              (line  60)
4339
* txfile (Ethernet configuration):       Ethernet Configuration.
4340
                                                              (line  69)
4341
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4342 82 jeremybenn
                                                              (line  36)
4343 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4344
                                                              (line  47)
4345
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4346 385 jeremybenn
                                                              (line 103)
4347 19 jeremybenn
* type (memory configuration):           Memory Configuration.
4348 385 jeremybenn
                                                              (line  37)
4349 418 julius
* type=exitnops (memory configuration):  Memory Configuration.
4350 420 jeremybenn
                                                              (line  66)
4351 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4352 385 jeremybenn
                                                              (line  47)
4353 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4354 385 jeremybenn
                                                              (line  41)
4355 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4356 385 jeremybenn
                                                              (line  51)
4357 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4358 385 jeremybenn
                                                              (line  56)
4359 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4360
* UART I/O from/to a physical serial port: UART Configuration.
4361
                                                              (line  62)
4362
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4363
* UART I/O from/to files:                UART Configuration.  (line  33)
4364
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4365
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4366
* UART verification (VAPI):              Verification API.    (line  41)
4367
* unstall (Interactive CLI):             Interactive Command Line.
4368
                                                              (line  78)
4369
* unstall the processor (Interactive CLI): Interactive Command Line.
4370
                                                              (line  78)
4371
* upr (CPU configuration):               CPU Configuration.   (line  21)
4372
* ustates (cache configuration):         Cache Configuration. (line  33)
4373
* ustates (MMU configuration):           Memory Management Configuration.
4374
                                                              (line  41)
4375
* VAPI configuration:                    Verification API Configuration.
4376
                                                              (line   6)
4377
* VAPI for Debug Unit:                   Verification API.    (line  34)
4378
* VAPI for DMA:                          Verification API.    (line  73)
4379
* VAPI for Ethernet:                     Verification API.    (line  78)
4380
* VAPI for GPIO:                         Verification API.    (line  88)
4381
* VAPI for UART:                         Verification API.    (line  41)
4382
* vapi_id (debug interface configuration): Debug Interface Configuration.
4383 235 jeremybenn
                                                              (line  43)
4384 346 jeremybenn
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4385 19 jeremybenn
                                                              (line  88)
4386 346 jeremybenn
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4387 19 jeremybenn
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4388
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4389
* vapi_log_file (verification API configuration): Verification API Configuration.
4390
                                                              (line  41)
4391
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4392
                                                              (line  41)
4393
* ver (CPU configuration):               CPU Configuration.   (line  15)
4394
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4395
* Verification API configuration:        Verification API Configuration.
4396
                                                              (line   6)
4397
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4398
                                                              (line 124)
4399
* VGA configuration:                     Display Interface Configuration.
4400
 
4401
 
4402
                                                              (line  50)
4403
4404
4405

4406
Tag Table:
4407 420 jeremybenn
Node: Top814
4408
Node: Installation1224
4409
Node: Preparation1471
4410
Node: Configuring the Build1766
4411
Node: Build and Install7910
4412
Node: Known Issues8688
4413
Node: Usage9743
4414
Node: Standalone Simulator9957
4415
Node: Profiling Utility14521
4416
Node: Memory Profiling Utility15431
4417
Node: Simulator Library16796
4418
Node: Configuration26879
4419
Node: Configuration File Format27491
4420
Node: Configuration File Preprocessing27876
4421
Node: Configuration File Syntax28173
4422
Node: Simulator Configuration30958
4423
Node: Simulator Behavior31249
4424
Node: Verification API Configuration35830
4425
Node: CUC Configuration37770
4426
Node: Core OpenRISC Configuration39762
4427
Node: CPU Configuration40264
4428
Node: Memory Configuration44383
4429
Node: Memory Management Configuration51105
4430
Node: Cache Configuration53482
4431
Node: Interrupt Configuration55868
4432
Node: Power Management Configuration56604
4433
Node: Branch Prediction Configuration57881
4434
Node: Debug Interface Configuration59241
4435
Node: Peripheral Configuration61584
4436
Node: Memory Controller Configuration62210
4437
Node: UART Configuration65990
4438
Node: DMA Configuration69509
4439
Node: Ethernet Configuration71376
4440
Node: GPIO Configuration75352
4441
Node: Display Interface Configuration76985
4442
Node: Frame Buffer Configuration79294
4443
Node: Keyboard Configuration81158
4444
Node: Disc Interface Configuration83396
4445
Node: Generic Peripheral Configuration88500
4446
Node: Interactive Command Line90795
4447
Node: Verification API97769
4448
Node: Code Internals102199
4449
Node: Coding Conventions102782
4450
Node: Global Data Structures107209
4451
Node: Concepts109866
4452
Ref: Output Redirection110011
4453
Node: Internal Debugging110550
4454
Node: Regression Testing111074
4455
Node: GNU Free Documentation License114863

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