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This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
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../../doc/or1ksim.texi.
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INFO-DIR-SECTION Embedded development
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START-INFO-DIR-ENTRY
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* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
7
                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 434 jeremybenn
     tar jxf or1ksim-2010-11-26.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
82 19 jeremybenn
default to OpenRISC 1000 32-bit with a warning
83
 
84 434 jeremybenn
     ../or1ksim-2010-11-26/configure --target=or32-uclinux ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 385 jeremybenn
For testing (using `make check'), the `--target' parameter may be
92
specified, to allow the target tool chain to be selected.  If not
93
specified, it will default to `or32-elf', which is the same prefix used
94
with the standard OpenRISC toolchain installation script.
95 19 jeremybenn
 
96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
101 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
`--enable-execution=dynamic'
108
     Or1ksim has developed to improve functionality and performance.
109
     This feature allows three versions of Or1ksim to be built
110
 
111
    `--enable-execution=simple'
112
          Build the original simple interpreting simulator
113
 
114
    `--enable-execution=complex'
115 82 jeremybenn
          Build a more complex interpreting simulator.  Experiments
116
          suggest this is 50% faster than the simple simulator.  This
117
          is the default.
118 19 jeremybenn
 
119
    `--enable-execution=dynamic'
120 82 jeremybenn
          Build a dynamically compiling simulator.  This is the way
121
          many modern ISS are built.  This represents a work in
122
          progress.  Currently Or1ksim will compile, but segfaults if
123
          configured with this option.
124 19 jeremybenn
 
125
 
126
     The default is `--enable-execution=complex'.
127
 
128
`--enable-ethphy'
129
`--disable-ethphy'
130
     If enabled, this option allows the Ethernet to be simulated by
131
     connecting via a socket (the alternative reads and writes, from
132 82 jeremybenn
     and to files).  This must then be configured using the relevant
133
     fields in the `ethernet' section of the configuration file.  *Note
134 19 jeremybenn
     Ethernet Configuration: Ethernet Configuration.
135
 
136
     The default is for this to be disabled.
137
 
138 127 jeremybenn
`--enable-unsigned-xori'
139
`--disable-unsigned-xori'
140 346 jeremybenn
     Historically, `l.xori', has sign extended its operand.  This is
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     inconsistent with the other logical opcodes (`l.andi', `l.ori'),
142
     but in the absence of `l.not', it allows a register to be inverted
143
     in a single instruction using:
144
 
145
          `l.xori  rD,rA,-1'
146
 
147
     This flag causes Or1ksim to treat the immediate operand as
148
     unsigned (i.e to zero-extend rather than sign-extend).
149
 
150
     The default is to sign-extend, so that existing code will continue
151
     to work.
152
 
153
          Caution: The GNU compiler tool chain makes heavy use of this
154
          instruction.  Using unsigned behavior will require the
155
          compiler to be modified accordingly.
156
 
157
          This option is provided for experimentation.  A future
158
          version of OpenRISC may adopt this more consistent behavior
159
          and also provide a `l.not' opcode.
160
 
161 19 jeremybenn
`--enable-range-stats'
162
`--disable-range-stats'
163
     If enabled, this option allows statistics to be collected to
164 82 jeremybenn
     analyse register access over time.  The default is for this to be
165 19 jeremybenn
     disabled.
166
 
167
`--enable-debug'
168
`--disable-debug'
169
     This is a feature of the Argtable2 package used to process
170 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
171
     Argtable2.  It is provided for completeness, but there is no
172
     reason why this feature should ever be needed by any Or1ksim user.
173 19 jeremybenn
 
174 82 jeremybenn
`--enable-all-tests'
175
`--disable-all-tests'
176
     Some of the tests (at the time of writing just one) will not
177
     compile without error.  If enabled with this flag, all test
178
     programs will be compiled with `make check'.
179 19 jeremybenn
 
180 82 jeremybenn
     This flag is intended for those working on the test package, who
181
     wish to get the missing test(s) working.
182
 
183
 
184 112 jeremybenn
A number of configuration flags have been removed since version 0.3.0,
185 346 jeremybenn
because they led to invalid behavior of Or1ksim.  Those removed are:
186 112 jeremybenn
 
187 124 jeremybenn
`--enable-arith-flag'
188
`--disable-arith-flag'
189
     If enabled, this option caused certain instructions to set the flag
190
     (`F' bit) in the supervision register if the result were zero.
191
     The instructions affected by this were `l.add', `l.addc',
192
     `l.addi', `l.and' and `l.andi'.
193
 
194 346 jeremybenn
     If set, this caused incorrect behavior.  Whether or not flags are
195 124 jeremybenn
     set is part of the OpenRISC 1000 architectural specification.  The
196
     only flags which should set this are the "set flag" instructions:
197
     `l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
198
     `l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
199
     `l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
200
     `l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
201
 
202 112 jeremybenn
`--enable-ov-flag'
203
`--disable-ov-flag'
204 124 jeremybenn
     This flag caused certain instructions to set the overflow flag.
205
     If not, those instructions would not set the overflow flat.  The
206
     instructions affected by this were `l.add', `l.addc', `l.addi',
207
     `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
208
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
209
     `l.sub', `l.xor' and `l.xori'.
210 112 jeremybenn
 
211
     This guaranteed incorrect behavior.  The OpenRISC 1000 architecture
212
     specification defines which flags are set by which instructions.
213
 
214
     Within the above list, the arithmetic instructions (`l.add',
215
     `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
216
     `l.sub'), together with `l.addic' which is missed out, set the
217
     overflow flag.  All the others (`l.and', `l.andi', `l.or',
218
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
219
     `l.xor' and `l.xori') do not.
220
 
221
 
222 19 jeremybenn

223
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
224
 
225
1.3 Building and Installing
226
===========================
227
 
228 82 jeremybenn
Build the tool with:
229 19 jeremybenn
 
230
     make all
231 82 jeremybenn
 
232
If you have the OpenRISC tool chain and DejaGNU installed, you can
233
verify the tool as follows (otherwise omit this step):
234
 
235
     make check
236
 
237
Install the tool with:
238
 
239 19 jeremybenn
     make install
240
 
241
This will install the three variations of the Or1ksim tool,
242
`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the
243
Or1ksim library, `libsim', the header file, `or1ksim.h' and this
244
documentation in `info' format.
245
 
246
The documentation may be created and installed in alternative formats
247
(PDF, Postscript, DVI, HTML) with for example:
248
 
249
     make pdf
250
     make install-pdf
251
 
252

253
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
254
 
255
1.4 Known Problems and Issues
256
=============================
257
 
258 346 jeremybenn
Full details of outstanding issues may be found in the `NEWS' file in
259
the main directory of the distribution.  The OpenRISC tracker may be
260
used to see the current state of these issues and to raise new problems
261
and feature requests.  It may be found at bugtracker.
262 19 jeremybenn
 
263 346 jeremybenn
The following issues are long standing and unlikely to be fixed in
264
Or1ksim in the near future.
265
 
266 19 jeremybenn
   * The Supervision Register Little Endian Enable (LEE) bit is
267 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
268 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
269
 
270
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
271 82 jeremybenn
     instances using the library.  This is clearly a problem when
272
     considering multi-core applications.  However it stems from the
273
     original design, and can only be fixed by a complete rewrite.  The
274 19 jeremybenn
     entire source code uses static global constants liberally!
275
 
276
 
277

278
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
279
 
280
2 Usage
281
*******
282
 
283
* Menu:
284
 
285
* Standalone Simulator::
286
* Profiling Utility::
287
* Memory Profiling Utility::
288
* Simulator Library::
289
 
290

291
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
292
 
293
2.1 Standalone Simulator
294
========================
295
 
296
The general form the standalone command is:
297
 
298 385 jeremybenn
     or32-uclinux-sim [-vhiqVt] [-f FILE] [--nosrv] [--srv=[N]]
299 346 jeremybenn
                      [-m ][-d STR]
300 19 jeremybenn
                      [--enable-profile] [--enable-mprofile] [FILE]
301
 
302 82 jeremybenn
Many of the options have both a short and a long form.  For example
303
`-h' or `--help'.
304 19 jeremybenn
 
305
`-v'
306
`--version'
307
     Print out the version and copyright notice for Or1ksim and exit.
308
 
309
`-h'
310
`--help'
311
     Print out help about the command line options and what they mean.
312
 
313 346 jeremybenn
`-i'
314
`--interactive'
315
     After starting, drop into the Or1ksim interactive command shell.
316
 
317
`-q'
318
`--quiet'
319
     Do not generate any information messages, only error messages.
320
 
321
`-V'
322
`--verbose'
323
     Generate extra output messages (equivalent of specifying the
324
     "verbose" option in the simulator configuration section (see *note
325
     Simulator Behavior: Simulator Behavior.).
326
 
327 385 jeremybenn
`-t'
328
`--trace'
329 420 jeremybenn
     Dump instruction just executed and any register/memory location
330
     chaged after each instruction (one line per instruction).
331 385 jeremybenn
 
332 19 jeremybenn
`-f FILE'
333 385 jeremybenn
`--file=FILE'
334 19 jeremybenn
     Read configuration commands from the specified file, looking first
335
     in the current directory, and otherwise in the `$HOME/.or1k'
336 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
337
     in those two locations is used.  Failure to find the file is a
338
     fatal error.  *Note Configuration: Configuration, for detailed
339
     information on configuring Or1ksim.
340 19 jeremybenn
 
341
`--nosrv'
342 235 jeremybenn
     Do not start up the "Remote Serial Protocol" debug server.  This
343
     overrides any setting specified in the configuration file.  This
344
     option may not be specified with `--srv'.  If it is, a rude
345
     message is printed and the `--nosrv' option is ignored.
346 19 jeremybenn
 
347
`--srv'
348
 
349
`--srv=N'
350 235 jeremybenn
     Start up the "Remote Serial Protocol" debug server.  This
351
     overrides any setting specified in the configuration file.  If the
352
     parameter, N, is specified, use that as the TCP/IP port for the
353
     server, otherwise a random value from the private port range
354
     (41920-65535) will be used.  This option may not be specified with
355
     `--nosrv'.  If it is, a rude message is printed and the `--nosrv'
356
     option is ignored.
357 19 jeremybenn
 
358 385 jeremybenn
`-m SIZE'
359 346 jeremybenn
`--memory=SIZE'
360
     Configure a memory block of SIZE bytes, starting at address zero.
361
     The size may be followed by `k', `K', `m', `M', `g', `G', to
362
     indicate kilobytes (2^10 bytes), megabytes (2^20 bytes) and
363
     gigabytes (2^30 bytes).
364
 
365
     This is mainly intended for use when Or1ksim is used without a
366
     configuration file, to allow just the processor and memory to be
367
     set up.  This is the equivalent of specifying a configuration
368
     memory section with `baseaddr = 0' and `size = SIZE' and all other
369
     parameters taking their default value.
370
 
371
     If a configuration file is also used, it should be sure not to
372
     specify an overlapping memory block.
373
 
374 385 jeremybenn
`-d CONFIG_STRING'
375 19 jeremybenn
`--debug-config=CONFIG_STRING'
376 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
377
     use by developers only, and is not covered further here.  See the
378 19 jeremybenn
     source code for more details.
379
 
380 346 jeremybenn
`--report-memory-errors'
381
     By default all exceptions are now handled silently.  If this
382
     option is specified, bus exceptions will be reported with a
383
     message to standard error indicating the address at which the
384
     exception occurred.
385 19 jeremybenn
 
386 346 jeremybenn
     This was the default behaviour up to Or1ksim 0.4.0.  This flag is
387
     provided for those who wish to keep that behavior.
388
 
389 19 jeremybenn
`--strict-npc'
390
     In real hardware, setting the next program counter (NPC, SPR 16),
391 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
392
     until the pipeline refills, reading the NPC will return zero.
393
     This is typically the case when debugging, since the processor is
394 19 jeremybenn
     stalled.
395
 
396
     Historically, Or1ksim has always returned the value of the NPC,
397 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
398
     is used, then Or1ksim will mirror real hardware more accurately.
399
     If the NPC is changed while the processor is stalled, subsequent
400 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
401
 
402
     This is not currently the default behavior, since tools such as
403
     GDB have been implemented assuming the historic Or1ksim behavior.
404
     However at some time in the future it will become the default.
405
 
406
`--enable-profile'
407
     Enable instruction profiling.
408
 
409
`--enable-mprofile'
410
     Enable memory profiling.
411
 
412
 
413

414
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
415
 
416
2.2 Profiling Utility
417
=====================
418
 
419 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
420
It may be invoked as a standalone command, or from the Or1ksim CLI.
421
The general form the standalone command is:
422 19 jeremybenn
 
423
     or32-uclinux-profile [-vhcq] [-g=FILE]
424
 
425 82 jeremybenn
Many of the options have both a short and a long form.  For example
426
`-h' or `--help'.
427 19 jeremybenn
 
428
`-v'
429
`--version'
430
     Print out the version and copyright notice for the Or1ksim
431
     profiling utility and exit.
432
 
433
`-h'
434
`--help'
435
     Print out help about the command line options and what they mean.
436
 
437
`-c'
438
`--cumulative'
439
     Show cumulative sum of cycles in functions
440
 
441
`-q'
442
`--quiet'
443
     Suppress messages
444
 
445
`-g=FILE'
446
`--generate=FILE'
447 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
448 19 jeremybenn
     `sim.profile' is used.
449
 
450
 
451

452
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Simulator Library,  Prev: Profiling Utility,  Up: Usage
453
 
454
2.3 Memory Profiling Utility
455
============================
456
 
457 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
458
be invoked as a standalone command, or from the Or1ksim CLI.  The
459 19 jeremybenn
general form the standalone command is:
460
 
461
     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
462
 
463 82 jeremybenn
Many of the options have both a short and a long form.  For example
464
`-h' or `--help'.
465 19 jeremybenn
 
466
`-v'
467
`--version'
468
     Print out the version and copyright notice for the Or1ksim memory
469
     profiling utility and exit.
470
 
471
`-h'
472
`--help'
473
     Print out help about the command line options and what they mean.
474
 
475
`-m=M'
476
`--mode=M'
477 82 jeremybenn
     Specify the mode out output.  Permitted options are
478 19 jeremybenn
 
479
    `detailed'
480
    `d'
481 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
482 19 jeremybenn
 
483
    `pretty'
484
    `p'
485
          Pretty printed output.
486
 
487
    `access'
488
    `a'
489
          Memory accesses only.
490
 
491
    `width'
492
    `w'
493
          Access width only.
494
 
495
 
496
`-g=N'
497
`--group=N'
498
     Group 2^n bits of successive addresses together.
499
 
500
`-f=FILE'
501
`--filename=FILE'
502 82 jeremybenn
     The data file to analyse.  If not specified, the default,
503 19 jeremybenn
     `sim.profile' is used.
504
 
505
`FROM'
506
`TO'
507
     FROM and TO are respectively the start and end address of the
508
     region of memory to be analysed.
509
 
510
 
511

512
File: or1ksim.info,  Node: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
513
 
514
2.4 Simulator Library
515
=====================
516
 
517
Or1ksim may be used as a static of dynamic library, `libsim.a' or
518 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
519 19 jeremybenn
should be added to the link command.
520
 
521
The header file `or1ksim.h' contains appropriate declarations of the
522 82 jeremybenn
functions exported by the Or1ksim library.  These are:
523 19 jeremybenn
 
524 346 jeremybenn
 -- `or1ksim.h': int or1ksim_init (int ARGC, char *ARGV, void
525 432 jeremybenn
          *CLASS_PTR, int (*UPR)(void *CLASS_PTR, unsigned long int
526
          ADDR, unsigned char MASK[], unsigned char RDATA[], int
527
          DATA_LEN), int (*UPW)(void *CLASS_PTR, unsigned long int
528
          ADDR, unsigned char MASK[], unsigned char WDATA[], int
529
          DATA_LEN))
530 346 jeremybenn
     The initialization function is supplied with a vector of arguments,
531
     which are interpreted as arguments to the standalone version (see
532
     *note Standalone Simulator: Standalone Simulator.), a pointer to
533
     the calling class, CLASS_PTR (since the library may be used from
534
     C++) and two up-call functions, one for reads, UPR, and one for
535
     writes, UPW.
536 19 jeremybenn
 
537
     UPW is called for any write to an address external to the model
538 82 jeremybenn
     (determined by a `generic' section in the configuration file).
539
     UPR is called for any reads to an external address.  The CLASS_PTR
540
     is passed back with these upcalls, allowing the function to
541
     associate the call with the class which originally initialized the
542 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
543
     non-zero otherwise.  At the present time the meaning of non-zero
544
     values is not defined but this may change in the future.
545 19 jeremybenn
 
546 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
547 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
548 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
549
     address, since the upcall function must handle all generic
550
     devices, using the full address for decoding.
551 19 jeremybenn
 
552 346 jeremybenn
     Endianness is not a concern, since Or1ksim is transferring byte
553
     vectors, not multi-byte values.
554 19 jeremybenn
 
555 346 jeremybenn
     The result indicates whether the initialization was successful.
556
     The integer values are available as an `enum or1ksim', with
557
     possible values `OR1KSIM_RC_OK' and `OR1KSIM_RC_BADINIT'.
558 19 jeremybenn
 
559 346 jeremybenn
          Caution: This is a change from versions 0.3.0 and 0.4.0.  It
560
          further simplifies the interface, and makes Or1ksim more
561
          consistent with payload representation in SystemC TLM 2.0.
562
 
563 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
564
          single words (4 bytes), using masks if smaller values are
565
          required.  In this it mimcs the behavior of the WishBone bus.
566
 
567
 
568 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
569
     Run the simulator for the simulated duration specified (in
570 346 jeremybenn
     seconds).  A duration of -1 indicates `run forever'
571 19 jeremybenn
 
572 346 jeremybenn
     The result indicates how the run terminated.  The integer values
573
     are available as an `enum or1ksim', with possible values
574
     `OR1KSIM_RC_OK' (ran for the full duration), `OR1KSIM_RC_BRKPT'
575
     (terminated early due to hitting a breakpoint) and
576
     `OR1KSIM_RC_HALTED' (terminated early due to hitting `l.nop 1').
577 19 jeremybenn
 
578 346 jeremybenn
 
579 19 jeremybenn
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
580
     Change the duration of a run specified in an earlier call to
581 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
582 19 jeremybenn
     realizes it needs to change the duration of the run specified in
583
     the call to `or1ksim_run' that has been interrupted by the upcall.
584
 
585
     The time specified is the amount of time that the run must continue
586
     for (i.e the duration from _now_, not the duration from the
587
     original call to `or1ksim_run').
588
 
589
 
590
 -- `or1ksim.h': void or1ksim_set_time_point ()
591 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
592 19 jeremybenn
 
593
 
594
 -- `or1ksim.h': double or1ksim_get_time_period ()
595
     Return the simulated time (in seconds) that has elapsed since the
596
     last call to `or1ksim_set_time_point'.
597
 
598
 
599
 -- `or1ksim.h': int or1ksim_is_le ()
600
     Return 1 (logical true) if the Or1ksim simulation is
601
     little-endian, 0 otherwise.
602
 
603
 
604
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
605 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
606
     specified in the configuration file.
607 19 jeremybenn
 
608
 
609
 -- `or1ksim.h': void or1ksim_interrupt (int I)
610 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
611 432 jeremybenn
     interrupt must be cleared separately by clearing the corresponding
612
     bit in the PICSR SPR.  Until the interrupt is cleared, any further
613
     interrupts on the same line will be ignored with a warning.  A
614
     warning will be generated and the interrupt request ignored if
615
     level sensitive interrupts have been configured with the
616
     programmable interrupt controller (*note Interrupt Configuration:
617
     Interrupt Configuration.).
618 19 jeremybenn
 
619
 
620
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
621 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
622 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
623 432 jeremybenn
     `or1ksim_interrupt_clear'.  Until the interrupt is cleared, any
624
     further setting of interrupts on the same line will be ignored
625
     with a warning.  A warning will be generated, and the interrupt
626
     request ignored if edge sensitive interrupts have been configured
627
     with the programmable interrupt controller (*note Interrupt
628
     Configuration: Interrupt Configuration.).
629 19 jeremybenn
 
630
 
631
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
632
     Clear a level-triggered interrupt on interrupt line I, which was
633 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
634 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
635
     edge sensitive interrupts have been configured with the
636
     programmable interrupt controller (*note Interrupt Configuration:
637
     Interrupt Configuration.).
638
 
639
 
640 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
641 346 jeremybenn
     Drive a reset sequence through the JTAG interface.  Return the
642 104 jeremybenn
     (model) time taken for this action.  Remember that the JTAG has
643
     its own clock, which can be an order of magnitude slower than the
644
     main clock, so even a reset (5 JTAG cycles) could take 50
645
     processor clock cycles to complete.
646
 
647
 
648 432 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned char *JREG, int
649
          NUM_BITS)
650 104 jeremybenn
     Shift the supplied register through the JTAG instruction register.
651 346 jeremybenn
     Return the (model) time taken for this action.  The register is
652 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
653
     least significant byte.  If the total number of bits is not an
654
     exact number of bytes, then the odd bits are found in the least
655
     significant end of the highest numbered byte.
656
 
657
     For example a 12-bit register would have bits 0-7 in byte 0 and
658
     bits 11-8 in the least significant 4 bits of byte 1.
659
 
660
 
661 432 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned char *JREG, int
662
          NUM_BITS)
663 104 jeremybenn
     Shift the supplied register through the JTAG data register.
664 346 jeremybenn
     Return the (model) time taken for this action.  The register is
665 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
666
     least significant byte.  If the total number of bits is not an
667
     exact number of bytes, then the odd bits are found in the least
668
     significant end of the highest numbered byte.
669
 
670
     For example a 12-bit register would have bits 0-7 in byte 0 and
671
     bits 11-8 in the least significant 4 bits of byte 1.
672
 
673
 
674 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_mem (unsigned long int ADDR, unsigned
675
          char *BUF, int LEN)
676 346 jeremybenn
     Read LEN bytes from ADDR, placing the result in BUF.  Return LEN
677
     on success and 0 on failure.
678
 
679
          Note: This function was added in Or1ksim 0.5.0.
680
 
681
 
682 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_mem (unsigned long int ADDR, const
683
          unsigned char *BUF, int LEN)
684 346 jeremybenn
     Write LEN bytes to ADDR, taking the data from BUF.  Return LEN on
685
     success and 0 on failure.
686
 
687
          Note: This function was added in Or1ksim 0.5.0.
688
 
689
 
690 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_spr (int SPRNUM, unsigned long int
691
          *SPRVAL_PTR)
692 346 jeremybenn
     Read the SPR specified by SPRNUM, placing the result in
693
     SPRVAL_PTR.  Return non-zero on success and 0 on failure.
694
 
695
          Note: This function was added in Or1ksim 0.5.0.
696
 
697
 
698 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_spr (int SPRNUM, unsigned long int
699
          SPRVA)
700 346 jeremybenn
     Write SPRVAL to the SPR specified by SPRNUM.  Return non-zero on
701
     success and 0 on failure.
702
 
703
          Note: This function was added in Or1ksim 0.5.0.
704
 
705
 
706 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_reg (int REGNUM, unsigned long int
707
          *REGVAL_PTR)
708 346 jeremybenn
     Read the general purpose register specified by REGNUM, placing the
709
     result in REGVAL_PTR.  Return non-zero on success and 0 on failure.
710
 
711
          Note: This function was added in Or1ksim 0.5.0.
712
 
713
 
714 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_reg (int REGNUM, unsigned long int
715
          REGVA)
716 346 jeremybenn
     Write REGVAL to the general purpose register specified by REGNUM.
717
     Return non-zero on success and 0 on failure.
718
 
719
          Note: This function was added in Or1ksim 0.5.0.
720
 
721
 
722 432 jeremybenn
 -- `or1ksim.h': void or1ksim_set_stall_state (int STATE)
723 346 jeremybenn
     Set the processor's state according to STATE (1 = stalled, 0 = not
724
     stalled).
725
 
726
          Note: This function was added in Or1ksim 0.5.0.
727
 
728
 
729 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
730
installation directory (as specified with the `--prefix' option to the
731
`configure' script).
732
 
733
For example if the main installation directory is `/opt/or1ksim', the
734 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
735 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
736
(`libsim.so').
737
 
738
To link against the library add the `-lsim' flag when linking and do
739
one of the following:
740
 
741
   * Add the library directory to the `LD_LIBRARY_PATH' environment
742 82 jeremybenn
     variable during execution.  For example:
743 19 jeremybenn
 
744
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
745
 
746
   * Add the library directory to the `LD_RUN_PATH' environment
747 82 jeremybenn
     variable during linking.  For example:
748 19 jeremybenn
 
749
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
750
 
751
   * Use the linker `--rpath' option and specify the library directory
752 82 jeremybenn
     when linking your program.  For example
753 19 jeremybenn
 
754 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
755 19 jeremybenn
 
756
   * Add the library directory to `/etc/ld.so.conf'
757
 
758
 
759

760
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
761
 
762
3 Configuration
763
***************
764
 
765 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
766 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
767 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
768
the default `sim.cfg' is used.  The file is looked for first in the
769 224 jeremybenn
current directory, then in the `$HOME/.or1ksim' directory of the user.
770 19 jeremybenn
 
771
* Menu:
772
 
773
* Configuration File Format::
774
* Simulator Configuration::
775
* Core OpenRISC Configuration::
776
* Peripheral Configuration::
777
 
778

779
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
780
 
781
3.1 Configuration File Format
782
=============================
783
 
784 346 jeremybenn
The configuration file is a plain text file.  A reference example,
785
`sim.cfg', is included in the top level directory of the distribution.
786 19 jeremybenn
 
787
* Menu:
788
 
789
* Configuration File Preprocessing::
790
* Configuration File Syntax::
791
 
792

793
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
794
 
795
3.1.1 Configuration File Preprocessing
796
--------------------------------------
797
 
798 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
799 19 jeremybenn
`/*' and `*/').
800
 
801

802
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
803
 
804
3.1.2 Configuration File Syntax
805
-------------------------------
806
 
807
The configuration file is divided into a series of sections, with the
808
general form:
809
 
810
     section SECTION_NAME
811
 
812
       ...
813
 
814
     end
815
 
816
Sections may also have sub-sections within them (currently only the
817
ATA/ATAPI disc interface uses this).
818
 
819
Within a section, or sub-section are a series of parameter assignments,
820
one per line, withe the general form
821
 
822
       PARAMETER = VALUE
823
 
824
Depending on the parameter, the value may be a named value (an
825
enumeration), an integer (specified in any format acceptable in C) or a
826 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
827
mean "true" or "on" and the value "0" to mean "false" or "off".  An
828 19 jeremybenn
example from a memory section shows each of these
829
 
830
     section memory
831
       type    = random
832
       pattern = 0x00
833
       name    = "FLASH"
834
       ...
835
     end
836
 
837
Many parameters are optional and take reasonable default values if not
838 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
839 19 jeremybenn
parameter in `section memory') _must_ be specified.
840
 
841
Subsections are introduced by a keyword, with a parameter value (no `='
842 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
843 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
844
 
845
     section ata
846
       ...
847
       device 0
848
         type    = 1
849
         file = "FILENAME"
850
         ...
851
       enddevice
852
       ...
853
     end
854
 
855
Some sections (for example `section sim') should appear only once.
856
Others (for example `section memory' may appear multiple times.
857
 
858
Sections may be omitted, _unless they contain parameters which are
859 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
860 19 jeremybenn
is optional (for example whether it has a UART), then that
861 82 jeremybenn
functionality will not be provided.  If the section describes a part of
862 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
863
parameters of that section will take their default values.
864
 
865
All optional parts of the functionality are always described by
866
sections including a `enabled' parameter, which can be set to 0 to
867
ensure that functionality is explicitly omitted.
868
 
869
Even if a section is disabled, all its parameters will be read and
870 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
871
the Or1ksim command line (*note Interactive Command Line: Interactive
872 19 jeremybenn
Command Line.).
873
 
874
     Tip: It generally clearer to have sections describing _all_
875
     components, with omitted functionality explicitly indicated by
876
     setting the `enabled' parameter to 0
877
 
878
The following sections describe the various configuration sections and
879
the parameters which may be set in each.
880
 
881

882
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
883
 
884
3.2 Simulator Configuration
885
===========================
886
 
887
* Menu:
888
 
889
* Simulator Behavior::
890
* Verification API Configuration::
891
* CUC Configuration::
892
 
893

894
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
895
 
896
3.2.1 Simulator Behavior
897
------------------------
898
 
899 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
900
appear only once.  The following parameters may be specified.
901 19 jeremybenn
 
902
`verbose = 0|1'
903 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
904 19 jeremybenn
 
905
`debug = 0-9'
906 82 jeremybenn
 
907
     higher the value the greater the number of messages.  Default 0.
908
     Negative values will be treated as 0 (with a warning).  Values
909
     that are too large will be treated as 9 (with a warning).
910 19 jeremybenn
 
911
`profile = 0|1'
912
     If 1 (true) generate a profiling file using the file specified in
913 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
914 19 jeremybenn
 
915
`prof_file = ``FILENAME'''
916 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
917
     Default `sim.profile'.  For backwards compatibility, the
918
     alternative name `prof_fn' is supported for this parameter, but
919 346 jeremybenn
     deprecated.  Default `sim.profile'.
920 19 jeremybenn
 
921
`mprofile = 0|1'
922
     If 1 (true) generate a memory profiling file using the file
923
     specified in the `mprof_file' parameter or otherwise
924 82 jeremybenn
     `sim.mprofile'.  Default 0.
925 19 jeremybenn
 
926 346 jeremybenn
`mprof_file = ``FILENAME'''
927 19 jeremybenn
     Specifies the file to be used with the `mprofile' parameter.
928 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
929 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
930 346 jeremybenn
     deprecated.  Default `sim.mprofile'.
931 19 jeremybenn
 
932
`history = 0|1'
933 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
934 19 jeremybenn
 
935
          Note: Setting this parameter seriously degrades performance.
936
 
937
          Note: If this execution flow tracking is enabled, then
938
          `dependstats' must be enabled in the CPU configuration
939
          section (*note CPU Configuration: CPU Configuration.).
940
 
941
`exe_log = 0|1'
942 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
943
     file specified in parameter `exe_log_file'.  Default 0.
944 19 jeremybenn
 
945
          Note: Setting this parameter seriously degrades performance.
946
 
947
`exe_log_type = default|hardware|simple|software'
948
     Type of execution log to produce.
949
 
950
    `default'
951 82 jeremybenn
          Produce default output for the execution log.  In the current
952 19 jeremybenn
          implementation this is the equivalent of `hardware'.
953
 
954
    `hardware'
955
          After each instruction execution, log the number of
956
          instructions executed so far, the next instruction to execute
957
          (in hex), the general purpose registers (GPRs), status
958
          register, exception program counter, exception, effective
959
          address register and exception status register.
960
 
961
    `simple'
962
          After each instruction execution, log the number of
963
          instructions executed so far and the next instruction to
964
          execute, symbolically disassembled.
965
 
966
    `software'
967
          After each instruction execution, log the number of
968
          instructions executed so far and the next instruction to
969 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
970 19 jeremybenn
          each operand to the instruction.
971
 
972
 
973 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
974 19 jeremybenn
     insensitive) will be treated as the default with a warning.
975
 
976
          Note: Execution logs can be _very_ big.
977
 
978
`exe_log_start = VALUE'
979 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
980 19 jeremybenn
 
981
`exe_log_end = VALUE'
982 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
983
     once started logging will continue until the simulator exits).
984 19 jeremybenn
 
985
`exe_log_marker = VALUE'
986
     Specifies the number of instructions between printing horizontal
987 82 jeremybenn
     markers.  Default is to produce no markers.
988 19 jeremybenn
 
989
`exe_log_file = FILENAME'
990
     Filename for the execution log filename if `exe_log' is enabled.
991 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
992 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
993
     deprecated.
994
 
995 202 julius
`exe_bin_insn_log = 0|1'
996 346 jeremybenn
     Enable logging of executed instructions to a file in binary format.
997
     This is helpful for off-line dynamic execution analysis.
998 202 julius
 
999 346 jeremybenn
          Note: Execution logs can be _very_ big.  For example, while
1000 220 jeremybenn
          booting the Linux kernel, version 2.6.34, a log file 1.2GB in
1001
          size was generated.
1002 202 julius
 
1003
`exe_bin_insn_log_file = FILENAME'
1004
     Filename for the binary execution log filename if
1005
     `exe_bin_insn_log' is enabled.  Default `exe-insn.bin'.
1006
 
1007 19 jeremybenn
`clkcycle = VALUE[ps|ns|us|ms]'
1008 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
1009
     specified, `ps' is assumed.  Default 4000ps (250MHz).
1010 19 jeremybenn
 
1011
 
1012

1013
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
1014
 
1015
3.2.2 Verification API (VAPI) Configuration
1016
-------------------------------------------
1017
 
1018
The Verification API (VAPI) provides a TCP/IP interface to allow
1019 82 jeremybenn
components of the simulation to be controlled externally.  *Note
1020 19 jeremybenn
Verification API: Verification API, for more details.
1021
 
1022 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
1023
section may appear at most once.  The following parameters may be
1024 19 jeremybenn
specified.
1025
 
1026
`enabled = 0|1'
1027
     If 1 (true), verification API is enabled and its server started.
1028
     If 0 (the default), it is disabled.
1029
 
1030
`server_port = VALUE'
1031
     When VAPI is enabled, communication will be via TCP/IP on the port
1032 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
1033 19 jeremybenn
     The default value is 50000.
1034
 
1035 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
1036 19 jeremybenn
          practice suggests users should adopt port values in the
1037 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
1038 19 jeremybenn
 
1039
`log_enabled = 0|1'
1040
     If 1 (true), all VAPI requests and sent commands will be logged.
1041 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
1042 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
1043
 
1044
          Caution: This can generate a substantial amount of file I/O
1045
          and seriously degrade simulator performance.
1046
 
1047
`hide_device_id = 0|1'
1048 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
1049
     device ID.  This feature (when set to 1) is provided for backwards
1050 19 jeremybenn
     compatibility with an old version of VAPI.
1051
 
1052
`vapi_log_file = "FILENAME"'
1053
     Use `filename' as the file for logged data is logging is enabled
1054 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
1055 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
1056
     supported for this parameter, but deprecated.
1057
 
1058
 
1059

1060
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
1061
 
1062
3.2.3 Custom Unit Compiler (CUC) Configuration
1063
----------------------------------------------
1064
 
1065
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
1066 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
1067
beyond the initial prototype phase.  The configuration parameters are
1068 19 jeremybenn
described here for the record.
1069
 
1070 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
1071
appear at most once.  The following parameters may be specified.
1072 19 jeremybenn
 
1073
`memory_order = none|weak|strong|exact'
1074
     This parameter specifies the memory ordering required:
1075
 
1076
    `memory_order=none'
1077
          Different memory ordering, even if there are dependencies.
1078
          Bursts can be made, width can change.
1079
 
1080 346 jeremybenn
    `memory_order=weak'
1081 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
1082 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
1083
          change.
1084
 
1085 346 jeremybenn
    `memory_order=strong'
1086 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
1087 19 jeremybenn
 
1088 346 jeremybenn
    `memory_order=exact'
1089 19 jeremybenn
          Exactly the same memory ordering and widths.
1090
 
1091
 
1092 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1093 19 jeremybenn
     orderings are ignored with a warning.
1094
 
1095
`calling_convention = 0|1'
1096 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1097 19 jeremybenn
     (the default), they may use other convenitions.
1098
 
1099
`enable_bursts = 0 | 1'
1100 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1101 19 jeremybenn
     not detected.
1102
 
1103
`no_multicycle = 0 | 1'
1104 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1105
     (the default), multicycle logic paths will be generated.
1106 19 jeremybenn
 
1107
`timings_file = "FILENAME"'
1108 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1109
     default value is `"virtex.tim"'.  For backwards compatibility, the
1110 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1111
     deprecated.
1112
 
1113
 
1114

1115
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1116
 
1117
3.3 Configuring the OpenRISC Architectural Components
1118
=====================================================
1119
 
1120
* Menu:
1121
 
1122
* CPU Configuration::
1123
* Memory Configuration::
1124
* Memory Management Configuration::
1125
* Cache Configuration::
1126
* Interrupt Configuration::
1127
* Power Management Configuration::
1128
* Branch Prediction Configuration::
1129
* Debug Interface Configuration::
1130
 
1131

1132
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1133
 
1134
3.3.1 CPU Configuration
1135
-----------------------
1136
 
1137 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1138
appear only once.  At present Or1ksim does not model multi-CPU systems.
1139 19 jeremybenn
The following parameters may be specified.
1140
 
1141
`ver = VALUE'
1142
 
1143
`cfg = VALUE'
1144
 
1145
`rev = VALUE'
1146
     The values are used to form the corresponding fields in the `VR'
1147 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1148 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1149
     and `cfg', 6 bits for `rev').
1150
 
1151
`upr = VALUE'
1152
     Used as the value of the Unit Present Register (UPR) Special
1153 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1154 19 jeremybenn
     i.e.
1155
        * UPR present (0x00000001)
1156
 
1157
        * Data cache present (0x00000002)
1158
 
1159
        * Instruction cache present (0x00000004)
1160
 
1161
        * Data MMY present (0x00000008)
1162
 
1163
        * Instruction MMU present (0x00000010)
1164
 
1165
        * Debug unit present (0x00000040)
1166
 
1167
        * Power management unit present (0x00000100)
1168
 
1169
        * Programmable interrupt controller present (0x00000200)
1170
 
1171
        * Tick timer present (0x00000400)
1172
 
1173
     However, with the exection of the UPR present (0x00000001) and tick
1174
     timer present, the various fields will be modified with the values
1175
     specified in their corresponding configuration sections.
1176
 
1177
`cfgr = VALUE'
1178
     Sets the CPU configuration register (Special Purpose Register 2) to
1179 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1180
     instruction set.  Attempts to set any other value are accepted, but
1181 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1182
 
1183
`sr = VALUE'
1184
     Sets the supervision register Special Purpose Register (SPR 0x11)
1185 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1186 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1187
 
1188 98 jeremybenn
          Note: This is particularly useful when an image is held in
1189
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1190
          so that interrupt vectors are basedf at 0xf0000000, rather
1191
          than 0x0.
1192
 
1193 19 jeremybenn
`superscalar = 0|1'
1194 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1195 19 jeremybenn
     0.
1196
 
1197
     In the current simulator, the only functional effect of superscalar
1198
     mode is to affect the calculation of the number of cycles taken to
1199
     execute an instruction.
1200
 
1201
          Caution: The code for this does not appear to be complete or
1202
          well tested, so users are advised not to use this option.
1203
 
1204
`hazards = 0|1'
1205 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1206
     value is 0.
1207 19 jeremybenn
 
1208
     In the current simulator, the only functional effect is to cause
1209
     logging of hazard waiting information if the CPU is superscalar.
1210
     However nowhere in the simulator is this data actually computed,
1211
     so the net result is probably to have no effect.
1212
 
1213
     if harzards are tracked, current hazards can be displayed using the
1214
     simulator's `r' command.
1215
 
1216
          Caution: The code for this does not appear to be complete or
1217
          well tested, so users are advised not to use this option.
1218
 
1219
`dependstats = 0|1'
1220 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1221
     value 0.
1222 19 jeremybenn
 
1223
     If these values are calculated, the depencies can be displayed
1224
     using the simulator's `stat' command.
1225
 
1226
          Note: This field must be enabled, if execution execution flow
1227
          tracking (field `history') has been requested in the simulator
1228
          configuration section (*note Simulator Behavior: Simulator
1229
          Behavior.).
1230
 
1231
`sbuf_len = VALUE'
1232
     The length of the store buffer is set to VALUE, which must be no
1233 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1234
     warning.  Negative values will be treated as 0 with a warning.
1235
     Use 0 to disable the store buffer.
1236 19 jeremybenn
 
1237
     When the store buffer is active, stores are accumulated and
1238
     committed when I/O is idle.
1239
 
1240 100 julius
`hardfloat = 0|1'
1241 346 jeremybenn
     If 1, hardfloat instructions are enabled.  Default value 0.
1242 19 jeremybenn
 
1243 104 jeremybenn
 
1244 19 jeremybenn

1245
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1246
 
1247
3.3.2 Memory Configuration
1248
--------------------------
1249
 
1250 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1251 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1252 19 jeremybenn
 
1253 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1254 385 jeremybenn
     controller.  If a memory controller is enabled, then appropriate
1255
     initalization code must be provided.  The section describing
1256
     memory controller configuration describes the steps necessary for
1257
     using smaller or larger memory sections (*note Memory Controller
1258
     Configuration: Memory Controller Configuration.).
1259 98 jeremybenn
 
1260 385 jeremybenn
     The "uClibc" startup code initalizes a memory controller, assumed
1261
     to be mapped at 0x93000000.  If a memory controller is _not_
1262
     enabled, then the standard C library code will generate memory
1263
     access errors.  The solution is to declare an additional writable
1264
     memory block, mimicing the memory controller's register bank as
1265
     follows.
1266 98 jeremybenn
 
1267
          section memory
1268
            pattern = 0x00
1269
            type = unknown
1270
            name = "MC shadow"
1271
            baseaddr = 0x93000000
1272
            size     = 0x00000080
1273
            delayr = 2
1274
            delayw = 4
1275
          end
1276
 
1277
 
1278
The following parameters may be specified.
1279
 
1280 418 julius
`type=random|pattern|unknown|zero|exitnops'
1281 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1282 19 jeremybenn
     default value is `unknown'.
1283
 
1284
    `random'
1285 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1286 19 jeremybenn
          random generator may be set using the `random_seed' field in
1287
          this section (see below), thus ensuring the same "random"
1288
          values are used each time.
1289
 
1290
    `pattern'
1291
          Set the memory values to be a pattern value, which is set
1292
          using the `pattern' field in this section (see below).
1293
 
1294
    `unknown'
1295 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1296 240 julius
          This option will yield faster initialization of the
1297 346 jeremybenn
          simulator.  This is the default.
1298 19 jeremybenn
 
1299
    `zero'
1300 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1301 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1302
          such.
1303
 
1304 420 jeremybenn
               Note: As a consequence, if the `pattern' field is
1305
               _subsequently_ specified in this section, the value in
1306
               that field will be used instead of zero to initialize
1307
               the memory.
1308
 
1309 418 julius
    `exitnops'
1310
          Set the memory values to be an instruction used to signal end
1311
          of simulation. This is useful for causing immediate end of
1312
          simulation when PC corruption occurs.
1313
 
1314 19 jeremybenn
 
1315
`random_seed = VALUE'
1316 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1317 19 jeremybenn
     has any effect for memory type `random'.
1318
 
1319
     The default value is -1, which means the seed will be set from a
1320
     call to the `time' function, thus ensuring different random values
1321 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1322 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1323
     values used in any particular run.
1324
 
1325
`pattern = VALUE'
1326 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1327
     default value is 0.  This only has any effect for memory type
1328
     `pattern'.  The least significant 8 bits of this value is used to
1329
     initialize each byte.  More than 8 bits can be specified, but will
1330 19 jeremybenn
     ignored with a warning.
1331
 
1332
          Tip: The default value, is equivalent to setting the memory
1333 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1334 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1335
          and not specifying a value for `pattern'.
1336
 
1337
`baseaddr = VALUE'
1338 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1339 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1340
     The default value is 0.
1341
 
1342
`size = VALUE'
1343 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1344
     be a multiple of 4 (i.e.  word aligned).  The default value is
1345
     1024.
1346 19 jeremybenn
 
1347
          Note: When allocating memory, the simulator will allocate the
1348
          nearest 2^n bytes greater than or equal to VALUE, and will not
1349
          notice memory misses in any part of the memory between VALUE
1350
          and the amount allocated.
1351
 
1352
          As a consequence users are strongly recommended to specify
1353 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1354 19 jeremybenn
          amount of memory is required, it should be specified as
1355
          separate, contiguous blocks, each of which is a power of 2 in
1356
          size.
1357
 
1358
`name = "TEXT"'
1359 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1360
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1361 19 jeremybenn
     `"anonymous memory block"'.
1362
 
1363
          Note: It is not clear that this information is currently ever
1364 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1365 19 jeremybenn
          command of the simulator ignores it.
1366
 
1367
`ce = VALUE'
1368 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1369 19 jeremybenn
     instance should have a unique chip enable index, which should be
1370 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1371 19 jeremybenn
     controller when identifying different memory instances.
1372
 
1373 346 jeremybenn
     There is no requirement to set `ce' if a memory controller is not
1374
     enabled.  The default value is -1 (invalid).
1375 19 jeremybenn
 
1376
`mc = VALUE'
1377 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1378 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1379
     for a memory controller (*note Memory Controller Configuration:
1380
     Memory Controller Configuration.).
1381
 
1382 346 jeremybenn
     There is no requirement to set `mc' if a memory controller is not
1383
     enabled.  Default value is 0, which is also the default value of a
1384 98 jeremybenn
     memory controller `index' field.  This is suitable therefore for
1385
     designs with just one memory controller.
1386 19 jeremybenn
 
1387
`delayr = VALUE'
1388 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1389
     memory does not support reading.  Default value 1.  The simulator
1390 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1391
     count when reading from main memory.
1392
 
1393
`delayw = VALUE'
1394 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1395
     memory does not support writing.  Default value 1.  The simulator
1396 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1397
     count when writing to main memory.
1398
 
1399
`log = "FILE"'
1400
     If specified, `file' names a file for all memory accesses to be
1401 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1402 19 jeremybenn
     that the memory is not logged.
1403
 
1404
 
1405

1406
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1407
 
1408
3.3.3 Memory Management Configuration
1409
-------------------------------------
1410
 
1411
Memory Management Unit (MMU) configuration is described in `section
1412
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1413 82 jeremybenn
Each section should appear at most once.  The following parameters may
1414 19 jeremybenn
be specified.
1415
 
1416
`enabled = 0|1'
1417
     If 1 (true), the data or instruction (as appropriate) MMU is
1418 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1419 19 jeremybenn
 
1420
`nsets = VALUE'
1421
     Sets the number of data or instruction (as appropriate) TLB sets to
1422 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1423
     which do not fit these criteria are ignored with a warning.  The
1424 19 jeremybenn
     default value is 1.
1425
 
1426
`nways = VALUE'
1427
     Sets the number of data or instruction (as appropriate) TLB ways to
1428 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1429
     this range are ignored with a warning.  The default value is 1.
1430 19 jeremybenn
 
1431
`pagesize = VALUE'
1432
     The data or instruction (as appropriate) MMU page size is set to
1433 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1434
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1435 19 jeremybenn
 
1436
`entrysize = VALUE'
1437
     The data or instruction (as appropriate) MMU entry size is set to
1438 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1439
     of 2 are ignored with a warning.  The default value is 1.
1440 19 jeremybenn
 
1441
          Note: Or1ksim does not appear to use the `entrysize' parameter
1442 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1443 19 jeremybenn
          not seem to matter.
1444
 
1445
`ustates = VALUE'
1446
     The number of instruction usage states for the data or instruction
1447
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1448 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1449 19 jeremybenn
     value is 2.
1450
 
1451
          Note: Or1ksim does not appear to use the `ustates' parameter
1452 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1453 19 jeremybenn
          not seem to matter.
1454
 
1455
`hitdelay = VALUE'
1456
     Set the number of cycles a data or instruction (as appropriate) MMU
1457 82 jeremybenn
     hit costs.  Default value 1.
1458 19 jeremybenn
 
1459
`missdelay = VALUE'
1460
     Set the number of cycles a data or instruction (as appropriate) MMU
1461 82 jeremybenn
     miss costs.  Default value 1.
1462 19 jeremybenn
 
1463
 
1464

1465
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1466
 
1467
3.3.4 Cache Configuration
1468
-------------------------
1469
 
1470
Cache configuration is described in `section dc' (for the data cache)
1471 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1472
appear at most once.  The following parameters may be specified.
1473 19 jeremybenn
 
1474
`enabled = 0|1'
1475
     If 1 (true), the data or instruction (as appropriate) cache is
1476 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1477 19 jeremybenn
 
1478
`nsets = VALUE'
1479
     Sets the number of data or instruction (as appropriate) cache sets
1480
     to VALUE, which must be a power of two, not exceeding
1481
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1482 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1483
     both defined in the code to be 1024).  The default value is 1.
1484 19 jeremybenn
 
1485
`nways = VALUE'
1486
     Sets the number of data or instruction (as appropriate) cache ways
1487
     to VALUE, which must be a power of two, not exceeding
1488
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1489 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1490
     both defined in the code to be 32).  The default value is 1.
1491 19 jeremybenn
 
1492
`blocksize = VALUE'
1493
     The data or instruction (as appropriate) cache block size is set to
1494 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1495 19 jeremybenn
 
1496
`ustates = VALUE'
1497
     The number of instruction usage states for the data or instruction
1498
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1499
     The default value is 2.
1500
 
1501
`hitdelay = VALUE'
1502 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1503
     cache hit costs.  Default value 1.
1504 19 jeremybenn
 
1505
`missdelay = VALUE'
1506 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1507
     cache miss costs.  Default value 1.
1508 19 jeremybenn
 
1509
`load_hitdelay = VALUE'
1510 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1511
     costs.  Default value 2.
1512 19 jeremybenn
 
1513
`load_missdelay = VALUE'
1514 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1515
     miss costs.  Default value 2.
1516 19 jeremybenn
 
1517
`store_hitdelay = VALUE'
1518 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1519
     costs.  Default value 0.
1520 19 jeremybenn
 
1521
`store_missdelay = VALUE'
1522 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1523
     miss costs.  Default value 0.
1524 19 jeremybenn
 
1525
 
1526

1527
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1528
 
1529
3.3.5 Interrupt Configuration
1530
-----------------------------
1531
 
1532
Programmable Interrupt Controller (PIC) configuration is described in
1533 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1534
mechanism for handling multiple interrupt controllers.  The following
1535 19 jeremybenn
parameters may be specified.
1536
 
1537
`enabled = 0|1'
1538 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1539
 
1540 19 jeremybenn
 
1541
`edge_trigger = 0|1'
1542
     If 1 (true, the default), the programmable interrupt controller is
1543 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1544 19 jeremybenn
 
1545 432 jeremybenn
     The library interface (*note Simulator Library: Simulator Library.)
1546
     provides different functions for setting the different types of
1547
     interrupt, and a function to clear level sensitive interrupts. Edge
1548
     sensitive interrupts must be cleared by clearing the corresponding
1549
     bit in the PICSR SPR.
1550 19 jeremybenn
 
1551 432 jeremybenn
     Internal functions to set and clear interrupts are also provided
1552
     for peripherals implemented within Or1ksim. *Note Interrupts
1553
     Internal: Interrupts Internal for more details.
1554 430 julius
 
1555 432 jeremybenn
`use_nmi = 0|1'
1556
     If 1 (true, the default), interrupt lines 0 and 1 are
1557
     non-maskable. In other words the least significant 2 bits of the
1558
     PICMR SPR are hard-wired to 1.  If 0 (false), all interrupt lines
1559
     are treated as equivalent.
1560 430 julius
 
1561 432 jeremybenn
          Note: These are not non-maskable in the true sense that they
1562
          will pre-empt other interrupts.  Rather they can never be
1563
          masked out using the PICMR register. It is up the interrupt
1564
          exception handler to give these interrupt lines priority, and
1565
          indeed to decide on the priority order in general.
1566 430 julius
 
1567 432 jeremybenn
 
1568 19 jeremybenn

1569
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1570
 
1571
3.3.6 Power Management Configuration
1572
------------------------------------
1573
 
1574 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1575 19 jeremybenn
(which only happens when the power management unit is enabled) of
1576
setting the different bits in the power management Special Purpose
1577
Register (PMR, SPR 0x4000) is
1578
 
1579
`SDF (bit mask 0x0000000f)'
1580
     No effect - these bits are ignored
1581
 
1582
`DME (bit mask 0x00000010)'
1583
`SME (bit mask 0x00000020)'
1584
     Both these bits cause the processor to stop executing
1585 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1586 19 jeremybenn
     VAPI etc) carry on as normal.
1587
 
1588
`DCGE (bit mask 0x00000004)'
1589
     No effect - this bit is ignored
1590
 
1591
`SUME (bit mask 0x00000008)'
1592
     Enabling this bit causes a message to be printed, advising that the
1593
     processor is suspending and the simulator exits.
1594
 
1595
 
1596
On reset all bits are cleared.
1597
 
1598 82 jeremybenn
Power management configuration is described in `section pm'.  This
1599
section may appear at most once.  The following parameter may be
1600 19 jeremybenn
specified.
1601
 
1602
`enabled = 0|1'
1603 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1604
     is disabled.
1605 19 jeremybenn
 
1606
 
1607

1608
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1609
 
1610
3.3.7 Branch Prediction Configuration
1611
-------------------------------------
1612
 
1613
From examining the code base, it seems the branch prediction function
1614 82 jeremybenn
is not fully implemented.  At present the functionality seems
1615
restricted to collection of statistics.
1616 19 jeremybenn
 
1617 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1618
section may appear at most once.  The following parameters may be
1619 19 jeremybenn
specified.
1620
 
1621
`enabled = 0|1'
1622 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1623 19 jeremybenn
     is disabled.
1624
 
1625
`btic = 0|1'
1626
     If 1 (true), the branch target instruction cache model is enabled.
1627
     If 0 (the default), it is disabled.
1628
 
1629
`sbp_bf_fwd = 0|1'
1630 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1631 19 jeremybenn
 
1632
     instruction.
1633
 
1634
`sbp_bnf_fwd = 0|1'
1635 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1636
     If 0 (the default), do not use forward prediction for this
1637 19 jeremybenn
     instruction.
1638
 
1639
`hitdelay = VALUE'
1640 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1641 19 jeremybenn
     value 0.
1642
 
1643
`missdelay = VALUE'
1644 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1645 19 jeremybenn
     value 0.
1646
 
1647
 
1648

1649
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1650
 
1651
3.3.8 Debug Interface Configuration
1652
-----------------------------------
1653
 
1654
The debug unit and debug interface configuration is described in
1655 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1656 19 jeremybenn
parameters may be specified.
1657
 
1658
`enabled = 0|1'
1659 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1660 19 jeremybenn
     disabled.
1661
 
1662
          Note: This enables the functionality of the debug unit (its
1663 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1664
          external interface to the debug unit.  For that, see
1665 235 jeremybenn
          `rsp_enabled' below.
1666 19 jeremybenn
 
1667
`rsp_enabled = 0|1'
1668
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1669
     provding an interface to an external GNU debugger, using the port
1670
     specified in the `rsp_port' field (see below), or the
1671 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1672 19 jeremybenn
     not started, and no external interface is provided.
1673
 
1674
     For more detailed information on the interface to the GNU Debugger
1675
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1676
     Practical Experience with the OpenRISC 1000 Architecture', by
1677
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1678
 
1679
`rsp_port = VALUE'
1680
     VALUE specifies the port to be used for the GDB "Remote Serial
1681 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1682
     51000.  If the value 0 is specified, Or1ksim will instead look for
1683 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1684
 
1685
          Tip: There is no registered port for Or1ksim "Remote Serial
1686 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1687
          users should adopt port values in the "Dynamic" or "Private"
1688
          port range, i.e.  49152-65535.
1689 19 jeremybenn
 
1690
`vapi_id = VALUE'
1691
     VALUE specifies the value of the Verification API (VAPI) base
1692 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1693 19 jeremybenn
     Verification API, for more details.
1694
 
1695
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1696
     JTAG protocol transactions will be logged to the VAPI log file, if
1697 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
1698
     the debug unit.  No VAPI commands are sent, nor requests handled.
1699 19 jeremybenn
 
1700
 
1701

1702
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
1703
 
1704
3.4 Configuring Memory Mapped Peripherals
1705
=========================================
1706
 
1707 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1708 19 jeremybenn
(unlike other components) by default they are enabled.
1709
 
1710
* Menu:
1711
 
1712
* Memory Controller Configuration::
1713
* UART Configuration::
1714
* DMA Configuration::
1715
* Ethernet Configuration::
1716
* GPIO Configuration::
1717
* Display Interface Configuration::
1718
* Frame Buffer Configuration::
1719
* Keyboard Configuration::
1720
* Disc Interface Configuration::
1721
* Generic Peripheral Configuration::
1722
 
1723

1724
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
1725
 
1726
3.4.1 Memory Controller Configuration
1727
-------------------------------------
1728
 
1729
The memory controller used in Or1ksim is the component implemented at
1730 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
1731 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
1732 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1733
memory mapped component, which resides on the main OpenRISC Wishbone
1734
data bus.
1735 19 jeremybenn
 
1736 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
1737 19 jeremybenn
section may appear multiple times, specifying multiple memory
1738 98 jeremybenn
controllers.
1739 19 jeremybenn
 
1740 385 jeremybenn
     Warning: There are known to be problems with the current memory
1741
     controller, which currently is not included in the regression test
1742
     suite. Users are advised not to use the memory controller in the
1743
     current release.
1744 98 jeremybenn
 
1745 385 jeremybenn
     Caution: There is no initialization code in the standard "newlib"
1746
     library.
1747
 
1748
     The standard "uClibc" library assumes a memory controller mapped
1749
     at 0x93000000 and will initialize the memory controller to expect
1750
     64MB memory blocks, and any memory declarations _must_ reflect
1751
     this.
1752
 
1753 98 jeremybenn
     If smaller memory blocks are declared with a memory controller,
1754
     then sufficient memory will not be allocated by Or1ksim, but out of
1755 346 jeremybenn
     range memory accesses will not be trapped.  For example declaring a
1756 98 jeremybenn
     memory section from 0-4MB with a memory controller enabled would
1757
     mean that accesses between 4MB and 64MB would be permitted, but
1758
     having no allocated memory would likely cause a segmentation fault.
1759
 
1760
     If the user is determined to use smaller memories with the memory
1761
     controller, then custom initialization code must be provided, to
1762
     ensure the memory controller traps out-of-memory accesses.
1763
 
1764
The following parameters may be specified.
1765
 
1766 19 jeremybenn
`enabled = 0|1'
1767 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
1768
     0, it is disabled.
1769 19 jeremybenn
 
1770
          Note: The memory controller can effectively also be disabled
1771
          by setting an appropriate power on control register value
1772 82 jeremybenn
          (see below).  However this should only be used if it is
1773 19 jeremybenn
          desired to specifically model this behavior of the memory
1774
          controller, not as a way of disabling the memory controller
1775
          in general.
1776
 
1777
`baseaddr = VALUE'
1778
     Set the base address of the memory controller's memory mapped
1779 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
1780 19 jeremybenn
     sensible value.
1781
 
1782
     The memory controller has a 7 bit address bus, with a total of 19
1783
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1784
     addresses 0x50 through 0x7c are not used).
1785
 
1786
`poc = VALUE'
1787
     Specifies the value of the power on control register, The least
1788
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
1789
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
1790
     the type of memory connected (use 0 for a disabled interface, 1
1791
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
1792
     devices).
1793
 
1794
     If other bits are specified, they are ignored with a warning.
1795
 
1796
          Caution: The default value, 0, corresponds to a disabled
1797
          8-bit bus, and is likely not the most suitable value
1798
 
1799
`index = VALUE'
1800
     Specify the index of this memory controller amongst all the memory
1801 82 jeremybenn
     controllers.  This value should be unique for each memory
1802 19 jeremybenn
     controller, and is used to associate specific memories with the
1803
     controller, through the `mc' field in the `section memory'
1804
     configuration (*note Memory Configuration: Memory Configuration.).
1805
 
1806
     The default value, 0, is suitable when there is only one memory
1807
     controller.
1808
 
1809
 
1810

1811
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
1812
 
1813
3.4.2 UART Configuration
1814
------------------------
1815
 
1816
The UART implemented in Or1ksim follows the specification of the
1817 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
1818 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
1819
 
1820
The component provides a number of interfaces to emulate the behavior
1821
of an external terminal connected to the UART.
1822
 
1823 82 jeremybenn
UART configuration is described in `section uart'.  This section may
1824
appear multiple times, specifying multiple UARTs.  The following
1825 19 jeremybenn
parameters may be specified.
1826
 
1827
`enabled = 0|1'
1828 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
1829 19 jeremybenn
     disabled.
1830
 
1831
`baseaddr = VALUE'
1832
     Set the base address of the UART's memory mapped registers to
1833 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1834 19 jeremybenn
 
1835
     The UART has a 3 bit address bus, with a total of 8 8-bit
1836
     registers, at addresses 0x0 through 0x7.
1837
 
1838
`channel = "TYPE:ARGS"'
1839
     Specify the channel representing the terminal connected to the UART
1840
     Rx & Tx pins.
1841
 
1842
    `channel="file:`rxfile',`txfile'"'
1843
          Read input characters from the file `rxfile' and write output
1844
          characters to the file `txfile' (which will be created if
1845
          required).
1846
 
1847
    `channel="xterm:ARGS"'
1848
          Create an xterm on startup, write UART Tx traffic to the
1849
          xterm and take Rx traffic from the keyboard when the xterm
1850 82 jeremybenn
          window is selected.  Additional arguments to the xterm
1851
          command (for example specifying window size may be specified
1852
          in ARGS, or this may be left blank.
1853 19 jeremybenn
 
1854
    `channel="tcp:VALUE"'
1855
          Open the TCP/IP port specified by VALUE and read and write
1856
          UART traffic from and to it.
1857
 
1858
          Typically a telnet session is connected to the other end of
1859
          this port.
1860
 
1861
               Tip: There is no registered port for Or1ksim telnet UART
1862 82 jeremybenn
               connection.  Priviledged access is required to read
1863 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
1864 346 jeremybenn
               Instead users should use port values in the "Dynamic" or
1865
               "Private" port range, i.e.  49152-65535.
1866 19 jeremybenn
 
1867
    `channel="fd:`rxfd',`txfd'"'
1868
          Read and write characters from and to the existing open
1869
          numerical file descriptors, file `rxfd' and `txfd'.
1870
 
1871
    `channel="tty:device=/dev/ttyS0,baud=9600"'
1872
          Read and write characters from and to a physical serial port.
1873 346 jeremybenn
          The precise device (shown here as `/dev/ttyS0') may vary from
1874
          machine to machine.
1875 19 jeremybenn
 
1876
 
1877
     The default value for this field is `"xterm:"'.
1878
 
1879
`irq = VALUE'
1880 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
1881 19 jeremybenn
 
1882
`16550 = 0|1'
1883 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
1884
     default), it has the functionality of a 16450.  The principal
1885 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
1886
 
1887
`jitter = VALUE'
1888
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
1889 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
1890 19 jeremybenn
 
1891
          Note: This functionality has yet to be implemented, so this
1892
          parameter has no effect.
1893
 
1894
`vapi_id = VALUE'
1895
     VALUE specifies the value of the Verification API (VAPI) base
1896 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
1897 19 jeremybenn
     Verification API, for more details, which details the use of the
1898
     VAPI with the UART.
1899
 
1900
 
1901

1902
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
1903
 
1904
3.4.3 DMA Configuration
1905
-----------------------
1906
 
1907
The DMA controller used in Or1ksim is the component implemented at
1908 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
1909 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
1910 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1911
memory mapped component, which resides on the main OpenRISC Wishbone
1912
data bus.  The present implementation is incomplete, intended only to
1913
support the Ethernet interface (*note Ethernet Configuration::),
1914
although the Ethernet interface is not yet completed.
1915 19 jeremybenn
 
1916 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
1917
appear multiple times, specifying multiple DMA controllers.  The
1918 19 jeremybenn
following parameters may be specified.
1919
 
1920
`enabled = 0|1'
1921 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
1922
     it is disabled.
1923 19 jeremybenn
 
1924
`baseaddr = VALUE'
1925
     Set the base address of the DMA's memory mapped registers to
1926 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1927 19 jeremybenn
 
1928
     The DMA controller has a 10 bit address bus, with a total of 253
1929 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
1930
     0x010 control the overall behavior of the DMA controller.  There
1931
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
1932
     channels available.  Addresses 0x014 through 0x01c are not used.
1933 19 jeremybenn
 
1934
`irq = VALUE'
1935 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
1936 19 jeremybenn
     0.
1937
 
1938
`vapi_id = VALUE'
1939
     VALUE specifies the value of the Verification API (VAPI) base
1940 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
1941 19 jeremybenn
     API: Verification API, for more details, which details the use of
1942
     the VAPI with the DMA controller.
1943
 
1944
 
1945

1946
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
1947
 
1948
3.4.4 Ethernet Configuration
1949
----------------------------
1950
 
1951
The Ethernet MAC used in Or1ksim is the component implemented at
1952 98 jeremybenn
OpenCores, and found in the top level SVN directory, `ethmac'.  It also
1953
forms part of the OpenRISC SoC, ORPSoC.  It is described in the
1954 19 jeremybenn
document `Ethernet IP Core Specification' by Igor Mohor, which can be
1955 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1956
which resides on the main OpenRISC Wishbone data bus.
1957 19 jeremybenn
 
1958 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
1959
section may appear multiple times, specifying multiple Ethernet
1960
interfaces.  The following parameters may be specified.
1961 19 jeremybenn
 
1962
`enabled = 0|1'
1963 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
1964
     is disabled.
1965 19 jeremybenn
 
1966
`baseaddr = VALUE'
1967
     Set the base address of the MAC's memory mapped registers to
1968 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1969 19 jeremybenn
 
1970
     The Ethernet MAC has a 7-bit address bus, with a total of 21
1971 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
1972 19 jeremybenn
 
1973
          Note: The Ethernet specification describes a Tx control
1974 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
1975
          is not implemented in the Or1ksim model.
1976 19 jeremybenn
 
1977
`dma = VALUE'
1978
     VALUE specifies the DMA controller with which this Ethernet is
1979 82 jeremybenn
     associated.  The default value is 0.
1980 19 jeremybenn
 
1981
          Note: Support for external DMA is not provided in the current
1982 82 jeremybenn
          implementation, and this value is ignored.  In any case there
1983 19 jeremybenn
          is no equivalent field to which this can be matched in the
1984
          current DMA component implementation (*note DMA
1985
          Configuration: DMA Configuration.).
1986
 
1987
`irq = VALUE'
1988 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
1989 19 jeremybenn
 
1990
`rtx_type = 0|1'
1991
     If 1 (true) use a socket interface to the Ethernet (see parameter
1992 82 jeremybenn
     `sockif' below).  If 0 (the default), use a file interface,
1993
     reading and writing from and to the files specified in the
1994
     `rxfile' and `txfile' parameters (see below).
1995 19 jeremybenn
 
1996
          Note: By default the socket interface is not provided in
1997 82 jeremybenn
          Or1ksim.  If it is required, this must be requested when
1998 19 jeremybenn
          configuring, by use of the `--enable-ethphy' option to
1999
          `configure'.
2000
 
2001
               configure --target=or32-uclinux --enable-ethphy ...
2002
 
2003
`rx_channel = RXVALUE'
2004
`tx_channel = TXVALUE'
2005
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
2006 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
2007 19 jeremybenn
 
2008
          Note: As noted above, support for external DMA is not
2009
          provided in the current implementation, and so these values
2010
          are ignored.
2011
 
2012
`rxfile = "RXFILE"'
2013
`txfile = "TXFILE"'
2014
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
2015
     as input and TXFILE specifies the fie to use as output.
2016
 
2017 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
2018
     packet length (32 bits), followed by that many bytes of data.
2019
     Once the input file is empty, the Ethernet MAC behaves as though
2020
     there were no data on the Ethernet.  The default values of these
2021 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
2022
 
2023 82 jeremybenn
     The input file must exist and be readable.  The output file must be
2024
     writable and will be created if necessary.  If either of these
2025 19 jeremybenn
     conditions is not met, a warning will be given.
2026
 
2027
`sockif = "SERVICE"'
2028
     When `rtx_type' is 1 (see above), SERVICE specifies the service to
2029 82 jeremybenn
     use for communication.  This may be TCP/IP or UDP/IP.  The default
2030 19 jeremybenn
     value of this parameter is `"or1ksim_eth"'.
2031
 
2032
`vapi_id = VALUE'
2033
     VALUE specifies the value of the Verification API (VAPI) base
2034 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
2035 19 jeremybenn
     Verification API, for more details, which details the use of the
2036
     VAPI with the DMA controller.
2037
 
2038 429 julius
`phy_addr = VALUE'
2039
     VALUE specifies address for emulated ethernet PHY. Defaults to 0
2040
     otherwise.
2041 19 jeremybenn
 
2042 429 julius
 
2043 19 jeremybenn

2044
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
2045
 
2046
3.4.5 GPIO Configuration
2047
------------------------
2048
 
2049
The GPIO used in Or1ksim is the component implemented at OpenCores, and
2050 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
2051 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
2052 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
2053 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
2054
 
2055 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
2056
appear multiple times, specifying multiple GPIO devices.  The following
2057 19 jeremybenn
parameters may be specified.
2058
 
2059
`enabled = 0|1'
2060 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
2061 19 jeremybenn
     disabled.
2062
 
2063
`baseaddr = VALUE'
2064
     Set the base address of the GPIO's memory mapped registers to
2065 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2066 19 jeremybenn
 
2067
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
2068
     registers, although the number of bits that are actively used
2069 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
2070 19 jeremybenn
 
2071
`irq = VALUE'
2072 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
2073 19 jeremybenn
 
2074
`vapi_id = VALUE'
2075
     VALUE specifies the value of the Verification API (VAPI) base
2076 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
2077 19 jeremybenn
     Verification API, for more details, which details the use of the
2078 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
2079 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
2080
     but deprecated.
2081
 
2082
 
2083

2084
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
2085
 
2086
3.4.6 Display Interface Configuration
2087
-------------------------------------
2088
 
2089
Or1ksim models a VGA interface to an external monitor.  The VGA
2090
controller used in Or1ksim is the component implemented at OpenCores,
2091 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
2092 82 jeremybenn
for the optional hardware cursors.  It is described in the document
2093 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
2094 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2095
which resides on the main OpenRISC Wishbone data bus.
2096 19 jeremybenn
 
2097
The current implementation provides only functionality to dump the
2098
screen to a file at intervals.
2099
 
2100 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
2101 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
2102
The following parameters may be specified.
2103
 
2104
`enabled = 0|1'
2105 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
2106 19 jeremybenn
     disabled.
2107
 
2108
`baseaddr = VALUE'
2109
     Set the base address of the VGA controller's memory mapped
2110 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2111 19 jeremybenn
     sensible value.
2112
 
2113
     The VGA controller has a 12-bit address bus, with 7 32-bit
2114
     registers, at addresses 0x000 through 0x018, and two color lookup
2115 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2116 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2117
     are not used.
2118
 
2119
`irq = VALUE'
2120 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2121 19 jeremybenn
     0.
2122
 
2123
`refresh_rate = VALUE'
2124 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2125 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2126
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2127
     50 times per simulated second.
2128
 
2129
`txfile = "FILE"'
2130
     FILE specifies the base of the filename for screen dumps.
2131
     Successive screen dumps will be in BMP format, in files with the
2132
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2133 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2134 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2135
     supported for this parameter, but deprecated.
2136
 
2137
 
2138

2139
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2140
 
2141
3.4.7 Frame Buffer Configuration
2142
--------------------------------
2143
 
2144 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2145 19 jeremybenn
     configuration fields are described here, but the component should
2146 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2147 19 jeremybenn
     to make screen dumps to file.
2148
 
2149 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2150
may appear multiple times, specifying multiple frame buffers.  The
2151 19 jeremybenn
following parameters may be specified.
2152
 
2153
`enabled = 0|1'
2154 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2155 19 jeremybenn
     is disabled.
2156
 
2157
`baseaddr = VALUE'
2158
     Set the base address of the frame buffer's memory mapped registers
2159 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2160
     value.
2161 19 jeremybenn
 
2162
     The frame buffer has an 121-bit address bus, with 4 32-bit
2163
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2164 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2165 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2166
 
2167
`refresh_rate = VALUE'
2168 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2169 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2170
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2171
     50 times per simulated second.
2172
 
2173
`txfile = "FILE"'
2174
     FILE specifies the base of the filename for screen dumps.
2175
     Successive screen dumps will be in BMP format, in files with the
2176
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2177 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2178 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2179
     supported for this parameter, but deprecated.
2180
 
2181
 
2182

2183
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2184
 
2185
3.4.8 Keyboard Configuration (PS2)
2186
----------------------------------
2187
 
2188 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2189 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2190 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2191
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2192 19 jeremybenn
standard, this is presumably what is expected with this device.
2193
 
2194
The implementation only provides for keyboard support, which is
2195 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2196 19 jeremybenn
 
2197
     Caution: A standard i8042 device has two registers at addresses
2198 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2199
     suggests that the Or1ksim component places these registers at
2200
     addresses 0x00 and 0x04.
2201 19 jeremybenn
 
2202
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2203
     implements the i8042 device driver, anticipating these registers
2204 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2205 19 jeremybenn
     code will work.
2206
 
2207
     This component should be used with caution.
2208
 
2209 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2210
appear multiple times, specifying multiple keyboard interfaces.  The
2211 19 jeremybenn
following parameters may be specified.
2212
 
2213
`enabled = 0|1'
2214 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2215 19 jeremybenn
     disabled.
2216
 
2217
`baseaddr = VALUE'
2218
     Set the base address of the keyboard's memory mapped registers to
2219 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2220 19 jeremybenn
 
2221
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2222
     registers, at addresses 0x000 and 0x004.
2223
 
2224
          Caution: As noted above, a standard Intel 8042 interface
2225
          would expect to find these registers at locations 0x60 and
2226
          0x64, thus requiring at least a 7-bit bus.
2227
 
2228
`irq = VALUE'
2229 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2230 19 jeremybenn
     value 0.
2231
 
2232
`rxfile = "FILE"'
2233
     `file' specifies a file containing raw key stroke data, which
2234 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2235 19 jeremybenn
     `"kbd_in"'.
2236
 
2237
 
2238

2239
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2240
 
2241
3.4.9 Disc Interface Configuration
2242
----------------------------------
2243
 
2244
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2245
IDE Controller) component implemented at OpenCores, and found in the
2246 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2247 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2248 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2249
which resides on the main OpenRISC Wishbone data bus.
2250 19 jeremybenn
 
2251 385 jeremybenn
     Warning: In the current release of Or1ksim, parsing of the ATA
2252
     section is broken. Users should not configure the disc interface
2253
     in this release.
2254
 
2255 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2256
may appear multiple times, specifying multiple disc controllers.  The
2257 19 jeremybenn
following parameters may be specified.
2258
 
2259
`enabled = 0|1'
2260 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2261 19 jeremybenn
     0, it is disabled.
2262
 
2263
`baseaddr = VALUE'
2264
     Set the base address of the ATA/ATAPI interface's memory mapped
2265 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2266 19 jeremybenn
     sensible value.
2267
 
2268
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2269 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2270
     ATA/ATAPI interface selected (see `dev_id' below), not all
2271
     registers will be available.
2272 19 jeremybenn
 
2273
`irq = VALUE'
2274 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2275 19 jeremybenn
     value 0.
2276
 
2277
`dev_id = 1|2|3'
2278
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2279 82 jeremybenn
     interface to model.  The default value is 1.
2280 19 jeremybenn
 
2281
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2282
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2283
     registers and the `RXD'/`TXD' registers.
2284
 
2285
`rev = VALUE'
2286
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2287 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2288
     be in the range 0-15.  Larger values are truncated with a warning.
2289 346 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2290
     forms bits 24-27.
2291 19 jeremybenn
 
2292
`pio_mode0_t1 = VALUE'
2293
`pio_mode0_t2 = VALUE'
2294
`pio_mode0_t4 = VALUE'
2295
`pio_mode0_teoc = VALUE'
2296
     These parameters specify the timings for use with Programmed
2297 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2298 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2299 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2300 19 jeremybenn
     they do, they will be ignored with a warning.
2301
 
2302
     See the ATA/ATAPI-5 specification for explanations of each of these
2303 82 jeremybenn
     timing parameters.  The default values are:
2304 19 jeremybenn
 
2305
          pio_mode0_t1   =  6
2306
          pio_mode0_t2   = 28
2307
          pio_mode0_t4   =  2
2308
          pio_mode0_teoc = 23
2309
 
2310
`dma_mode0_tm = VALUE'
2311
`dma_mode0_td = VALUE'
2312
`dma_mode0_teoc = VALUE'
2313
     These parameters specify the timings for use with DMA transfers.
2314
     They are specified as the number of clock cycles - 2, rounded up
2315
     to the next highest integer, or zero if that would be negative.
2316 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2317
     ignored with a warning.
2318 19 jeremybenn
 
2319
     See the ATA/ATAPI-5 specification for explanations of each of these
2320 82 jeremybenn
     timing parameters.  The default values are:
2321 19 jeremybenn
 
2322
          dma_mode0_tm   =  4
2323
          dma_mode0_td   = 21
2324
          dma_mode0_teoc = 21
2325
 
2326
 
2327
3.4.9.1 ATA/ATAPI Device Configuration
2328
......................................
2329
 
2330 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2331 19 jeremybenn
device subsection is introduced by
2332
 
2333
     device VALUE
2334
 
2335 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2336
ends with `enddevice'.  Note that if the same device number is
2337
specified more than once, the previous values will be overwritten.
2338
Within the `device' subsection, the following parameters may appear:
2339 19 jeremybenn
 
2340
`type = VALUE'
2341
     VALUEspecifies the type of device: 0 (the default) for "not
2342
     connected", 1 for hard disk simulated in a file and 2 for local
2343
     system hard disk.
2344
 
2345
`file = "FILENAME"'
2346
     `filename' specifies the file to be used for a simulated ATA
2347 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2348 346 jeremybenn
     `"ata_fileN"', where N is the device number.
2349 19 jeremybenn
 
2350
`size = VALUE'
2351
     VALUE specifies the size of a simulated ATA device if the file
2352 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2353 19 jeremybenn
 
2354
`packet = 0|1'
2355 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2356 19 jeremybenn
     default), do not implement the PACKET command feature set.
2357
 
2358
`firmware = "STR"'
2359
     Firmware to report in response to the "Identify Device" command.
2360
     Default `"02207031"'.
2361
 
2362
`heads = VALUE'
2363 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2364 19 jeremybenn
     heads.
2365
 
2366
`sectors = VALUE'
2367 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2368 19 jeremybenn
 
2369
`mwdma = 0|1|2|-1'
2370 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2371 19 jeremybenn
     disable.
2372
 
2373
`pio = 0|1|2|3|4'
2374 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2375 19 jeremybenn
 
2376
 
2377

2378
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2379
 
2380
3.4.10 Generic Peripheral Configuration
2381
---------------------------------------
2382
 
2383
When used as a library (*note Simulator Library: Simulator Library.),
2384
Or1ksim makes provision for any additional peripheral to be implemented
2385 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2386
generates "upcall"s to an external handler.  This interface can support
2387 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2388
for OSCI SystemC (see `http://www.systemc.org').
2389
 
2390
Generic peripheral configuration is described in `section generic'.
2391
This section may appear multiple times, specifying multiple external
2392 82 jeremybenn
peripherals.  The following parameters may be specified.
2393 19 jeremybenn
 
2394
`enabled = 0|1'
2395 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2396 19 jeremybenn
     0, it is disabled.
2397
 
2398
`baseaddr = VALUE'
2399
     Set the base address of the generic peripheral's memory mapped
2400 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2401 19 jeremybenn
     sensible value.
2402
 
2403
     The size of the memory mapped register space is controlled by the
2404
     `size' paramter, described below.
2405
 
2406
`size = VALUE'
2407
     Set the size of the generic peripheral's memory mapped register
2408 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2409 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2410
     parameter `baseaddr' (see above) will be directed to the external
2411
     interface.
2412
 
2413 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2414
     value is zero.  If VALUE is not an exact power of two, accesses to
2415 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2416
     generate a warning, and have no effect (reads will return zero).
2417
 
2418
`name = "STR"'
2419 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2420 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2421 82 jeremybenn
     reporting its status.  The default value is
2422 19 jeremybenn
     `"anonymous external peripheral"'.
2423
 
2424
`byte_enabled = 0|1'
2425
`hw_enabled = 0|1'
2426
`word_enabled = 0|1'
2427
     If 1 (true, the default), these parameters respectively enable the
2428 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2429 19 jeremybenn
     accesses of that width will fail.
2430
 
2431
 
2432

2433
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2434
 
2435
4 Interactive Command Line
2436
**************************
2437
 
2438
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2439 82 jeremybenn
provides the user with an interactive command line.  The commands
2440 19 jeremybenn
available, which may not be abbreviated, are:
2441
 
2442
`q'
2443
     Exit the simulator
2444
 
2445
`r'
2446 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2447 19 jeremybenn
     just executed and next to be executed instructions symbolically
2448
     and the state of the flag in the Supervision Register.
2449
 
2450
`t'
2451
     Execute the next instruction and then display register/instruction
2452
     information as with the `r' command (see above).
2453
 
2454
`run NUM [ hush ]'
2455 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2456 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2457
     above) _unless_ `hush' is specified.
2458
 
2459
`pr REG VALUE'
2460
     Patch register REG with VALUE.
2461
 
2462
`dm FROMADDR [ TOADDR ]'
2463 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2464
     not given, 64 bytes are displayed, starting at FROMADDR.
2465 19 jeremybenn
 
2466
          Caution: The output from this command is broken (a bug).
2467 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2468 19 jeremybenn
          instead of printing out the address at the start of each row,
2469
          it prints the address (of the first of the 16 bytes) before
2470
          _each_ byte.
2471
 
2472
`de FROMADDR [ TOADDR ]'
2473 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2474 19 jeremybenn
     given, 16 instructions are disassembled.
2475
 
2476
     The disassembly is entirely numerical, and gives no symbolic
2477
     information.
2478
 
2479
`pm ADDR VALUE'
2480
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2481
 
2482
`pc VALUE'
2483
     Patch the program counter with VALUE.
2484
 
2485
`cm FROMADDR TOADDR SIZE'
2486
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2487
 
2488
`break ADDR'
2489
     Toggle the breakpoint set at ADDR.
2490
 
2491
`breaks'
2492
     List all set breakpoints
2493
 
2494
`reset'
2495 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2496
     so execution will restart from the reset vector location, 0x100.
2497 19 jeremybenn
 
2498
`hist'
2499
     If saving the execution history has been configured (*note
2500
     Simulator Behavior: Simulator Behavior.), display the execution
2501
     history.
2502
 
2503
`stall'
2504
     Stall the processor, so that control is passed to the debug unit.
2505 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2506 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2507
     debuggers such as GDB.
2508
 
2509
`unstall'
2510 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2511
     This command is useful when debugging the JTAG interface, used by
2512 19 jeremybenn
     debuggers such as GDB.
2513
 
2514
`stats CATEGORY | clear'
2515
     Print the statistics for the given CATEGORY, if available, or
2516 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2517 19 jeremybenn
 
2518
    1
2519
          Miscellaneous statistics: branch predictions (if branch
2520
          predictions are enabled), branch target cache model (if
2521
          enabled), cache (if enbaled), MMU (if enabled) and number of
2522
          addtional load & store cycles.
2523
 
2524
          *Note Configuring the OpenRisc Achitectural Components: Core
2525
          OpenRISC Configuration, for details of how to enable these
2526
          various features.
2527
 
2528
    2
2529 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2530 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2531
 
2532
    3
2533 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2534 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2535
 
2536
    4
2537 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2538 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2539
          Configuration.).
2540
 
2541
    5
2542 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2543 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2544
 
2545
    6
2546 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2547 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2548
 
2549
 
2550
`info'
2551
     Display detailed information about the simulator configuration.
2552
     This is quite a lengthy about, because all MMU TLB information is
2553
     displayed.
2554
 
2555
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2556
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2557 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2558 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2559 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2560 19 jeremybenn
 
2561
     To save to a file, use the redirection function (described after
2562
     this table, below).
2563
 
2564
`dh FROMADDR [ TOADDR ]'
2565
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2566 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2567 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2568
 
2569
     To save to a file, use the redirection function (described after
2570
     this table, below).
2571
 
2572
`setdbch'
2573 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2574 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2575
     channels on the command line.
2576
 
2577
`set SECTION PARAM = VALUE'
2578
     Set the configuration parameter PARA in section SECTION to VALUE.
2579
     *Note Configuration: Configuration, for details of configuration
2580
     parameters and their settings.
2581
 
2582
`debug'
2583 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2584 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2585
     this parameter.
2586
 
2587
          Caution: This is effectively enabling or disabling the debug
2588 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2589 19 jeremybenn
          However using the remote debug interface while the debug unit
2590
          is disabled will lead to undefined behavior and likely crash
2591
          Or1ksim
2592
 
2593
`cuc'
2594
     Enter the the Custom Unit Compiler command prompt (*note CUC
2595
     Configuration: CUC Configuration.).
2596
 
2597
          Caution: The CUC must be properly configured, for this to
2598 82 jeremybenn
          succeed.  In particular a timing file must be available and
2599
          readable.  Otherwise Or1ksim will crash.
2600 19 jeremybenn
 
2601
`help'
2602
     Print out brief information about each command available.
2603
 
2604
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2605 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2606 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2607
     Profiling Utility.).
2608
 
2609
`profile [-vhcq] [-g FILE]'
2610 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2611
     usage as the standalone command (*note Profiling Utility:
2612
     Profiling Utility.).
2613 19 jeremybenn
 
2614
 
2615
For all commands, it is possible to redirect the output to a file, by
2616
using the redirection operator, `>'.
2617
 
2618
     COMMAND > FILENAME
2619
 
2620
This is particularly useful for commands dumping a large amount of
2621
output, such as `dv'.
2622
 
2623
     Caution: Unfortunately there is a serious bug with the redirection
2624 82 jeremybenn
     operator.  It does not return output to standard output after the
2625
     command completes.  Until this bug is fixed, file redirection
2626 19 jeremybenn
     should not be used.
2627
 
2628

2629
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2630
 
2631
5 Verification API (VAPI)
2632
*************************
2633
 
2634
The Verification API (VAPI) provides a TCP/IP interface to allow
2635 82 jeremybenn
components of the simulation to be controlled externally.  The
2636
interface is polled for new requests on each simulated clock cycle.
2637
Components within the simulator may send responses to such requests.
2638 19 jeremybenn
 
2639 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2640
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2641
with a single piece of data (also a 32 bit integer).  On the send side,
2642
it provides for sending a single VAPI ID and data.  However there is no
2643
explicit command-response structure.  Some components just accept
2644
requests (e.g.  to set values), some just generate sends (to report
2645 19 jeremybenn
values), and some do both.
2646
 
2647
Each component has a base ID (32 bit) and its commands will start from
2648 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2649
amongst components.  Request commands will be directed to the component
2650 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2651
 
2652
Thus if there are two components with base IDs of 0x200 and 0x300, and
2653
a request with VAPI ID of 0x203 is received, it will be directed to the
2654
first component as its command #3.
2655
 
2656
The results of VAPI interactions are logged (by default in `vapi.log'
2657
unless an alternative is specified in `section vapi').
2658
 
2659
Currently the following components support VAPI:
2660
 
2661
Debug Unit
2662
     Although the Debug Unit can specify a base VAPI ID, it is not used
2663
     to send commands or receive requests.
2664
 
2665
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2666
     exchanges are logged in the VAPI log file.
2667
 
2668
UART
2669
     If a base VAPI ID is specified, the UART sends details of any
2670
     chars or break characters sent, with dteails of the line control
2671
     register etc encoded in the data packet sent.
2672
 
2673
     This supports a single VAPI command request, but encodes a
2674
     sub-command in the top 8 bits of the associated data.
2675
 
2676
    `0x00'
2677
          This stuffs the least significant 8 bits of the data into the
2678
          serial register of the UART and the next 8 bits into the line
2679
          control register, effectively providing control of the next
2680
          character to be sent or received.
2681
 
2682
    `0x01'
2683
          The divisor latch bytes are set from the least significant 16
2684
          bits of the data.
2685
 
2686
    `0x02'
2687
          The line control register is set from bits 15-8 of the data.
2688
 
2689
    `0x03'
2690
          The UART skew is set from the least significant 16 bits of
2691
          the data
2692
 
2693
    `0x04'
2694
          If the 16th most significant bit of the data is 1, start
2695 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
2696
          are sent or cleared after the number of UART clock divider
2697
          ticks specified by the data (immediately if the data is zero).
2698 19 jeremybenn
 
2699
 
2700
DMA
2701
     Although the DMA unit supports a base VAPI ID in its configuration
2702
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
2703
     implemented.
2704
 
2705
Ethernet
2706 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
2707 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
2708 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
2709 19 jeremybenn
     VAPI requests.
2710
 
2711
    `ETH_VAPI_DATA (0)'
2712
 
2713
    `ETH_VAPI_CTRL (0)'
2714
 
2715
GPIO
2716
     If a base VAPI ID is specified, the GPIO sends out on its base
2717
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
2718
     VAPI ID) any changes in outputs.
2719
 
2720 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
2721 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
2722
     GPIO.
2723
 
2724
    `GPIO_VAPI_DATA (0)'
2725
          Set the next input to the commands data field
2726
 
2727
    `GPIO_VAPI_AUX (1)'
2728
          Set the GPIO auxiliary inputs to the data field
2729
 
2730
    `GPIO_VAPI_CLOCK (2)'
2731
          Add an external GPIO clock trigger of period specified in the
2732
          data field.
2733
 
2734
    `GPIO_VAPI_RGPIO_OE (3)'
2735
          Set the GPIO output enable to the data field
2736
 
2737
    `GPIO_VAPI_RGPIO_INTE (4)'
2738
          Set the next interrupt to the data field
2739
 
2740
    `GPIO_VAPI_RGPIO_PTRIG (5)'
2741
          Set the next trigger to the data field
2742
 
2743
    `GPIO_VAPI_RGPIO_AUX (6)'
2744
          Set the next auxiliary input to the data field
2745
 
2746
    `GPIO_VAPI_RGPIO_CTRL (7)'
2747
          Set th next control input to the data field
2748
 
2749
 
2750
 
2751

2752
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
2753
 
2754
6 A Guide to Or1ksim Internals
2755
******************************
2756
 
2757 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
2758 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
2759 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
2760
Linux manual page for `etags'.  A tag file can be created with:
2761 19 jeremybenn
 
2762
     make tags
2763
 
2764
* Menu:
2765
 
2766
* Coding Conventions::
2767
* Global Data Structures::
2768
* Concepts::
2769
* Internal Debugging::
2770 104 jeremybenn
* Regression Testing::
2771 19 jeremybenn
 
2772

2773
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
2774
 
2775
6.1 Coding Conventions for Or1ksim
2776
==================================
2777
 
2778
This chapter provides some guidelines for coding, to facilitate
2779
extensions to Or1ksim
2780
 
2781
_GNU Coding Standard_
2782
     Code should follow the GNU coding standard for C
2783 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
2784 19 jeremybenn
     through the `indent' program.
2785
 
2786
_`#include' headers_
2787
     All C source code files should include `config.h' before any other
2788
     file.
2789
 
2790
     This should be followed by inclusion of any system headers (but see
2791
     the comments about portability and `port.h' below) and then by any
2792
     Or1ksim package headers.
2793
 
2794
     If `port.h' is required, it should be the first package header to
2795
     be included after the system headers.
2796
 
2797
     All C source code and header files should directly include any
2798 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
2799
     other header having already included it.  The two exceptions are
2800 19 jeremybenn
 
2801
       1. All header files may assume that `config.h' has already been
2802
          included.
2803
 
2804
       2. System headers which impose portability problems should be
2805
          included by using the package header `port.h', rather than
2806 82 jeremybenn
          the system headers themselves.  This is the case for code
2807 19 jeremybenn
          requiring
2808
 
2809
             * `strndup' (from `string.h')
2810
 
2811
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
2812
 
2813
             * `isblank' (from `ctype.h')
2814
 
2815
 
2816
 
2817
_`#include' files once only_
2818
     All include files should be protected by `#ifndef' to ensure their
2819 82 jeremybenn
     definitions are only included once.  For instance a header file
2820 19 jeremybenn
     `X-Y.H' should surround its contents with:
2821
 
2822
          #ifndef X_Y__H
2823
          #define X_Y__H
2824
 
2825
          
2826
 
2827
          #endif  /* X_Y__H */
2828
 
2829
_Avoid `typedef'_
2830
     The GNU coding style for C does not have a clear way to distinguish
2831 82 jeremybenn
     between user type name and user variables.  For this reason
2832 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
2833 82 jeremybenn
     defined types.  This makes the code much easier to read.
2834 19 jeremybenn
 
2835
     There are some `typedef' declarations in the `argtable2' library
2836
     and the ELF and COFF headers, because this code is taken from
2837
     other places.
2838
 
2839
     Within Or1ksim legacy uses of `typedef' have largely been purged,
2840
     except in the Custom Unit Compiler (*note Custom Unit Compiler
2841
     (CUC) Configuration: CUC Configuration.).
2842
 
2843
     The remaining uses of `typedef' occur in two places:
2844
 
2845
        * `port/port.h' defines types to replace those in header files
2846
          that are not available (character functions, string
2847
          duplication, integer types).
2848
 
2849
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
2850
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
2851
          and signed register (`orreg_t') values.
2852
 
2853
 
2854
     Where new types are defined, they should appear in one of these two
2855 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
2856
     `arch.h' should always have the suffix `_h'.
2857 19 jeremybenn
 
2858
_Don't begin names with underscore_
2859
     Names beginning with `_' are intended to be part of the C
2860 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
2861 19 jeremybenn
 
2862
_Keep Non-global top level entities static_
2863
     All top level entities (functions, variables), which are not
2864
     explicitly part of a global interface should be declared static.
2865
     This ensures that unwanted connections are not inadvertently built
2866
     across the program.
2867
 
2868
_Use of `inline'_
2869 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
2870 19 jeremybenn
     out for themselves what is best in this respect.
2871
 
2872
_Initialization_
2873 82 jeremybenn
     All data structures should be explicitly initialized.  In
2874
     particular code should not rely on static data structures being
2875
     initialized to zero.
2876 19 jeremybenn
 
2877
     The rationale is that in future static data structures may become
2878 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
2879 19 jeremybenn
     historically.
2880
 
2881
     A specific case is with new peripherals, which should always
2882
     include a `start' function to pre-initialize all configuration
2883
     parameters to sensible defaults
2884
 
2885
_Configuration Validation_
2886
     All configuration values should be validated, preferably when
2887
     encountered, if not when the `section' is closed, or otherwise at
2888
     run time when the parameter is first used.
2889
 
2890
 
2891

2892
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
2893
 
2894
6.2 Global Data Structures
2895
==========================
2896
 
2897
`config'
2898
     The global variable `config' of type `struct config' holds the
2899
     configuration data for some of the Or1ksim components which are
2900 82 jeremybenn
     always present.  At present the components are:
2901 19 jeremybenn
 
2902
        * The simulator defined in `section sim' (*note Simulator
2903
          Configuration: Simulator Configuration.).
2904
 
2905
        * The Verification API (VAPI) defined  in `section vapi' (*note
2906
          Verification API (VAPI) Configuration: Verification API
2907
          Configuration.).
2908
 
2909
        * The Custom Unit Compiler (CUC), defined in `section cuc'
2910
          (*note Custom Unit Compiler (CUC) Configuration: CUC
2911
          Configuration.).
2912
 
2913
        * The CPU, defined in `section cpu' (*note CPU Configuration:
2914
          CPU Configuration.).
2915
 
2916
        * The data cache (but not the instruction cache), defined in
2917
          `section dc' (*note Cache Configuration: Cache
2918
          Configuration.).
2919
 
2920
        * The power management unit, defined in `section pm' (*note
2921
          Power Management Configuration: Power Management
2922
          Configuration.).
2923
 
2924
        * The programmable interrupt controller, defined in
2925
          `section pic' (*note Interrupt Configuration: Interrupt
2926
          Configuration.).
2927
 
2928
        * Branch prediciton, defined in `section bpb' (*note Branch
2929
          Prediction Configuration: Branch Prediction Configuration.).
2930
 
2931
        * The debug unit, defined in `section debug' (*note Debug
2932
          Interface Configuration: Debug Interface Configuration.).
2933
 
2934
 
2935
     This struct is made of a collection of structs, one for each
2936 82 jeremybenn
     component.  For example the simulator configuration is held in
2937 19 jeremybenn
     `config.sim'.
2938
 
2939
`config'
2940
     This is a linked list of data structures holding configuration data
2941
     for all sections which are not held in the main `config' data
2942 82 jeremybenn
     structure.  In general these are components (such as peripherals
2943
     and memory) which may occur multiple times.  However it also
2944
     handles some architectural components which may occur only once,
2945
     such as the memory management units, the instruction cache, the
2946
     interrupt controller and branch prediction.
2947 19 jeremybenn
 
2948
`runtime'
2949
     The global variable `runtime' of type `struct runtime' holds all
2950 82 jeremybenn
     the runtime information about the simulation.  To access this
2951 19 jeremybenn
     variable, `sim-config.h' must be included.
2952
 
2953
     This struct is itself made of 3 other structs, `cpu' (for CPU run
2954
     time state), `vapi' (for Verification API state) and `cuc' (for
2955
     Custom Unit Compiler state).
2956
 
2957
 
2958

2959
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
2960
 
2961
6.3 Concepts
2962
============
2963
 
2964
_Output Redirection_
2965 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
2966 19 jeremybenn
     should be explicitly written to this stream, or may use the
2967
     `PRINTF' macro, which will write its arguments to this output
2968
     stream.
2969
 
2970
_Reset Hooks_
2971
     Any peripheral may register a routine to be called when the the
2972
     processor is reset by calling `reg_sim_reset', providing a
2973 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
2974 19 jeremybenn
     that function will be called with the data stucture pointer as
2975
     argument.
2976
 
2977 432 jeremybenn
_Interrupts_
2978
     An internal peripheral can model the effect of an interrupt being
2979
     asserted by calling `report_interrupt'.  This is used for both edge
2980
     and level sensitive interrupts.
2981 19 jeremybenn
 
2982 432 jeremybenn
     The effect is to set the corresponding bit in the PICSR SPR and to
2983
     queue an interrupt exception to take place after the current
2984
     instruction completes execution.
2985
 
2986
     Externally, the different interrupts require different mechanisms
2987
     for clearing.  Level sensitive interrupts should be cleared by
2988
     deasserting the interrupt line, edge sensitive interrupts by
2989
     clearing the corresponding bit in the PICSR SPR.
2990
 
2991
     Internally this amounts to the same thing (clearing the PICSPR
2992
     bit), so a single function is provided, `clear_interrupt'.  Note
2993
     however that when level sensitive interrupts are configured, PICSR
2994
     is read only, and can only be cleared by calling
2995
     `clear_interrupt'.  Using the two functions provided will ensure
2996
     the peripheral works correctly whichever type of interrupt is used.
2997
 
2998
          Note: Until an interrupt is cleared, all subsequent
2999
          interrupts are ignored with a warning.
3000
 
3001
 
3002 19 jeremybenn

3003 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
3004 19 jeremybenn
 
3005
6.4 Internal Debugging
3006
======================
3007
 
3008
The function `debug' is like `printf', but with an extra first
3009 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
3010
the simulator configuration (*note Simulator Behavior: Simulator
3011
Behavior.) is greater than or equal to this value, the remaining
3012
arguments are printed to the current output stream (*note Output
3013
Redirection: Output Redirection.).
3014 19 jeremybenn
 
3015

3016 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
3017
 
3018
6.5 Regression Testing
3019
======================
3020
 
3021
Or1ksim now includes a regression test suite for both standalone and
3022
library usage as described earlier (*note Building and Installing:
3023
Build and Install.).  Running the tests requires that the OpenRISC
3024
toolchain and DejaGNU are both installed.
3025
 
3026
Tests are written using `expect', a derivative of TCL.  Documentation
3027
of DejaGnu, `expect' and TCL are freely available on the Web.  The
3028
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
3029
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
3030
provides a concise introduction.
3031
 
3032
All test code is found in the `testsuite' directory.  The key files and
3033
directories used are as follows.
3034
 
3035
`global-conf.exp'
3036
     This is the global DejaGNU configuration file used to set up
3037
     parameters common to all tests.  If the user has the environment
3038
     varialbe `DEJAGNU' defined, it will be used instead, but this is
3039
     not recommended.
3040
 
3041
`Makefile.am'
3042
     This is the top level `automake' file for the testsuite.  The only
3043
     changes likely to be needed here is additional local cleanup of
3044
     files created by new tests.
3045
 
3046
`README'
3047
     This contains details of all the tests
3048
 
3049
`config'
3050
     This contains DejaGnu board configurations.  Since the tests are
3051
     generally run on a Unix host, this should just contain `Unix.exp'.
3052
 
3053
`lib'
3054
     This contains DejaGnu tool specific configurations.  "Tool" has a
3055
     specific meaning in DejaGNU, referring just to a grouping of
3056
     tests.  In this case there are two such "tools", "or1ksim" and
3057
     "libsim" for tests of the standalone tool and tests of the library.
3058
 
3059
     Corresponding to this, there are two tool specific configuration
3060
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
3061
     procedures for common use among the tests.
3062
 
3063
`libsim.tests'
3064
`or1ksim.tests'
3065
     These are the directories of tests of the Or1ksim library.  They
3066
     also include Or1ksim configuration files and each has a
3067
     `Makefile.am' file.  `Makefile.am' should be updated whenever
3068
     files are added to this directory, to ensure they are included in
3069
     the distribution.
3070
 
3071
`test-code'
3072
     These are all the test programs to be compiled on the host (each
3073
     in its own directory).  In general these are programs to support
3074
     testing of the library, and build various programs linking in the
3075
     library.
3076
 
3077
`test-code'
3078
     These are all the test programs to be compiled with the OpenRISC
3079
     tool chain to run with either standalone Or1ksim or the library.
3080
     This directory includes its own `configure.ac', since it must set
3081
     up a separate tool chain based on the target, not the host.
3082
 
3083
 
3084
To add a new test needs the following steps.
3085
 
3086 346 jeremybenn
   * Put new host C code in its own directory within `test-code'.  Add
3087 104 jeremybenn
     the directory to the existing `Makefile.am' in the `test-code'
3088
     directory and create a `Makefile.am' in the new directory to drive
3089 346 jeremybenn
     building the test program(s).  Don't forget to add the new
3090 104 jeremybenn
     `Makefile' to the top level `configure.ac' so it gets generated.
3091
     Not all tests require code here.
3092
 
3093 346 jeremybenn
   * Put new target C code in its own directory within `test-code-or1k'.
3094
     Once again modify & create `Makefile.am'.  This time modify the
3095
     `configure.ac' in the `test-code-or1k' so the `Makefile' gets
3096
     generated.  The existing programs provide examples to start from,
3097
     including custom linker scripts where needed.
3098 104 jeremybenn
 
3099
   * Add one or more tests and configuration files to the relevant
3100 346 jeremybenn
     "tool" test directory.  Use the existing tests as templates.  They
3101 104 jeremybenn
     make heavy use of the `expect'/TCL procedures in the `config'
3102
     directory to facilitate driving the tests.
3103
 
3104
 
3105

3106 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
3107
 
3108
7 GNU Free Documentation License
3109
********************************
3110
 
3111
                      Version 1.2, November 2002
3112
 
3113
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
3114
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
3115
 
3116
     Everyone is permitted to copy and distribute verbatim copies
3117
     of this license document, but changing it is not allowed.
3118
 
3119
  0. PREAMBLE
3120
 
3121
     The purpose of this License is to make a manual, textbook, or other
3122
     functional and useful document "free" in the sense of freedom: to
3123
     assure everyone the effective freedom to copy and redistribute it,
3124
     with or without modifying it, either commercially or
3125
     noncommercially.  Secondarily, this License preserves for the
3126
     author and publisher a way to get credit for their work, while not
3127
     being considered responsible for modifications made by others.
3128
 
3129
     This License is a kind of "copyleft", which means that derivative
3130
     works of the document must themselves be free in the same sense.
3131
     It complements the GNU General Public License, which is a copyleft
3132
     license designed for free software.
3133
 
3134
     We have designed this License in order to use it for manuals for
3135
     free software, because free software needs free documentation: a
3136
     free program should come with manuals providing the same freedoms
3137
     that the software does.  But this License is not limited to
3138
     software manuals; it can be used for any textual work, regardless
3139
     of subject matter or whether it is published as a printed book.
3140
     We recommend this License principally for works whose purpose is
3141
     instruction or reference.
3142
 
3143
  1. APPLICABILITY AND DEFINITIONS
3144
 
3145
     This License applies to any manual or other work, in any medium,
3146
     that contains a notice placed by the copyright holder saying it
3147
     can be distributed under the terms of this License.  Such a notice
3148
     grants a world-wide, royalty-free license, unlimited in duration,
3149
     to use that work under the conditions stated herein.  The
3150
     "Document", below, refers to any such manual or work.  Any member
3151
     of the public is a licensee, and is addressed as "you".  You
3152
     accept the license if you copy, modify or distribute the work in a
3153
     way requiring permission under copyright law.
3154
 
3155
     A "Modified Version" of the Document means any work containing the
3156
     Document or a portion of it, either copied verbatim, or with
3157
     modifications and/or translated into another language.
3158
 
3159
     A "Secondary Section" is a named appendix or a front-matter section
3160
     of the Document that deals exclusively with the relationship of the
3161
     publishers or authors of the Document to the Document's overall
3162
     subject (or to related matters) and contains nothing that could
3163
     fall directly within that overall subject.  (Thus, if the Document
3164
     is in part a textbook of mathematics, a Secondary Section may not
3165
     explain any mathematics.)  The relationship could be a matter of
3166
     historical connection with the subject or with related matters, or
3167
     of legal, commercial, philosophical, ethical or political position
3168
     regarding them.
3169
 
3170
     The "Invariant Sections" are certain Secondary Sections whose
3171
     titles are designated, as being those of Invariant Sections, in
3172
     the notice that says that the Document is released under this
3173
     License.  If a section does not fit the above definition of
3174
     Secondary then it is not allowed to be designated as Invariant.
3175
     The Document may contain zero Invariant Sections.  If the Document
3176
     does not identify any Invariant Sections then there are none.
3177
 
3178
     The "Cover Texts" are certain short passages of text that are
3179
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3180
     that says that the Document is released under this License.  A
3181
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3182
     be at most 25 words.
3183
 
3184
     A "Transparent" copy of the Document means a machine-readable copy,
3185
     represented in a format whose specification is available to the
3186
     general public, that is suitable for revising the document
3187
     straightforwardly with generic text editors or (for images
3188
     composed of pixels) generic paint programs or (for drawings) some
3189
     widely available drawing editor, and that is suitable for input to
3190
     text formatters or for automatic translation to a variety of
3191
     formats suitable for input to text formatters.  A copy made in an
3192
     otherwise Transparent file format whose markup, or absence of
3193
     markup, has been arranged to thwart or discourage subsequent
3194
     modification by readers is not Transparent.  An image format is
3195
     not Transparent if used for any substantial amount of text.  A
3196
     copy that is not "Transparent" is called "Opaque".
3197
 
3198
     Examples of suitable formats for Transparent copies include plain
3199
     ASCII without markup, Texinfo input format, LaTeX input format,
3200
     SGML or XML using a publicly available DTD, and
3201
     standard-conforming simple HTML, PostScript or PDF designed for
3202
     human modification.  Examples of transparent image formats include
3203
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3204
     can be read and edited only by proprietary word processors, SGML or
3205
     XML for which the DTD and/or processing tools are not generally
3206
     available, and the machine-generated HTML, PostScript or PDF
3207
     produced by some word processors for output purposes only.
3208
 
3209
     The "Title Page" means, for a printed book, the title page itself,
3210
     plus such following pages as are needed to hold, legibly, the
3211
     material this License requires to appear in the title page.  For
3212
     works in formats which do not have any title page as such, "Title
3213
     Page" means the text near the most prominent appearance of the
3214
     work's title, preceding the beginning of the body of the text.
3215
 
3216
     A section "Entitled XYZ" means a named subunit of the Document
3217
     whose title either is precisely XYZ or contains XYZ in parentheses
3218
     following text that translates XYZ in another language.  (Here XYZ
3219
     stands for a specific section name mentioned below, such as
3220
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3221
     To "Preserve the Title" of such a section when you modify the
3222
     Document means that it remains a section "Entitled XYZ" according
3223
     to this definition.
3224
 
3225
     The Document may include Warranty Disclaimers next to the notice
3226
     which states that this License applies to the Document.  These
3227
     Warranty Disclaimers are considered to be included by reference in
3228
     this License, but only as regards disclaiming warranties: any other
3229
     implication that these Warranty Disclaimers may have is void and
3230
     has no effect on the meaning of this License.
3231
 
3232
  2. VERBATIM COPYING
3233
 
3234
     You may copy and distribute the Document in any medium, either
3235
     commercially or noncommercially, provided that this License, the
3236
     copyright notices, and the license notice saying this License
3237
     applies to the Document are reproduced in all copies, and that you
3238
     add no other conditions whatsoever to those of this License.  You
3239
     may not use technical measures to obstruct or control the reading
3240
     or further copying of the copies you make or distribute.  However,
3241
     you may accept compensation in exchange for copies.  If you
3242
     distribute a large enough number of copies you must also follow
3243
     the conditions in section 3.
3244
 
3245
     You may also lend copies, under the same conditions stated above,
3246
     and you may publicly display copies.
3247
 
3248
  3. COPYING IN QUANTITY
3249
 
3250
     If you publish printed copies (or copies in media that commonly
3251
     have printed covers) of the Document, numbering more than 100, and
3252
     the Document's license notice requires Cover Texts, you must
3253
     enclose the copies in covers that carry, clearly and legibly, all
3254
     these Cover Texts: Front-Cover Texts on the front cover, and
3255
     Back-Cover Texts on the back cover.  Both covers must also clearly
3256
     and legibly identify you as the publisher of these copies.  The
3257
     front cover must present the full title with all words of the
3258
     title equally prominent and visible.  You may add other material
3259
     on the covers in addition.  Copying with changes limited to the
3260
     covers, as long as they preserve the title of the Document and
3261
     satisfy these conditions, can be treated as verbatim copying in
3262
     other respects.
3263
 
3264
     If the required texts for either cover are too voluminous to fit
3265
     legibly, you should put the first ones listed (as many as fit
3266
     reasonably) on the actual cover, and continue the rest onto
3267
     adjacent pages.
3268
 
3269
     If you publish or distribute Opaque copies of the Document
3270
     numbering more than 100, you must either include a
3271
     machine-readable Transparent copy along with each Opaque copy, or
3272
     state in or with each Opaque copy a computer-network location from
3273
     which the general network-using public has access to download
3274
     using public-standard network protocols a complete Transparent
3275
     copy of the Document, free of added material.  If you use the
3276
     latter option, you must take reasonably prudent steps, when you
3277
     begin distribution of Opaque copies in quantity, to ensure that
3278
     this Transparent copy will remain thus accessible at the stated
3279
     location until at least one year after the last time you
3280
     distribute an Opaque copy (directly or through your agents or
3281
     retailers) of that edition to the public.
3282
 
3283
     It is requested, but not required, that you contact the authors of
3284
     the Document well before redistributing any large number of
3285
     copies, to give them a chance to provide you with an updated
3286
     version of the Document.
3287
 
3288
  4. MODIFICATIONS
3289
 
3290
     You may copy and distribute a Modified Version of the Document
3291
     under the conditions of sections 2 and 3 above, provided that you
3292
     release the Modified Version under precisely this License, with
3293
     the Modified Version filling the role of the Document, thus
3294
     licensing distribution and modification of the Modified Version to
3295
     whoever possesses a copy of it.  In addition, you must do these
3296
     things in the Modified Version:
3297
 
3298
       A. Use in the Title Page (and on the covers, if any) a title
3299
          distinct from that of the Document, and from those of
3300
          previous versions (which should, if there were any, be listed
3301
          in the History section of the Document).  You may use the
3302
          same title as a previous version if the original publisher of
3303
          that version gives permission.
3304
 
3305
       B. List on the Title Page, as authors, one or more persons or
3306
          entities responsible for authorship of the modifications in
3307
          the Modified Version, together with at least five of the
3308
          principal authors of the Document (all of its principal
3309
          authors, if it has fewer than five), unless they release you
3310
          from this requirement.
3311
 
3312
       C. State on the Title page the name of the publisher of the
3313
          Modified Version, as the publisher.
3314
 
3315
       D. Preserve all the copyright notices of the Document.
3316
 
3317
       E. Add an appropriate copyright notice for your modifications
3318
          adjacent to the other copyright notices.
3319
 
3320
       F. Include, immediately after the copyright notices, a license
3321
          notice giving the public permission to use the Modified
3322
          Version under the terms of this License, in the form shown in
3323
          the Addendum below.
3324
 
3325
       G. Preserve in that license notice the full lists of Invariant
3326
          Sections and required Cover Texts given in the Document's
3327
          license notice.
3328
 
3329
       H. Include an unaltered copy of this License.
3330
 
3331
       I. Preserve the section Entitled "History", Preserve its Title,
3332
          and add to it an item stating at least the title, year, new
3333
          authors, and publisher of the Modified Version as given on
3334
          the Title Page.  If there is no section Entitled "History" in
3335
          the Document, create one stating the title, year, authors,
3336
          and publisher of the Document as given on its Title Page,
3337
          then add an item describing the Modified Version as stated in
3338
          the previous sentence.
3339
 
3340
       J. Preserve the network location, if any, given in the Document
3341
          for public access to a Transparent copy of the Document, and
3342
          likewise the network locations given in the Document for
3343
          previous versions it was based on.  These may be placed in
3344
          the "History" section.  You may omit a network location for a
3345
          work that was published at least four years before the
3346
          Document itself, or if the original publisher of the version
3347
          it refers to gives permission.
3348
 
3349
       K. For any section Entitled "Acknowledgements" or "Dedications",
3350
          Preserve the Title of the section, and preserve in the
3351
          section all the substance and tone of each of the contributor
3352
          acknowledgements and/or dedications given therein.
3353
 
3354
       L. Preserve all the Invariant Sections of the Document,
3355
          unaltered in their text and in their titles.  Section numbers
3356
          or the equivalent are not considered part of the section
3357
          titles.
3358
 
3359
       M. Delete any section Entitled "Endorsements".  Such a section
3360
          may not be included in the Modified Version.
3361
 
3362
       N. Do not retitle any existing section to be Entitled
3363
          "Endorsements" or to conflict in title with any Invariant
3364
          Section.
3365
 
3366
       O. Preserve any Warranty Disclaimers.
3367
 
3368
     If the Modified Version includes new front-matter sections or
3369
     appendices that qualify as Secondary Sections and contain no
3370
     material copied from the Document, you may at your option
3371
     designate some or all of these sections as invariant.  To do this,
3372
     add their titles to the list of Invariant Sections in the Modified
3373
     Version's license notice.  These titles must be distinct from any
3374
     other section titles.
3375
 
3376
     You may add a section Entitled "Endorsements", provided it contains
3377
     nothing but endorsements of your Modified Version by various
3378
     parties--for example, statements of peer review or that the text
3379
     has been approved by an organization as the authoritative
3380
     definition of a standard.
3381
 
3382
     You may add a passage of up to five words as a Front-Cover Text,
3383
     and a passage of up to 25 words as a Back-Cover Text, to the end
3384
     of the list of Cover Texts in the Modified Version.  Only one
3385
     passage of Front-Cover Text and one of Back-Cover Text may be
3386
     added by (or through arrangements made by) any one entity.  If the
3387
     Document already includes a cover text for the same cover,
3388
     previously added by you or by arrangement made by the same entity
3389
     you are acting on behalf of, you may not add another; but you may
3390
     replace the old one, on explicit permission from the previous
3391
     publisher that added the old one.
3392
 
3393
     The author(s) and publisher(s) of the Document do not by this
3394
     License give permission to use their names for publicity for or to
3395
     assert or imply endorsement of any Modified Version.
3396
 
3397
  5. COMBINING DOCUMENTS
3398
 
3399
     You may combine the Document with other documents released under
3400
     this License, under the terms defined in section 4 above for
3401
     modified versions, provided that you include in the combination
3402
     all of the Invariant Sections of all of the original documents,
3403
     unmodified, and list them all as Invariant Sections of your
3404
     combined work in its license notice, and that you preserve all
3405
     their Warranty Disclaimers.
3406
 
3407
     The combined work need only contain one copy of this License, and
3408
     multiple identical Invariant Sections may be replaced with a single
3409
     copy.  If there are multiple Invariant Sections with the same name
3410
     but different contents, make the title of each such section unique
3411
     by adding at the end of it, in parentheses, the name of the
3412
     original author or publisher of that section if known, or else a
3413
     unique number.  Make the same adjustment to the section titles in
3414
     the list of Invariant Sections in the license notice of the
3415
     combined work.
3416
 
3417
     In the combination, you must combine any sections Entitled
3418
     "History" in the various original documents, forming one section
3419
     Entitled "History"; likewise combine any sections Entitled
3420
     "Acknowledgements", and any sections Entitled "Dedications".  You
3421
     must delete all sections Entitled "Endorsements."
3422
 
3423
  6. COLLECTIONS OF DOCUMENTS
3424
 
3425
     You may make a collection consisting of the Document and other
3426
     documents released under this License, and replace the individual
3427
     copies of this License in the various documents with a single copy
3428
     that is included in the collection, provided that you follow the
3429
     rules of this License for verbatim copying of each of the
3430
     documents in all other respects.
3431
 
3432
     You may extract a single document from such a collection, and
3433
     distribute it individually under this License, provided you insert
3434
     a copy of this License into the extracted document, and follow
3435
     this License in all other respects regarding verbatim copying of
3436
     that document.
3437
 
3438
  7. AGGREGATION WITH INDEPENDENT WORKS
3439
 
3440
     A compilation of the Document or its derivatives with other
3441
     separate and independent documents or works, in or on a volume of
3442
     a storage or distribution medium, is called an "aggregate" if the
3443
     copyright resulting from the compilation is not used to limit the
3444
     legal rights of the compilation's users beyond what the individual
3445
     works permit.  When the Document is included in an aggregate, this
3446
     License does not apply to the other works in the aggregate which
3447
     are not themselves derivative works of the Document.
3448
 
3449
     If the Cover Text requirement of section 3 is applicable to these
3450
     copies of the Document, then if the Document is less than one half
3451
     of the entire aggregate, the Document's Cover Texts may be placed
3452
     on covers that bracket the Document within the aggregate, or the
3453
     electronic equivalent of covers if the Document is in electronic
3454
     form.  Otherwise they must appear on printed covers that bracket
3455
     the whole aggregate.
3456
 
3457
  8. TRANSLATION
3458
 
3459
     Translation is considered a kind of modification, so you may
3460
     distribute translations of the Document under the terms of section
3461
     4.  Replacing Invariant Sections with translations requires special
3462
     permission from their copyright holders, but you may include
3463
     translations of some or all Invariant Sections in addition to the
3464
     original versions of these Invariant Sections.  You may include a
3465
     translation of this License, and all the license notices in the
3466
     Document, and any Warranty Disclaimers, provided that you also
3467
     include the original English version of this License and the
3468
     original versions of those notices and disclaimers.  In case of a
3469
     disagreement between the translation and the original version of
3470
     this License or a notice or disclaimer, the original version will
3471
     prevail.
3472
 
3473
     If a section in the Document is Entitled "Acknowledgements",
3474
     "Dedications", or "History", the requirement (section 4) to
3475
     Preserve its Title (section 1) will typically require changing the
3476
     actual title.
3477
 
3478
  9. TERMINATION
3479
 
3480
     You may not copy, modify, sublicense, or distribute the Document
3481
     except as expressly provided for under this License.  Any other
3482
     attempt to copy, modify, sublicense or distribute the Document is
3483
     void, and will automatically terminate your rights under this
3484
     License.  However, parties who have received copies, or rights,
3485
     from you under this License will not have their licenses
3486
     terminated so long as such parties remain in full compliance.
3487
 
3488
 10. FUTURE REVISIONS OF THIS LICENSE
3489
 
3490
     The Free Software Foundation may publish new, revised versions of
3491
     the GNU Free Documentation License from time to time.  Such new
3492
     versions will be similar in spirit to the present version, but may
3493
     differ in detail to address new problems or concerns.  See
3494
     `http://www.gnu.org/copyleft/'.
3495
 
3496
     Each version of the License is given a distinguishing version
3497
     number.  If the Document specifies that a particular numbered
3498
     version of this License "or any later version" applies to it, you
3499
     have the option of following the terms and conditions either of
3500
     that specified version or of any later version that has been
3501
     published (not as a draft) by the Free Software Foundation.  If
3502
     the Document does not specify a version number of this License,
3503
     you may choose any version ever published (not as a draft) by the
3504
     Free Software Foundation.
3505
 
3506
ADDENDUM: How to use this License for your documents
3507
====================================================
3508
 
3509
To use this License in a document you have written, include a copy of
3510
the License in the document and put the following copyright and license
3511
notices just after the title page:
3512
 
3513
       Copyright (C)  YEAR  YOUR NAME.
3514
       Permission is granted to copy, distribute and/or modify this document
3515
       under the terms of the GNU Free Documentation License, Version 1.2
3516
       or any later version published by the Free Software Foundation;
3517
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3518
       Texts.  A copy of the license is included in the section entitled ``GNU
3519
       Free Documentation License''.
3520
 
3521
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3522
replace the "with...Texts." line with this:
3523
 
3524
         with the Invariant Sections being LIST THEIR TITLES, with
3525
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3526
         being LIST.
3527
 
3528
If you have Invariant Sections without Cover Texts, or some other
3529
combination of the three, merge those two alternatives to suit the
3530
situation.
3531
 
3532
If your document contains nontrivial examples of program code, we
3533
recommend releasing these examples in parallel under your choice of
3534
free software license, such as the GNU General Public License, to
3535
permit their use in free software.
3536
 
3537

3538
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3539
 
3540
Index
3541
*****
3542
 
3543
 
3544
* Menu:
3545
3546
* --cumulative:                          Profiling Utility.   (line  26)
3547
* --debug-config:                        Standalone Simulator.
3548 385 jeremybenn
                                                              (line  86)
3549 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3550 127 jeremybenn
                                                              (line 105)
3551 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3552 127 jeremybenn
                                                              (line 118)
3553 124 jeremybenn
* --disable-debug:                       Configuring the Build.
3554 127 jeremybenn
                                                              (line  98)
3555 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3556 104 jeremybenn
                                                              (line  59)
3557 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3558 127 jeremybenn
                                                              (line 133)
3559 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3560 104 jeremybenn
                                                              (line  30)
3561 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3562 127 jeremybenn
                                                              (line  92)
3563
* --disable-unsigned-xori:               Configuring the Build.
3564 104 jeremybenn
                                                              (line  69)
3565 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3566 127 jeremybenn
                                                              (line 104)
3567 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3568 127 jeremybenn
                                                              (line 117)
3569 124 jeremybenn
* --enable-debug:                        Configuring the Build.
3570 127 jeremybenn
                                                              (line  97)
3571 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3572 104 jeremybenn
                                                              (line  58)
3573 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3574 104 jeremybenn
                                                              (line  37)
3575 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3576 385 jeremybenn
                                                              (line 120)
3577 19 jeremybenn
* --enable-ov-flag:                      Configuring the Build.
3578 127 jeremybenn
                                                              (line 132)
3579 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3580 385 jeremybenn
                                                              (line 117)
3581 19 jeremybenn
* --enable-profiling:                    Configuring the Build.
3582 104 jeremybenn
                                                              (line  29)
3583 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3584 127 jeremybenn
                                                              (line  91)
3585
* --enable-unsigned-xori:                Configuring the Build.
3586 104 jeremybenn
                                                              (line  68)
3587 19 jeremybenn
* --file:                                Standalone Simulator.
3588 385 jeremybenn
                                                              (line  44)
3589 19 jeremybenn
* --filename:                            Memory Profiling Utility.
3590
                                                              (line  51)
3591
* --generate:                            Profiling Utility.   (line  34)
3592
* --group:                               Memory Profiling Utility.
3593
                                                              (line  47)
3594
* --help:                                Standalone Simulator.
3595 346 jeremybenn
                                                              (line  21)
3596 19 jeremybenn
* --help (memory profiling utility):     Memory Profiling Utility.
3597
                                                              (line  22)
3598
* --help (profiling utility):            Profiling Utility.   (line  22)
3599
* --interactive:                         Standalone Simulator.
3600 346 jeremybenn
                                                              (line  25)
3601
* --memory:                              Standalone Simulator.
3602 385 jeremybenn
                                                              (line  70)
3603 19 jeremybenn
* --mode:                                Memory Profiling Utility.
3604
                                                              (line  26)
3605
* --nosrv:                               Standalone Simulator.
3606 385 jeremybenn
                                                              (line  52)
3607 346 jeremybenn
* --quiet <1>:                           Profiling Utility.   (line  30)
3608
* --quiet:                               Standalone Simulator.
3609
                                                              (line  29)
3610
* --report-memory-errors:                Standalone Simulator.
3611 385 jeremybenn
                                                              (line  91)
3612 19 jeremybenn
* --srv:                                 Standalone Simulator.
3613 385 jeremybenn
                                                              (line  60)
3614 19 jeremybenn
* --strict-npc:                          Standalone Simulator.
3615 385 jeremybenn
                                                              (line 100)
3616 420 jeremybenn
* --trace:                               Standalone Simulator.
3617
                                                              (line  39)
3618 346 jeremybenn
* --verbose:                             Standalone Simulator.
3619
                                                              (line  33)
3620 19 jeremybenn
* --version:                             Standalone Simulator.
3621 346 jeremybenn
                                                              (line  17)
3622 19 jeremybenn
* --version (memory profiling utility):  Memory Profiling Utility.
3623
                                                              (line  17)
3624
* --version (profiling utility):         Profiling Utility.   (line  17)
3625
* -c:                                    Profiling Utility.   (line  26)
3626
* -d:                                    Standalone Simulator.
3627 385 jeremybenn
                                                              (line  86)
3628 19 jeremybenn
* -f <1>:                                Memory Profiling Utility.
3629
                                                              (line  51)
3630
* -f:                                    Standalone Simulator.
3631 385 jeremybenn
                                                              (line  44)
3632 346 jeremybenn
* -g <1>:                                Memory Profiling Utility.
3633 19 jeremybenn
                                                              (line  47)
3634 346 jeremybenn
* -g:                                    Profiling Utility.   (line  34)
3635 19 jeremybenn
* -h:                                    Standalone Simulator.
3636 346 jeremybenn
                                                              (line  21)
3637 19 jeremybenn
* -h (memory profiling utility):         Memory Profiling Utility.
3638
                                                              (line  22)
3639
* -h (profiling utility):                Profiling Utility.   (line  22)
3640
* -i:                                    Standalone Simulator.
3641 346 jeremybenn
                                                              (line  25)
3642
* -m <1>:                                Memory Profiling Utility.
3643 19 jeremybenn
                                                              (line  26)
3644 346 jeremybenn
* -m:                                    Standalone Simulator.
3645 385 jeremybenn
                                                              (line  70)
3646 346 jeremybenn
* -q <1>:                                Profiling Utility.   (line  30)
3647
* -q:                                    Standalone Simulator.
3648
                                                              (line  29)
3649 420 jeremybenn
* -t:                                    Standalone Simulator.
3650
                                                              (line  39)
3651 346 jeremybenn
* -V:                                    Standalone Simulator.
3652
                                                              (line  33)
3653 19 jeremybenn
* -v:                                    Standalone Simulator.
3654 346 jeremybenn
                                                              (line  17)
3655 19 jeremybenn
* -v (memory profiling utility):         Memory Profiling Utility.
3656
                                                              (line  17)
3657
* -v (profiling utility):                Profiling Utility.   (line  17)
3658
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3659
                                                              (line  49)
3660
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3661
                                                              (line  55)
3662
* 0x02 UART VAPI sub-command (UART verification): Verification API.
3663
                                                              (line  59)
3664
* 0x03 UART VAPI sub-command (UART verification): Verification API.
3665
                                                              (line  62)
3666
* 0x04 UART VAPI sub-command (UART verification): Verification API.
3667
                                                              (line  66)
3668
* 16550 (UART configuration):            UART Configuration.  (line  73)
3669 82 jeremybenn
* all tests enabled:                     Configuring the Build.
3670 127 jeremybenn
                                                              (line 105)
3671 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
3672 127 jeremybenn
                                                              (line  98)
3673 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
3674
                                                              (line   6)
3675
* ATA/ATAPI device configuration:        Disc Interface Configuration.
3676 385 jeremybenn
                                                              (line  92)
3677 19 jeremybenn
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
3678
                                                              (line  32)
3679
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
3680 385 jeremybenn
                                                              (line  26)
3681 19 jeremybenn
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
3682
* baseaddr (Ethernet configuration):     Ethernet Configuration.
3683
                                                              (line  22)
3684
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
3685
                                                              (line  20)
3686
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
3687
                                                              (line  22)
3688
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
3689
* baseaddr (keyboard configuration):     Keyboard Configuration.
3690
                                                              (line  36)
3691
* baseaddr (memory configuration):       Memory Configuration.
3692 418 julius
                                                              (line  94)
3693 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
3694 385 jeremybenn
                                                              (line  55)
3695 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
3696
* baseaddr (VGA configuration):          Display Interface Configuration.
3697
                                                              (line  26)
3698
* blocksize (cache configuration):       Cache Configuration. (line  29)
3699
* BPB configuration:                     Branch Prediction Configuration.
3700
                                                              (line   6)
3701
* branch prediction configuration:       Branch Prediction Configuration.
3702
                                                              (line   6)
3703
* break (Interactive CLI):               Interactive Command Line.
3704
                                                              (line  57)
3705
* breakpoint list (Interactive CLI):     Interactive Command Line.
3706
                                                              (line  60)
3707
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
3708
                                                              (line  57)
3709
* breaks (Interactive CLI):              Interactive Command Line.
3710
                                                              (line  60)
3711
* btic (branch prediction configuration): Branch Prediction Configuration.
3712
                                                              (line  19)
3713
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3714
                                                              (line  48)
3715
* cache configuration:                   Cache Configuration. (line   6)
3716 346 jeremybenn
* calling_convention (CUC configuration): CUC Configuration.  (line  37)
3717 19 jeremybenn
* ce (memory configuration):             Memory Configuration.
3718 418 julius
                                                              (line 124)
3719 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
3720
* channel (UART configuration):          UART Configuration.  (line  29)
3721
* clear breakpoint (Interactive CLI):    Interactive Command Line.
3722
                                                              (line  57)
3723 432 jeremybenn
* clear_interrupt:                       Concepts.            (line  20)
3724 202 julius
* clkcycle (simulator configuration):    Simulator Behavior.  (line 115)
3725 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
3726
                                                              (line  54)
3727
* command line for Or1ksim standalone use: Standalone Simulator.
3728
                                                              (line   6)
3729
* complex model:                         Configuring the Build.
3730 104 jeremybenn
                                                              (line  37)
3731 19 jeremybenn
* config:                                Global Data Structures.
3732
                                                              (line   7)
3733
* config.bpb:                            Global Data Structures.
3734
                                                              (line  37)
3735
* config.cpu:                            Global Data Structures.
3736
                                                              (line  22)
3737
* config.cuc:                            Global Data Structures.
3738
                                                              (line  18)
3739
* config.dc:                             Global Data Structures.
3740
                                                              (line  25)
3741
* config.debug:                          Global Data Structures.
3742
                                                              (line  40)
3743
* config.pic:                            Global Data Structures.
3744
                                                              (line  33)
3745
* config.pm:                             Global Data Structures.
3746
                                                              (line  29)
3747
* config.sim:                            Global Data Structures.
3748
                                                              (line  11)
3749
* config.vapi:                           Global Data Structures.
3750
                                                              (line  14)
3751
* configuration dynamic structure:       Global Data Structures.
3752
                                                              (line  49)
3753
* configuration file structure:          Configuration File Format.
3754
                                                              (line   6)
3755
* configuration global structure:        Global Data Structures.
3756
                                                              (line   7)
3757
* configuration info (Interactive CLI):  Interactive Command Line.
3758
                                                              (line 119)
3759
* configuration of generic peripherals:  Generic Peripheral Configuration.
3760
                                                              (line   6)
3761
* configuration parameter setting (Interactive CLI): Interactive Command Line.
3762
                                                              (line 146)
3763
* configuring branch prediction:         Branch Prediction Configuration.
3764
                                                              (line   6)
3765
* configuring data & instruction caches: Cache Configuration. (line   6)
3766
* configuring data & instruction MMUs:   Memory Management Configuration.
3767
                                                              (line   6)
3768
* configuring DMA:                       DMA Configuration.   (line   6)
3769
* configuring memory:                    Memory Configuration.
3770
                                                              (line   6)
3771
* configuring Or1ksim:                   Configuration.       (line   6)
3772
* configuring power management:          Power Management Configuration.
3773
                                                              (line   6)
3774
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
3775
                                                              (line   6)
3776
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
3777
* configuring the CPU:                   CPU Configuration.   (line   6)
3778
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
3779
                                                              (line   6)
3780
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
3781
                                                              (line   6)
3782
* configuring the Ethernet interface:    Ethernet Configuration.
3783
                                                              (line   6)
3784
* configuring the frame buffer:          Frame Buffer Configuration.
3785
                                                              (line   6)
3786
* configuring the GPIO:                  GPIO Configuration.  (line   6)
3787
* configuring the interrupt controller:  Interrupt Configuration.
3788
                                                              (line   6)
3789
* configuring the keyboard interface:    Keyboard Configuration.
3790
                                                              (line   6)
3791
* configuring the memory controller:     Memory Controller Configuration.
3792
                                                              (line   6)
3793
* configuring the processor:             CPU Configuration.   (line   6)
3794
* configuring the PS2 interface:         Keyboard Configuration.
3795
                                                              (line   6)
3796
* configuring the UART:                  UART Configuration.  (line   6)
3797
* configuring the Verification API (VAPI): Verification API Configuration.
3798
                                                              (line   6)
3799
* configuring the VGA interface:         Display Interface Configuration.
3800
                                                              (line   6)
3801
* copying memory (Interactive CLI):      Interactive Command Line.
3802
                                                              (line  54)
3803
* CPU configuration:                     CPU Configuration.   (line   6)
3804
* CUC configuration:                     CUC Configuration.   (line   6)
3805
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
3806
                                                              (line 162)
3807
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
3808
* data cache configuration:              Cache Configuration. (line   6)
3809
* data MMU configuration:                Memory Management Configuration.
3810
                                                              (line   6)
3811
* DCGE (power management register):      Power Management Configuration.
3812
                                                              (line  21)
3813
* debug (Interactive CLI):               Interactive Command Line.
3814 346 jeremybenn
                                                              (line 151)
3815 19 jeremybenn
* debug (simulator configuration):       Simulator Behavior.  (line  13)
3816
* debug channel toggle (Interactive CLI): Interactive Command Line.
3817
                                                              (line 141)
3818
* debug interface configuration:         Debug Interface Configuration.
3819
                                                              (line   6)
3820
* debug mode toggle (Interactive CLI):   Interactive Command Line.
3821
                                                              (line 151)
3822
* debug unit configuration:              Debug Interface Configuration.
3823
                                                              (line   6)
3824
* Debug Unit verification (VAPI):        Verification API.    (line  34)
3825
* debugging enabled (Argtable2):         Configuring the Build.
3826 127 jeremybenn
                                                              (line  98)
3827 104 jeremybenn
* DejaGnu board configurations:          Regression Testing.  (line  35)
3828
* DejaGnu configuration:                 Regression Testing.  (line  21)
3829
* DejaGNU tests directories:             Regression Testing.  (line  50)
3830
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
3831 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
3832 418 julius
                                                              (line 144)
3833 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
3834 418 julius
                                                              (line 150)
3835 98 jeremybenn
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
3836 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
3837 385 jeremybenn
                                                              (line  40)
3838 19 jeremybenn
* disassemble (Interactive CLI):         Interactive Command Line.
3839
                                                              (line  41)
3840
* disc interface configuration:          Disc Interface Configuration.
3841
                                                              (line   6)
3842
* disc interface device configuration:   Disc Interface Configuration.
3843 385 jeremybenn
                                                              (line  92)
3844 19 jeremybenn
* display interface configuration:       Display Interface Configuration.
3845
                                                              (line   6)
3846
* displaying memory (Interactive CLI):   Interactive Command Line.
3847
                                                              (line  31)
3848
* displaying registers (Interactive CLI): Interactive Command Line.
3849
                                                              (line  14)
3850
* dm (Interactive CLI):                  Interactive Command Line.
3851
                                                              (line  31)
3852
* dma (Ethernet configuration):          Ethernet Configuration.
3853 346 jeremybenn
                                                              (line  33)
3854 19 jeremybenn
* DMA configuration:                     DMA Configuration.   (line   6)
3855
* DMA verification (VAPI):               Verification API.    (line  73)
3856
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
3857 385 jeremybenn
                                                              (line  74)
3858 19 jeremybenn
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3859 385 jeremybenn
                                                              (line  75)
3860 19 jeremybenn
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
3861 385 jeremybenn
                                                              (line  73)
3862 19 jeremybenn
* DME (power management register):       Power Management Configuration.
3863
                                                              (line  15)
3864
* DMMU configuration:                    Memory Management Configuration.
3865
                                                              (line   6)
3866
* doze mode (power management register): Power Management Configuration.
3867
                                                              (line  15)
3868
* dv (Interactive CLI):                  Interactive Command Line.
3869
                                                              (line 124)
3870
* dynamic clock gating (power management register): Power Management Configuration.
3871
                                                              (line  21)
3872
* dynamic model:                         Configuring the Build.
3873 104 jeremybenn
                                                              (line  37)
3874 19 jeremybenn
* dynamic ports, use of:                 Verification API Configuration.
3875
                                                              (line  23)
3876
* edge_trigger (interrupt controller):   Interrupt Configuration.
3877
                                                              (line  16)
3878 346 jeremybenn
* enable_bursts (CUC configuration):     CUC Configuration.   (line  41)
3879 19 jeremybenn
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
3880 385 jeremybenn
                                                              (line  22)
3881 19 jeremybenn
* enabled (branch prediction configuration): Branch Prediction Configuration.
3882
                                                              (line  15)
3883
* enabled (cache configuration):         Cache Configuration. (line  11)
3884
* enabled (debug interface configuration): Debug Interface Configuration.
3885
                                                              (line  11)
3886
* enabled (DMA configuration):           DMA Configuration.   (line  20)
3887
* enabled (Ethernet configuration):      Ethernet Configuration.
3888
                                                              (line  18)
3889
* enabled (frame buffer configuration):  Frame Buffer Configuration.
3890
                                                              (line  16)
3891
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
3892
                                                              (line  18)
3893
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
3894
* enabled (interrupt controller):        Interrupt Configuration.
3895
                                                              (line  12)
3896
* enabled (keyboard configuration):      Keyboard Configuration.
3897
                                                              (line  32)
3898
* enabled (memory controller configuration): Memory Controller Configuration.
3899 385 jeremybenn
                                                              (line  44)
3900 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
3901
                                                              (line  12)
3902
* enabled (power management configuration): Power Management Configuration.
3903
                                                              (line  35)
3904
* enabled (UART configuration):          UART Configuration.  (line  18)
3905
* enabled (verification API configuration): Verification API Configuration.
3906
                                                              (line  15)
3907
* enabled (VGA configuration):           Display Interface Configuration.
3908
                                                              (line  22)
3909
* enabling Ethernet via socket:          Configuring the Build.
3910 104 jeremybenn
                                                              (line  59)
3911 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
3912
                                                              (line  32)
3913
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
3914
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
3915
* Ethernet configuration:                Ethernet Configuration.
3916
                                                              (line   6)
3917
* Ethernet verification (VAPI):          Verification API.    (line  78)
3918
* Ethernet via socket, enabling:         Configuring the Build.
3919 104 jeremybenn
                                                              (line  59)
3920 127 jeremybenn
* exclusive-OR immediate operand:        Configuring the Build.
3921
                                                              (line  69)
3922 202 julius
* exe_bin_insn_log (simulator configuration): Simulator Behavior.
3923
                                                              (line 103)
3924
* exe_bin_insn_log_file (simulator configuration): Simulator Behavior.
3925
                                                              (line 111)
3926 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
3927
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
3928
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
3929 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
3930 82 jeremybenn
                                                              (line  97)
3931 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
3932 82 jeremybenn
                                                              (line  93)
3933 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
3934 82 jeremybenn
                                                              (line  86)
3935
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
3936 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
3937 82 jeremybenn
                                                              (line  58)
3938 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
3939 82 jeremybenn
                                                              (line  62)
3940 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
3941 82 jeremybenn
                                                              (line  69)
3942 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
3943 82 jeremybenn
                                                              (line  74)
3944 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
3945
                                                              (line  23)
3946
* execution history (Interactive CLI):   Interactive Command Line.
3947
                                                              (line  67)
3948
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
3949 385 jeremybenn
                                                              (line 108)
3950 19 jeremybenn
* file (keyboard configuration):         Keyboard Configuration.
3951
                                                              (line  51)
3952
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
3953 82 jeremybenn
                                                              (line  36)
3954 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
3955
                                                              (line  47)
3956
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
3957 385 jeremybenn
                                                              (line 121)
3958 19 jeremybenn
* flag setting by instructions:          Configuring the Build.
3959 127 jeremybenn
                                                              (line 118)
3960 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
3961
                                                              (line   6)
3962
* generic peripheral configuration:      Generic Peripheral Configuration.
3963
                                                              (line   6)
3964
* GPIO configuration:                    GPIO Configuration.  (line   6)
3965
* GPIO verification (VAPI):              Verification API.    (line  88)
3966
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
3967
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
3968
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
3969
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
3970
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
3971
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
3972
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
3973 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
3974 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
3975 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
3976 385 jeremybenn
                                                              (line 125)
3977 19 jeremybenn
* help (Interactive CLI):                Interactive Command Line.
3978
                                                              (line 170)
3979
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
3980
                                                              (line 133)
3981
* hide_device_id (verification API configuration): Verification API Configuration.
3982
                                                              (line  36)
3983
* hist (Interactive CLI):                Interactive Command Line.
3984
                                                              (line  67)
3985 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
3986 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
3987
                                                              (line  67)
3988
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
3989
                                                              (line  33)
3990
* hitdelay (instruction cache configuration): Cache Configuration.
3991
                                                              (line  38)
3992
* hitdelay (MMU configuration):          Memory Management Configuration.
3993
                                                              (line  51)
3994 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
3995 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3996
                                                              (line  49)
3997
* IMMU configuration:                    Memory Management Configuration.
3998
                                                              (line   6)
3999
* index (memory controller configuration): Memory Controller Configuration.
4000 385 jeremybenn
                                                              (line  77)
4001 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
4002
                                                              (line 119)
4003
* installing Or1ksim:                    Installation.        (line   6)
4004
* instruction cache configuration:       Cache Configuration. (line   6)
4005
* instruction MMU configuration:         Memory Management Configuration.
4006
                                                              (line   6)
4007
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
4008
* instruction profiling utility (Interactive CLI): Interactive Command Line.
4009
                                                              (line 178)
4010
* internal debugging:                    Internal Debugging.  (line   6)
4011
* interrupt controller configuration:    Interrupt Configuration.
4012
                                                              (line   6)
4013 432 jeremybenn
* interrupts:                            Concepts.            (line  20)
4014 19 jeremybenn
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
4015 385 jeremybenn
                                                              (line  36)
4016 19 jeremybenn
* irq (DMA configuration):               DMA Configuration.   (line  34)
4017
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
4018
* irq (keyboard configuration):          Keyboard Configuration.
4019
                                                              (line  47)
4020
* irq (UART configuration):              UART Configuration.  (line  70)
4021
* irq (VGA configuration):               Display Interface Configuration.
4022
                                                              (line  37)
4023
* jitter (UART configuration):           UART Configuration.  (line  78)
4024
* keyboard configuration:                Keyboard Configuration.
4025
                                                              (line   6)
4026
* library version of Or1ksim:            Simulator Library.   (line   6)
4027
* license for Or1ksim:                   GNU Free Documentation License.
4028
                                                              (line   6)
4029
* list breakpoints (Interactive CLI):    Interactive Command Line.
4030
                                                              (line  60)
4031
* load_hitdelay (data cache configuration): Cache Configuration.
4032
                                                              (line  46)
4033
* load_missdelay (data cache configuration): Cache Configuration.
4034
                                                              (line  50)
4035
* log (memory configuration):            Memory Configuration.
4036 418 julius
                                                              (line 156)
4037 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
4038
                                                              (line  28)
4039 432 jeremybenn
* long:                                  Simulator Library.   (line  94)
4040 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
4041 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
4042 418 julius
                                                              (line 133)
4043 19 jeremybenn
* memory configuration:                  Memory Configuration.
4044
                                                              (line   6)
4045
* memory controller configuration:       Memory Controller Configuration.
4046
                                                              (line   6)
4047
* memory copying (Interactive CLI):      Interactive Command Line.
4048
                                                              (line  54)
4049
* memory display (Interactive CLI):      Interactive Command Line.
4050
                                                              (line  31)
4051
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
4052
                                                              (line 133)
4053
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
4054
                                                              (line 124)
4055
* memory patching (Interactive CLI):     Interactive Command Line.
4056
                                                              (line  48)
4057
* memory profiling end address:          Memory Profiling Utility.
4058
                                                              (line  56)
4059
* memory profiling start address:        Memory Profiling Utility.
4060
                                                              (line  56)
4061
* memory profiling utility (Interactive CLI): Interactive Command Line.
4062
                                                              (line 173)
4063
* memory profiling version of Or1ksim:   Memory Profiling Utility.
4064
                                                              (line   6)
4065
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
4066 346 jeremybenn
* memory_order=exact (CUC configuration): CUC Configuration.  (line  30)
4067 19 jeremybenn
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
4068 346 jeremybenn
* memory_order=strong (CUC configuration): CUC Configuration. (line  27)
4069
* memory_order=weak (CUC configuration): CUC Configuration.   (line  22)
4070 19 jeremybenn
* missdelay (branch prediction configuration): Branch Prediction Configuration.
4071
                                                              (line  37)
4072
* missdelay (instruction cache configuration): Cache Configuration.
4073
                                                              (line  42)
4074
* missdelay (MMU configuration):         Memory Management Configuration.
4075
                                                              (line  55)
4076
* MMU configuration:                     Memory Management Configuration.
4077
                                                              (line   6)
4078 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
4079 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
4080 82 jeremybenn
                                                              (line  34)
4081 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
4082 346 jeremybenn
                                                              (line 173)
4083 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
4084 432 jeremybenn
* mtspr:                                 Concepts.            (line  20)
4085 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
4086 385 jeremybenn
                                                              (line 132)
4087 19 jeremybenn
* name (generic peripheral configuration): Generic Peripheral Configuration.
4088
                                                              (line  42)
4089
* name (memory configuration):           Memory Configuration.
4090 418 julius
                                                              (line 115)
4091 346 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  45)
4092 19 jeremybenn
* nsets (cache configuration):           Cache Configuration. (line  15)
4093
* nsets (MMU configuration):             Memory Management Configuration.
4094
                                                              (line  16)
4095
* nways (cache configuration):           Cache Configuration. (line  22)
4096
* nways (MMU configuration):             Memory Management Configuration.
4097
                                                              (line  22)
4098 432 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  84)
4099
* or1ksim_init:                          Simulator Library.   (line  19)
4100
* or1ksim_interrupt:                     Simulator Library.   (line  99)
4101
* or1ksim_interrupt_clear:               Simulator Library.   (line 121)
4102
* or1ksim_interrupt_set:                 Simulator Library.   (line 110)
4103
* or1ksim_is_le:                         Simulator Library.   (line  89)
4104
* or1ksim_jtag_reset:                    Simulator Library.   (line 130)
4105
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 152)
4106
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 139)
4107
* or1ksim_read_mem:                      Simulator Library.   (line 165)
4108
* or1ksim_read_reg:                      Simulator Library.   (line 197)
4109 346 jeremybenn
* or1ksim_read_spr:                      Simulator Library.   (line 181)
4110 432 jeremybenn
* or1ksim_reset_duration:                Simulator Library.   (line  69)
4111
* or1ksim_run:                           Simulator Library.   (line  58)
4112
* or1ksim_set_stall_state:               Simulator Library.   (line 212)
4113
* or1ksim_set_time_point:                Simulator Library.   (line  80)
4114
* or1ksim_write_mem:                     Simulator Library.   (line 173)
4115
* or1ksim_write_reg:                     Simulator Library.   (line 205)
4116
* or1ksim_write_spr:                     Simulator Library.   (line 189)
4117 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
4118
* overflow flag setting by instructions: Configuring the Build.
4119 127 jeremybenn
                                                              (line 133)
4120 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
4121 385 jeremybenn
                                                              (line 117)
4122 19 jeremybenn
* pagesize (MMU configuration):          Memory Management Configuration.
4123
                                                              (line  27)
4124
* patching memory (Interactive CLI):     Interactive Command Line.
4125
                                                              (line  48)
4126
* patching registers (Interactive CLI):  Interactive Command Line.
4127
                                                              (line  28)
4128
* patching the program counter (Interactive CLI): Interactive Command Line.
4129
                                                              (line  51)
4130
* pattern (memory configuration):        Memory Configuration.
4131 418 julius
                                                              (line  82)
4132 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
4133
                                                              (line  51)
4134 429 julius
* phy_addr:                              Ethernet Configuration.
4135
                                                              (line  94)
4136 19 jeremybenn
* PIC configuration:                     Interrupt Configuration.
4137
                                                              (line   6)
4138
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
4139 385 jeremybenn
                                                              (line 136)
4140 19 jeremybenn
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
4141 385 jeremybenn
                                                              (line  55)
4142 19 jeremybenn
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
4143 385 jeremybenn
                                                              (line  56)
4144 19 jeremybenn
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
4145 385 jeremybenn
                                                              (line  57)
4146 19 jeremybenn
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4147 385 jeremybenn
                                                              (line  58)
4148 19 jeremybenn
* pm (Interactive CLI):                  Interactive Command Line.
4149
                                                              (line  48)
4150
* PMR - DGCE:                            Power Management Configuration.
4151
                                                              (line  21)
4152
* PMR - DME:                             Power Management Configuration.
4153
                                                              (line  15)
4154
* PMR - SDF:                             Power Management Configuration.
4155
                                                              (line  12)
4156
* PMR - SME:                             Power Management Configuration.
4157
                                                              (line  16)
4158
* PMR - SUME:                            Power Management Configuration.
4159
                                                              (line  24)
4160
* PMU configuration:                     Power Management Configuration.
4161
                                                              (line   6)
4162
* poc (memory controller configuration): Memory Controller Configuration.
4163 385 jeremybenn
                                                              (line  64)
4164 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4165
                                                              (line  23)
4166
* power management configuration:        Power Management Configuration.
4167
                                                              (line   6)
4168
* power management register, DGCE:       Power Management Configuration.
4169
                                                              (line  21)
4170
* power management register, DME:        Power Management Configuration.
4171
                                                              (line  15)
4172
* power management register, SDF:        Power Management Configuration.
4173
                                                              (line  12)
4174
* power management register, SME:        Power Management Configuration.
4175
                                                              (line  16)
4176
* power management register, SUME:       Power Management Configuration.
4177
                                                              (line  24)
4178
* pr (Interactive CLI):                  Interactive Command Line.
4179
                                                              (line  28)
4180
* private ports, use of:                 Verification API Configuration.
4181
                                                              (line  23)
4182
* processor configuration:               CPU Configuration.   (line   6)
4183
* processor stall (Interactive CLI):     Interactive Command Line.
4184
                                                              (line  72)
4185
* processor unstall (Interactive CLI):   Interactive Command Line.
4186
                                                              (line  78)
4187
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4188
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4189
                                                              (line  23)
4190
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4191
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4192
* profiling utility (Interactive CLI):   Interactive Command Line.
4193
                                                              (line 178)
4194
* program counter patching (Interactive CLI): Interactive Command Line.
4195
                                                              (line  51)
4196
* programmable interrupt controller configuration: Interrupt Configuration.
4197
                                                              (line   6)
4198
* PS2 configuration:                     Keyboard Configuration.
4199
                                                              (line   6)
4200
* q (Interactive CLI):                   Interactive Command Line.
4201
                                                              (line  11)
4202
* quitting (Interactive CLI):            Interactive Command Line.
4203
                                                              (line  11)
4204
* r (Interactive CLI):                   Interactive Command Line.
4205
                                                              (line  14)
4206
* random_seed (memory configuration):    Memory Configuration.
4207 418 julius
                                                              (line  72)
4208 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4209 82 jeremybenn
                                                              (line  30)
4210 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4211
                                                              (line  41)
4212
* reg_sim_reset:                         Concepts.            (line  13)
4213
* register display (Interactive CLI):    Interactive Command Line.
4214
                                                              (line  14)
4215
* register over time statistics:         Configuring the Build.
4216 127 jeremybenn
                                                              (line  92)
4217 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4218
                                                              (line  28)
4219 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4220 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4221
                                                              (line  20)
4222 235 jeremybenn
* Remote Serial Protocol, --nosrv:       Standalone Simulator.
4223 385 jeremybenn
                                                              (line  52)
4224 235 jeremybenn
* Remote Serial Protocol, --srv:         Standalone Simulator.
4225 385 jeremybenn
                                                              (line  60)
4226 432 jeremybenn
* report_interrupt:                      Concepts.            (line  20)
4227 19 jeremybenn
* reset (Interactive CLI):               Interactive Command Line.
4228
                                                              (line  63)
4229
* reset hooks:                           Concepts.            (line  13)
4230
* reset the simulator (Interactive CLI): Interactive Command Line.
4231
                                                              (line  63)
4232
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4233 385 jeremybenn
                                                              (line  48)
4234 19 jeremybenn
* rev (CPU configuration):               CPU Configuration.   (line  15)
4235
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4236
                                                              (line  20)
4237
* rsp_port (debug interface configuration): Debug Interface Configuration.
4238 235 jeremybenn
                                                              (line  32)
4239 19 jeremybenn
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4240
                                                              (line  46)
4241
* run (Interactive CLI):                 Interactive Command Line.
4242
                                                              (line  23)
4243
* running code (Interactive CLI):        Interactive Command Line.
4244
                                                              (line  23)
4245
* running Or1ksim:                       Usage.               (line   6)
4246
* runtime:                               Global Data Structures.
4247
                                                              (line  58)
4248
* runtime global structure:              Global Data Structures.
4249
                                                              (line  58)
4250
* runtime.cpu:                           Global Data Structures.
4251
                                                              (line  62)
4252
* runtime.cpu.fout:                      Concepts.            (line   7)
4253
* runtime.cuc:                           Global Data Structures.
4254
                                                              (line  62)
4255
* runtime.vapi:                          Global Data Structures.
4256
                                                              (line  62)
4257
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4258
                                                              (line  59)
4259
* rxfile (Ethernet configuration):       Ethernet Configuration.
4260
                                                              (line  68)
4261
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4262
                                                              (line  23)
4263
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4264
                                                              (line  28)
4265 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4266 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4267
                                                              (line  12)
4268
* section ata:                           Disc Interface Configuration.
4269
                                                              (line   6)
4270
* section bpb:                           Branch Prediction Configuration.
4271
                                                              (line   6)
4272
* section cpio:                          GPIO Configuration.  (line   6)
4273
* section cpu:                           CPU Configuration.   (line   6)
4274
* section cuc:                           CUC Configuration.   (line   6)
4275
* section dc:                            Cache Configuration. (line   6)
4276
* section debug:                         Debug Interface Configuration.
4277
                                                              (line   6)
4278
* section dma:                           DMA Configuration.   (line   6)
4279
* section dmmu:                          Memory Management Configuration.
4280
                                                              (line   6)
4281
* section ethernet:                      Ethernet Configuration.
4282
                                                              (line   6)
4283
* section fb:                            Frame Buffer Configuration.
4284
                                                              (line   6)
4285
* section generic:                       Generic Peripheral Configuration.
4286
                                                              (line   6)
4287
* section ic:                            Cache Configuration. (line   6)
4288
* section immu:                          Memory Management Configuration.
4289
                                                              (line   6)
4290
* section kb:                            Keyboard Configuration.
4291
                                                              (line   6)
4292
* section mc:                            Memory Controller Configuration.
4293
                                                              (line   6)
4294
* section memory:                        Memory Configuration.
4295
                                                              (line   6)
4296
* section pic:                           Interrupt Configuration.
4297
                                                              (line   6)
4298
* section pmu:                           Power Management Configuration.
4299
                                                              (line   6)
4300
* section sim:                           Simulator Behavior.  (line   6)
4301
* section uart:                          UART Configuration.  (line   6)
4302
* section vapi:                          Verification API Configuration.
4303
                                                              (line   6)
4304
* section vga:                           Display Interface Configuration.
4305
                                                              (line   6)
4306
* sections:                              Global Data Structures.
4307
                                                              (line  49)
4308
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4309 385 jeremybenn
                                                              (line 129)
4310 19 jeremybenn
* server_port (verification API configuration): Verification API Configuration.
4311
                                                              (line  19)
4312
* set (Interactive CLI):                 Interactive Command Line.
4313
                                                              (line 146)
4314
* set breakpoint (Interactive CLI):      Interactive Command Line.
4315
                                                              (line  57)
4316
* setdbch (Interactive CLI):             Interactive Command Line.
4317
                                                              (line 141)
4318
* simple model:                          Configuring the Build.
4319 104 jeremybenn
                                                              (line  37)
4320 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4321
* simulator configuration info (Interactive CLI): Interactive Command Line.
4322
                                                              (line 119)
4323
* simulator reset (Interactive CLI):     Interactive Command Line.
4324
                                                              (line  63)
4325
* simulator statistics (Interactive CLI): Interactive Command Line.
4326
                                                              (line  83)
4327
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4328 385 jeremybenn
                                                              (line 113)
4329 19 jeremybenn
* size (generic peripheral configuration): Generic Peripheral Configuration.
4330
                                                              (line  30)
4331
* size (memory configuration):           Memory Configuration.
4332 418 julius
                                                              (line  99)
4333 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4334
                                                              (line  16)
4335
* slow down factor (power management register): Power Management Configuration.
4336
                                                              (line  12)
4337
* SME (power management register):       Power Management Configuration.
4338
                                                              (line  16)
4339
* sockif (Ethernet configuration):       Ethernet Configuration.
4340
                                                              (line  83)
4341
* sr (CPU configuration):                CPU Configuration.   (line  53)
4342
* stall (Interactive CLI):               Interactive Command Line.
4343
                                                              (line  72)
4344
* stall the processor (Interactive CLI): Interactive Command Line.
4345
                                                              (line  72)
4346
* statistics, register over time:        Configuring the Build.
4347 127 jeremybenn
                                                              (line  92)
4348 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4349
                                                              (line  83)
4350
* stats (Interactive CLI):               Interactive Command Line.
4351
                                                              (line  83)
4352
* stepping code (Interactive CLI):       Interactive Command Line.
4353
                                                              (line  19)
4354
* store_hitdelay (data cache configuration): Cache Configuration.
4355
                                                              (line  54)
4356
* store_missdelay (data cache configuration): Cache Configuration.
4357
                                                              (line  58)
4358
* SUME (power management register):      Power Management Configuration.
4359
                                                              (line  24)
4360 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4361 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4362
                                                              (line  24)
4363
* t (Interactive CLI):                   Interactive Command Line.
4364
                                                              (line  19)
4365 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4366 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4367
                                                              (line  23)
4368
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4369 235 jeremybenn
                                                              (line  37)
4370 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4371
* test code for target:                  Regression Testing.  (line  63)
4372
* test make file:                        Regression Testing.  (line  27)
4373
* test README:                           Regression Testing.  (line  32)
4374
* testing:                               Regression Testing.  (line   6)
4375 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4376 127 jeremybenn
                                                              (line 105)
4377 346 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  49)
4378 19 jeremybenn
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4379 346 jeremybenn
                                                              (line  49)
4380 19 jeremybenn
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4381
                                                              (line  57)
4382
* toggle debug channels (Interactive CLI): Interactive Command Line.
4383
                                                              (line 141)
4384
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4385
                                                              (line 151)
4386
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4387
                                                              (line  60)
4388
* txfile (Ethernet configuration):       Ethernet Configuration.
4389
                                                              (line  69)
4390
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4391 82 jeremybenn
                                                              (line  36)
4392 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4393
                                                              (line  47)
4394
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4395 385 jeremybenn
                                                              (line 103)
4396 19 jeremybenn
* type (memory configuration):           Memory Configuration.
4397 385 jeremybenn
                                                              (line  37)
4398 418 julius
* type=exitnops (memory configuration):  Memory Configuration.
4399 420 jeremybenn
                                                              (line  66)
4400 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4401 385 jeremybenn
                                                              (line  47)
4402 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4403 385 jeremybenn
                                                              (line  41)
4404 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4405 385 jeremybenn
                                                              (line  51)
4406 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4407 385 jeremybenn
                                                              (line  56)
4408 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4409
* UART I/O from/to a physical serial port: UART Configuration.
4410
                                                              (line  62)
4411
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4412
* UART I/O from/to files:                UART Configuration.  (line  33)
4413
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4414
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4415
* UART verification (VAPI):              Verification API.    (line  41)
4416
* unstall (Interactive CLI):             Interactive Command Line.
4417
                                                              (line  78)
4418
* unstall the processor (Interactive CLI): Interactive Command Line.
4419
                                                              (line  78)
4420
* upr (CPU configuration):               CPU Configuration.   (line  21)
4421 432 jeremybenn
* use_nmi (interrupt controller):        Interrupt Configuration.
4422
                                                              (line  30)
4423 19 jeremybenn
* ustates (cache configuration):         Cache Configuration. (line  33)
4424
* ustates (MMU configuration):           Memory Management Configuration.
4425
                                                              (line  41)
4426
* VAPI configuration:                    Verification API Configuration.
4427
                                                              (line   6)
4428
* VAPI for Debug Unit:                   Verification API.    (line  34)
4429
* VAPI for DMA:                          Verification API.    (line  73)
4430
* VAPI for Ethernet:                     Verification API.    (line  78)
4431
* VAPI for GPIO:                         Verification API.    (line  88)
4432
* VAPI for UART:                         Verification API.    (line  41)
4433
* vapi_id (debug interface configuration): Debug Interface Configuration.
4434 235 jeremybenn
                                                              (line  43)
4435 346 jeremybenn
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4436 19 jeremybenn
                                                              (line  88)
4437 346 jeremybenn
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4438 19 jeremybenn
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4439
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4440
* vapi_log_file (verification API configuration): Verification API Configuration.
4441
                                                              (line  41)
4442
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4443
                                                              (line  41)
4444
* ver (CPU configuration):               CPU Configuration.   (line  15)
4445
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4446
* Verification API configuration:        Verification API Configuration.
4447
                                                              (line   6)
4448
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4449
                                                              (line 124)
4450
* VGA configuration:                     Display Interface Configuration.
4451
 
4452
 
4453
                                                              (line  50)
4454
4455
4456

4457
Tag Table:
4458 432 jeremybenn
Node: Top814
4459
Node: Installation1224
4460
Node: Preparation1471
4461
Node: Configuring the Build1766
4462
Node: Build and Install7910
4463
Node: Known Issues8688
4464
Node: Usage9743
4465
Node: Standalone Simulator9957
4466
Node: Profiling Utility14521
4467
Node: Memory Profiling Utility15431
4468
Node: Simulator Library16796
4469
Node: Configuration27201
4470
Node: Configuration File Format27813
4471
Node: Configuration File Preprocessing28198
4472
Node: Configuration File Syntax28495
4473
Node: Simulator Configuration31280
4474
Node: Simulator Behavior31571
4475
Node: Verification API Configuration36152
4476
Node: CUC Configuration38092
4477
Node: Core OpenRISC Configuration40084
4478
Node: CPU Configuration40586
4479
Node: Memory Configuration44705
4480
Node: Memory Management Configuration51427
4481
Node: Cache Configuration53804
4482
Node: Interrupt Configuration56190
4483
Node: Power Management Configuration58023
4484
Node: Branch Prediction Configuration59300
4485
Node: Debug Interface Configuration60660
4486
Node: Peripheral Configuration63003
4487
Node: Memory Controller Configuration63629
4488
Node: UART Configuration67409
4489
Node: DMA Configuration70928
4490
Node: Ethernet Configuration72795
4491
Node: GPIO Configuration76877
4492
Node: Display Interface Configuration78510
4493
Node: Frame Buffer Configuration80819
4494
Node: Keyboard Configuration82683
4495
Node: Disc Interface Configuration84921
4496
Node: Generic Peripheral Configuration90025
4497
Node: Interactive Command Line92320
4498
Node: Verification API99294
4499
Node: Code Internals103724
4500
Node: Coding Conventions104307
4501
Node: Global Data Structures108734
4502
Node: Concepts111391
4503
Ref: Output Redirection111536
4504
Ref: Interrupts Internal112074
4505
Node: Internal Debugging113227
4506
Node: Regression Testing113751
4507
Node: GNU Free Documentation License117540

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